TL H 8358
TL081
Wide
Bandwidth
JFET
Input
Operational
Amplifier
December 1995
TL081 Wide Bandwidth JFET
Input Operational Amplifier
General Description
The TL081 is a low cost high speed JFET input operational
amplifier with an internally trimmed input offset voltage
(BI-FET II
TM
technology) The device requires a low supply
current and yet maintains a large gain bandwidth product
and a fast slew rate In addition well matched high voltage
JFET input devices provide very low input bias and offset
currents The TL081 is pin compatible with the standard
LM741 and uses the same offset voltage adjustment circuit-
ry This feature allows designers to immediately upgrade the
overall performance of existing LM741 designs
The TL081 may be used in applications such as high speed
integrators fast D A converters sample-and-hold circuits
and many other circuits requiring low input offset voltage
low input bias current high input impedance high slew rate
and wide bandwidth The devices has low noise and offset
voltage drift but for applications where these requirements
are critical the LF356 is recommended If maximum supply
current is important however the TL081C is the better
choice
Features
Y
Internally trimmed offset voltage
15 mV
Y
Low input bias current
50 pA
Y
Low input noise voltage
25 nV
0
Hz
Y
Low input noise current
0 01 pA
0
Hz
Y
Wide gain bandwidth
4 MHz
Y
High slew rate
13 V ms
Y
Low supply current
1 8 mA
Y
High input impedance
10
12
X
Y
Low total harmonic distortion A
V
e
10
k
0 02%
R
L
e
10k V
O
e
20 Vp-p
BW
e
20 Hz
b
20 kHz
Y
Low 1 f noise corner
50 Hz
Y
Fast settling time to 0 01%
2 ms
Typical Connection
TL H 8358 1
Connection Diagram
Simplified Schematic
TL H 8358 2
Dual-In-Line Package
TL H 8358 4
Order Number TL081CP
See NS Package Number N08E
BI-FET II
TM
is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation
RRD-B30M125 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
g
18V
Power Dissipation (Notes 1 and 6)
670 mW
Operating Temperature Range
0 C to
a
70 C
T
j(MAX)
115 C
Differential Input Voltage
g
30V
Input Voltage Range (Note 2)
g
15V
Output Short Circuit Duration
Continuous
Storage Temperature Range
b
65 C to
a
150 C
Lead Temp (Soldering 10 seconds)
260 C
i
jA
120 C W
ESD rating to be determined
DC Electrical Characteristics
(Note 3)
Symbol
Parameter
Conditions
TL081C
Units
Min
Typ
Max
V
OS
Input Offset Voltage
R
S
e
10 kX T
A
e
25 C
5
15
mV
Over Temperature
20
mV
D
V
OS
D
T
Average TC of Input Offset
R
S
e
10 kX
10
m
V C
Voltage
I
OS
Input Offset Current
T
j
e
25 C (Notes 3 4)
25
100
pA
T
j
s
70 C
4
nA
I
B
Input Bias Current
T
j
e
25 C (Notes 3 4)
50
200
pA
T
j
s
70 C
8
nA
R
IN
Input Resistance
T
j
e
25 C
10
12
X
A
VOL
Large Signal Voltage Gain
V
S
e
g
15V T
A
e
25 C
25
100
V mV
V
O
e
g
10V R
L
e
2 kX
Over Temperature
15
V mV
V
O
Output Voltage Swing
V
S
e
g
15V R
L
e
10 kX
g
12
g
13 5
V
V
CM
Input Common-Mode Voltage
V
S
e
g
15V
g
11
a
15
V
Range
b
12
V
CMRR
Common-Mode Rejection Ratio
R
S
s
10 kX
70
100
dB
PSRR
Supply Voltage Rejection Ratio
(Note 5)
70
100
dB
I
S
Supply Current
1 8
2 8
mA
AC Electrical Characteristics
(Note 3)
Symbol
Parameter
Conditions
TL081C
Units
Min
Typ
Max
SR
Slew Rate
V
S
e
g
15V T
A
e
25 C
13
V ms
GBW
Gain Bandwidth Product
V
S
e
g
15V T
A
e
25 C
4
MHz
e
n
Equivalent Input Noise Voltage
T
A
e
25 C R
S
e
100X
25
nV
0
Hz
f
e
1000 Hz
i
n
Equivalent Input Noise Current
T
j
e
25 C f
e
1000 Hz
0 01
pA
0
Hz
Note 1
For operating at elevated temperature the device must be derated based on a thermal resistance of 120 C W junction to ambient for N package
Note 2
Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage
Note 3
These specifications apply for V
S
e g
15V and 0 C
s
T
A
s a
70 C V
OS
I
B
and I
OS
are measured at V
CM
e
0
Note 4
The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature T
j
Due to the limited
production test time the input bias currents measured are correlated to junction temperature In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation P
D
T
j
e
T
A
a
i
jA
P
D
where i
jA
is the thermal resistance from junction to ambient Use of a heat sink is
recommended if input bias current is to be kept to a minimum
Note 5
Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice from
V
S
e g
5V to
g
15V
Note 6
Max Power Dissipation is defined by the package characteristics Operating the part near the Max Power Dissipation may cause the part to operate
outside guaranteed limits
2
Typical Performance Characteristics
(Continued)
Distortion vs Frequency
Undistorted Output Voltage
Swing
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
Open Loop Voltage Gain (V V)
Output Impedance
Inverter Settling Time
TL H 8358 6
4
Pulse Response
Small Signal Inverting
TL H 8358 7
Small Signal Non-Inverting
TL H 8358 13
Large Signal Inverting
TL H 8358 14
Large Signal Non-Inverting
TL H 8358 15
Current Limit (R
L
e
100X)
TL H 8358 16
Application Hints
The TL081 is an op amp with an internally trimmed input
offset voltage and JFET input devices (BI-FET II) These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs Therefore large differential input voltages can easily
be accommodated without a large increase in input current
The maximum differential input voltage is independent of
the supply voltages However neither of the input voltages
should be allowed to exceed the negative supply as this
will cause large currents to flow which can result in a de-
stroyed unit
Exceeding the negative common-mode limit on either input
will force the output to a high state potentially causing a
reversal of phase to the output
Exceeding the negative common-mode limit on both inputs
will force the amplifier output to a high state In neither case
does a latch occur since raising the input back within the
5
PDF 
ZIP