Document Outline
- General Description
- Outstanding Features
- Block Diagram
- Features
- Table of Contents
- Signal/Pin Connection and Description
- Functional Overview
- Parallel Interface
- Direct Memory Access (DMA) Support
- MICROWIRE/PLUS Interface
- Functional Description
- Register Set
- 7.1 CONTROL REGISTERS
- 7.2 TRANSFER REGISTERS
- 7.2.1 FIFO Warning Event Register (FWEV)
- 7.2.2 FIFO Warning Mask Register (FWMSK)
- 7.2.3 Frame Number High Byte Register (FNH)
- 7.2.4 Frame Number Low Byte Register (FNL)
- 7.2.5 Function Address Register (FAR)
- 7.2.6 DMA Control Register (DMACNTRL)
- 7.2.7 DMA Event Register (DMAEV)
- 7.2.8 DMA Mask Register (DMAMSK)
- 7.2.9 Mirror Register (MIR)
- 7.2.10 DMA Count Register (DMACNT)
- 7.2.11 DMA Error Register (DMAERR)
- 7.2.12 Wake-Up Register (WKUP)
- 7.2.13 Endpoint Control 0 Register (EPC0)
- 7.2.14 Transmit Status 0 Register (TXS0)
- 7.2.15 Transmit Command 0 Register (TXC0)
- 7.2.16 Transmit Data 0 Register (TXD0)
- 7.2.17 Receive Status 0 Register (RXS0)
- 7.2.18 Receive Command 0 Register (RXC0)
- 7.2.19 Receive Data 0 Register (RXD0)
- 7.2.20 Endpoint Control X Register (EPC1 to EPC6)
- 7.2.21 Transmit Status X Register (TXS1, TXS2, TXS3)
- 7.2.22 Transmit Command X Register (TXC1, TXC2, TXC3)
- 7.2.23 Transmit Data X Register (TXD1, TXD2, TXD3)
- 7.2.24 Receive Status X Register (RXS1, RXS2, RXS3)
- 7.2.25 Receive Command X Register (RXC1, RXC2, RXC3)
- 7.2.26 Receive Data X Register (RXD1, RXD2, RXD3)
- 7.3 REGISTER MAP
- Device Characteristics
- Physical Dimensions
- May 1998
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USBN9603 Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support
PRELIMINARY
March 2000
USBN9603 Universal Serial Bus
Full Speed Function Controller with Enhanced DMA Support
General Description
The USBN9603 is an integrated, USB Node controller that
features enhanced DMA support with many automatic data
handling features. It is compatible with USB specification ver-
sions 1.0 and 1.1, and is an advanced version of the currently
available USBN9602.
A single IC integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUSTM interface. Seven
endpoint pipes are supported: one for the mandatory con-
trol endpoint and six to support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Outstanding Features
q
Low EMI, low standby current, 24 MHz oscillator
q
Advanced DMA mechanism
q
Fully static HALT mode with asynchronous wake-up
for bus powered operation
q
5V or 3.3V operation
q
Improved input range 3.3V signal voltage regulator
q
All unidirectional FIFOs are 64 bytes
q
Power-up reset and startup delay counter simplify sys-
tem design
q
Simple programming model controlled by external controller
q
Available in two packages
-- USBN9603SLB: small footprint for new designs and
portable applications
-- USBN9603-28M: standard package, pin-to-pin com-
patible with USBN9602-28M
Block Diagram
Physical Layer Interface (PHY)
Media Access Controller (MAC)
Transceiver
24 MHz
Oscillator
Clock
Generator
XIN
XOUT
CLKOUT
Microcontroller Interface
D+
D-
Upstream Port
INTR
V3.3
A0/ALE D7-0/AD7-0
Endpoint/Control FIFOs
VReg
AGND
RESET
V
CC
GND
MODE1-0
Serial Interface Engine (SIE)
USB Event
Detect
Clock
Recovery
CS
RD
WR
2000 National Semiconductor Corporation
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
TM
and MICROWIRE
TM
are trademarks of National Semiconductor Corporation.
2
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Features
q
Full-speed USB node device
q
USB transceiver
q
24 MHz oscillator circuit
q
Programmable clock generator
q
Serial Interface Engine (SIE) consisting of Physical
Layer Interface (PHY) and Media Access Controller
(MAC), USB Specification 1.0 and 1.1 compliant
q
Control/Status register file
q
USB Function Controller with seven FIFO-based End-
points:
-- One bidirectional Control Endpoint 0 (8 bytes)
-- Three Transmit Endpoints (64 bytes each)
-- Three Receive Endpoints (64 bytes each)
q
8-bit parallel interface with two selectable modes:
-- Non-multiplexed
-- Multiplexed (Intel compatible)
q
Enhanced DMA support
-- Automatic DMA (ADMA) mode for fully CPU-inde-
pendent transfer of large bulk or ISO packets
-- DMA controller, together with the USBN9603 ADMA
logic, can transfer a large block of data in 64-byte
packets via the USB
-- Automatic Data PID toggling/checking and NAK
packet recovery (maximum 256x64 bytes of data =
16K bytes)
q
MICROWIRE/PLUS
TM
interface
3
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Table of Contents
1.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAMS ........................................................................................................ 6
1.2
DETAILED SIGNAL/PIN DESCRIPTIONS .................................................................................. 7
1.2.1
Power Supply ................................................................................................................ 7
1.2.2
Oscillator, Clock and Reset ........................................................................................... 7
1.2.3
USB Port ....................................................................................................................... 8
1.2.4
Microprocessor Interface ............................................................................................... 8
2.0
Functional Overview
2.1
TRANSCEIVER ......................................................................................................................... 10
2.2
VOLTAGE REGULATOR (VREG) ............................................................................................. 10
2.3
SERIAL INTERFACE ENGINE (SIE) ......................................................................................... 10
2.4
ENDPOINT PIPE CONTROLLER (EPC) ................................................................................... 12
2.5
MICROCONTROLLER INTERFACE ......................................................................................... 12
3.0
Parallel Interface
3.1
NON-MULTIPLEXED MODE ..................................................................................................... 13
3.1.1
Standard Access Mode ............................................................................................... 14
3.1.2
Burst Mode .................................................................................................................. 14
3.1.3
User Registers ............................................................................................................. 14
3.2
MULTIPLEXED MODE .............................................................................................................. 15
4.0
Direct Memory Access (DMA) Support
4.1
STANDARD DMA MODE (DMA) ............................................................................................... 16
4.2
AUTOMATIC DMA MODE (ADMA) ........................................................................................... 17
5.0
MICROWIRE/PLUS Interface
5.1
OPERATING COMMANDS ....................................................................................................... 19
5.2
READ AND WRITE TIMING ...................................................................................................... 20
6.0
Functional Description
6.1
FUNCTIONAL STATES ............................................................................................................. 22
6.1.1
Line Condition Detection ............................................................................................. 22
6.1.2
Functional State Transition .......................................................................................... 22
6.2
ENDPOINT OPERATION .......................................................................................................... 24
6.2.1
Address Detection ....................................................................................................... 24
6.2.2
Transmit and Receive Endpoint FIFOs ....................................................................... 24
6.2.3
Programming Model .................................................................................................... 28
6.3
POWER SAVING MODES ........................................................................................................ 28
7.0
Register Set
7.1
CONTROL REGISTERS ........................................................................................................... 30
7.1.1
Main Control Register (MCNTRL) ............................................................................... 30
7.1.2
Clock Configuration Register (CCONF)...................................................................... 31
Table of Contents
(Continued)
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7.1.3
Revision Identifier (RID) .............................................................................................. 31
7.1.4
Node Functional State Register (NFSR) ..................................................................... 32
7.1.5
Main Event Register (MAEV) ....................................................................................... 32
7.1.6
Main Mask Register (MAMSK) .................................................................................... 33
7.1.7
Alternate Event Register (ALTEV).............................................................................. 33
7.1.8
Alternate Mask Register (ALTMSK) ............................................................................ 34
7.1.9
Transmit Event Register (TXEV) ................................................................................. 34
7.1.10
Transmit Mask Register (TXMSK) ............................................................................... 35
7.1.11
Receive Event Register (RXEV) ................................................................................. 35
7.1.12
Receive Mask Register (RXMSK) ............................................................................... 35
7.1.13
NAK Event Register (NAKEV) .................................................................................... 36
7.1.14
NAK Mask Register (NAKMSK) ................................................................................... 36
7.2
TRANSFER REGISTERS .......................................................................................................... 36
7.2.1
FIFO Warning Event Register (FWEV) ....................................................................... 36
7.2.2
FIFO Warning Mask Register (FWMSK) ..................................................................... 37
7.2.3
Frame Number High Byte Register (FNH) .................................................................. 37
7.2.4
Frame Number Low Byte Register (FNL) .................................................................... 37
7.2.5
Function Address Register (FAR) ................................................................................ 38
7.2.6
DMA Control Register (DMACNTRL) .......................................................................... 38
7.2.7
DMA Event Register (DMAEV) .................................................................................... 39
7.2.8
DMA Mask Register (DMAMSK) ................................................................................. 40
7.2.9
Mirror Register (MIR) ................................................................................................... 41
7.2.10
DMA Count Register (DMACNT) ................................................................................. 41
7.2.11
DMA Error Register (DMAERR) .................................................................................. 41
7.2.12
Wake-Up Register (WKUP) ........................................................................................ 42
7.2.13
Endpoint Control 0 Register (EPC0) ............................................................................ 43
7.2.14
Transmit Status 0 Register (TXS0) ............................................................................. 43
7.2.15
Transmit Command 0 Register (TXC0) ..................................................................... 44
7.2.16
Transmit Data 0 Register (TXD0) ................................................................................ 44
7.2.17
Receive Status 0 Register (RXS0) .............................................................................. 44
7.2.18
Receive Command 0 Register (RXC0) ....................................................................... 45
7.2.19
Receive Data 0 Register (RXD0) ................................................................................ 45
7.2.20
Endpoint Control X Register (EPC1 to EPC6) ............................................................. 46
7.2.21
Transmit Status X Register (TXS1, TXS2, TXS3) ....................................................... 46
7.2.22
Transmit Command X Register (TXC1, TXC2, TXC3) ................................................ 47
7.2.23
Transmit Data X Register (TXD1, TXD2, TXD3) ......................................................... 48
7.2.24
Receive Status X Register (RXS1, RXS2, RXS3) ....................................................... 48
7.2.25
Receive Command X Register (RXC1, RXC2, RXC3) ................................................ 49
7.2.26
Receive Data X Register (RXD1, RXD2, RXD3) ......................................................... 50
Table of Contents
(Continued)
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7.3
REGISTER MAP ........................................................................................................................ 50
8.0
Device Characteristics
8.1
ABSOLUTE MAXIMUM RATINGS ............................................................................................ 52
8.2
DC ELECTRICAL CHARACTERISTICS ................................................................................... 52
8.3
AC ELECTRICAL CHARACTERISTICS .................................................................................... 53
8.4
PARALLEL INTERFACE TIMING (MODE1-0 = 00B) ................................................................ 54
8.5
PARALLEL INTERFACE TIMING (MODE1-0 = 01B) ................................................................ 55
8.6
DMA SUPPORT TIMING ........................................................................................................... 57
8.7
MICROWIRE INTERFACE TIMING (MODE1-0 = 10B) ............................................................. 58
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