NTE1639
Integrated Circuit
CMOS Clock Generator/Driver for BBDs
Description:
The NTE1639 is a CMOS LSI Clock Generator ina 8Lead DIP type package capable of generating
two phase clock signals of low output impedance for use as a BBD driver. The builtin V
GG
power
supply circuit provides the proper voltages needed for driving BBDs such as the NTE1641.
Features:
D
BBD Direct Driving Capability of up to two BBD's
D
Self and Separate Oscillations.
D
Two Phase Clock Output (Duty: 1/2)
D
Builtin V
GG
Voltage Generator for Driving the NTE1641 BBD.
D
Single Power Supply: 8V to 16V.
Applications:
D
BBD Clock Generator/Driver.
Absolute Maximum Ratings: (T
A
= +25
C unless otherwise specified)
Drain Supply Voltage, V
DD
18V to +0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pin Voltage, V
I,
V
O
V
DD
0.3V to +0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation, P
D
200mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Ambient Temperature Range, T
opr
10
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
30
to +125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions: (T
A
= +25
C unless otherwise specified)
Item
Symbol
Condition
Min
Typ
Max
Unit
Drain Supply Voltage
V
DD
GND = 0V
8
15
16
V
V
GG(OUT)
14
15
V
DD
Electrical Characteristics: (T
A
= +25
C, V
DD
= 15V, GND = 0V unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Drain Current
I
DD
No load
3
mA
Total Power Dissipation
P
tot
No load
Clock Output 40kH
Z
45
mW
OX1 Input Pin
Voltage "H" Level
V
IH
0
1
V
Voltage "L" Level
V
IL
V
DD
+1
V
DD
V
Input Leakage Current
I
Leak
V
I
= 0V to 15V
30
A
OX2 Output Pin
Output Current "H" Level
I
OH(1)
V
O
= 1V
0.6
mA
Output Current "L" Level
I
OL(1)
V
O
= 14V
0.5
mA
Output Leakage Current
I
LOL(1)
V
O
= V
DD
V
O
= GND
30
30
A
A
OX3 Output pin
Output Current "H" Level
I
OH(2)
V
O
= 1V
1.5
mA
Output Current "L" Level
I
OL(2)
V
O
= 14V
2
mA
Output Leakage Current
I
LOL(2)
V
O
= V
DD
V
O
= GND
30
30
A
A
CP1, CP2 output pin
Output Current "H" Level
I
OH(3)
V
O
= 1V
10
mA
Output Current "L" Level
I
OL(3)
V
O
= 14V
10
mA
Output Leakage Current
I
LOL(3)
V
O
= V
DD
V
O
= GND
30
30
A
A
V
GG
OUT output pin (Note 1)
Output Voltage
V
GG(Out)
14
V
Note 1. This pin generates the V
GG
voltage for a BBD manufac-
tured by NTE. So therefore, it might not be applicable for
other devices. In any case, the V
GG(OUT)
changes by the
following formula depending on the value of V
DD
.
Pin Descriptions:
Pin No.
Symbol
Pin Name
Description
1
GND
Ground
Connected to GND of the circuit.
2
CP1
Clock Output 1
This pin outputs a clock signal that is the reverse
phase of CP2 with a Duty Cycle of 1/2 the frequency
of oscillation.
3
V
DD
V
DD
apply
15V is applied
4
CP2
Clock Output 2
This pin outputs a clock signal that is a the reverse
phase of CP1
5
OX3
OSC connections to
R, C are connected for the In case of separate excita-
6
OX2
C
1
, R
2
, and R
1
separately
internal clock.
tion, OX3 and OX2 are
opened and OX1 is set to
7
OX1
separately
opened and OX1 is set to
OSC input.
8
V
GG OUT
V
GG
Voltage Output
14V is output. (V
DD
= 15V) V
GG OUT
= 14/15V
DD
.
The Maximum Clock Frequency:
The upper limit value of the clock frequency is determined by the load capacitance and power con-
sumption. The maximum power dissipation for the NTE1639 is P
D
= 200mW. If the clock frequency
of the load capacitance is increased, the power consumption will be increased. Accordingly, in order
to utilize this device with a dissipation less than the permissible value, it is necessary to select ade-
quate values for the clock frequency and load capacitance. By connecting a resistance to the clock
output pin, it is possible to increase the value of the maximum clock frequency without increasing dis-
sipation. Because the dissipation on the LSI side is lessened, part of the power consumption required
for driving the load capacitance is consumed by the series resistance.
Pin Connection Diagram
V
GG
(Out)
V
DD
1
2
3
4
GND
CP 1
CP 2
8
7
6
5
OX 1
OX 2
OX 3
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