NTE1853
Integrated Circuit
Digital Filter for Compact Disc Digital Audio System
Features:
D
16Bit Serial Data Input (Two's Complement)
D
Interpolated Data Replaces Erroneous Data Samples
D
12dB Attenuation via the Active Low Attenuation Input Control (ATSB)
D
Smoothed Trasitions Before and After Muting
D
Two Identical Finite Impulse Response Transversal Filters each with a Sampling Rate of Four
Times that of the Normal Digital Audio Data
D
Digital Audio Output of 32Bit Words Transmitted in Biphasemark Code
Applications:
D
Compact Disc Digital Audio System
D
Digital Filter
Absolute Maximum Ratings:
Supply Voltage Range (Pin24), V
DD
0.5V to +7.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Input Voltage Range, V
I
0.5V to V
DD
+0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Handling (Note 2), V
ES
1000V to +1000V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Ambient Temperature Range, T
A
20
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
65
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. All outputs are shortcircuit protected except the crystal oscillator output.
Note 2. Equivalent to discharging a 100pF capacitor through a 1.5
series resistor with a rise time
of 15ns.
DC and AC Electrical Characteristics: (V
DD
= 4.5 to 5.5V, V
SS
= 0, T
A
= 20
to +70
C unless
otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Voltage (Pin24)
V
DD
4.5
5.0
5.5
V
Supply Current (Pin24)
I
DD
180
mA
DC and AC Electrical Characteristics (Cont'd): (V
DD
= 4.5 to 5.5V, V
SS
= 0, T
A
= 20
to +70
C
unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
WSAB, DAAB
Input Voltage, Low
V
IL
0.3
+0.8
V
Input Voltage, High
V
IH
2.0
V
DD
+0.5
V
Input Leakage Current
I
LI
10
+10
A
Input Capacitance
C
I
7
pF
EFAB, SDAB (Note 1)
Input Voltage, Low
V
IL
0.3
+0.8
V
Input Voltage, High
V
IH
2.0
V
DD
+0.5
V
Input Leakage Current
I
LI
V
I
= 0V
10
A
V
I
= V
DD
+50
A
Input Capacitance
C
I
7
pF
CLAB, SCAB, ATSB, MUSB (Note 2)
Input Voltage, Low
V
IL
0.3
+0.8
V
Input Voltage, High
V
IH
2.0
V
DD
+0.5
V
Input Leakage Current
I
LI
V
I
= 0V
30
A
V
I
= V
DD
+10
A
Input Capacitance
C
I
7
pF
Output XOUT
Mutual Conductance at 100kHz
G
M
1.5
mA/V
SmallSignal Voltage Gain
A
V
A
V
= G
M
x R
O
3.5
V/V
Input Capacitance
C
I
10
pF
Feedback Capacitance
C
FB
5
pF
Output Capacitance
C
O
10
pF
Input Leakage Current
I
LI
10
0
+10
A
Slave Clock Mode
Input Voltage (Peak to Peak)
V
I(PP)
Note 3
3.0
V
DD
+0.5
V
Input Voltage, Low
V
IL
Note 3
0
1
V
Input Voltage, High
V
IH
Note 3
3.0
V
DD
+0.5
V
Input Rise Time
t
R
Note 4
20
ns
Input Fall Time
t
F
Note 4
20
ns
Input High Time at 2V (Relative to
Clock Period)
t
HIGH
35
65
%
Note 1. Inputs EFAB and SDAB both have internal pulldowns.
Note 2. Inputs CLAB, SCAB, ATSB, and MUSB have internal pullups.
Note 3. The minimum peaktopeak voltage can be reduced to 2V if the output XSYS is not being
used. Similarly V
IH
can be reduced to 2.4V (Min). All other levels remain the same.
Note 4. Reference levels = 10% and 90%.
DC and AC Electrical Characteristics (Cont'd): (V
DD
= 4.5 to 5.5V, V
SS
= 0, T
A
= 20
to +70
C
unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
DABD, CLBD, WSBD
Output Voltage, Low
V
OL
I
OL
= 1.6mA
0
0.4
V
Output Voltage, High
V
OH
I
OH
= 0.2mA
2.4
V
DD
V
Load Capacitance
C
L
50
pF
XSYS (Note 5)
Output Voltage, Low
V
OL
0
0.4
V
Output Voltage, High
V
OH
2.4
V
DD
V
Load Capacitance
C
L
50
pF
DOBM
Voltage Across a 75
Load via
Attenuator (PeaktoPeak)
V
L(PP)
0.4
0.6
V
Note 5. The output current conditions are dependent on the drive conditions. When a crystal oscilla-
tor is being used, the output current capability is I
OL
= +1.6mA; I
OH
= 0.2mA. But if a slave
input is being used, the output currents are reduced to I
OL
= +0.2mA; I
OH
= 0.2mA.
Timing Characteristics:
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Operating Frequency (XTAL)
f
XTAL
10.16
11.2896
12.42
MHz
Inputs
SCAB, CLAB (Note 6)
SCAB Clock Frequency (Burst Clock)
f
SCAB
2.8224
MHz
CLAB Clock Frequency
f
CLAB
Note 7
2.8224
MHz
1.4112
MHz
Clock Low Time
t
CKL
110
ns
Clock High Time
t
CKH
110
ns
Input Rise Time
t
R
20
ns
Input Fall Time
t
F
20
ns
DAAB, WSAB, EFAB (Note 8)
Data Setup Time
t
SU
, t
DAT
40
ns
Data Hold Time
t
HD
, t
DAT
0
ns
Input Rise Time
t
R
20
ns
Input Fall Time
t
F
20
ns
Note 6. Reference levels = 0.8V and 2.0V
Note 7. The signal CLAB can run at either 2.8MHz (
1
/
4
system clock) or 1.4MHz (
1
/
8
system clock)
under typical conditions. It does not have a minimum or maximum frequency, but is limited
to being
1
/
4
or
1
/
8
of the system clock frequency.
Note 8. Input setup and hold times measured with respect to clock input from Achip (CLAB). Refer-
ence levels = 0.8V and 2.0V.
Timing Characteristics (Cont'd):
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
SDAB (Note 9)
Subcode Data Setup Time
t
SU
, t
SDAT
40
ns
Subcode Data Hold Time
t
HD
, t
SDAT
0
ns
Input Rise Time
t
R
20
ns
Input Fall Time
t
F
20
ns
Outputs
WSBD (Note 6 & Note 10)
Word Select Setup Time
t
SU
, t
WS
40
ns
Word Select Hold Time
t
HD
, t
WS
0
ns
WSBD (Note 6)
Output Rise Time
t
R
20
ns
Output Fall Time
t
F
20
ns
DABD (Note 6 & Note 10)
Data Setup Time
t
SU
, t
DATD
40
ns
Data Hold Time
t
HD
, t
DATD
0
ns
Outputs (Cont'd)
DABD (Note 6)
Output Rise Time
t
R
20
ns
Output Fall Time
t
F
20
ns
CLBD (Note 6 & Note 10)
Clock Period
t
CK
161
177
197
ns
Clock Low Time
t
CKL
65
ns
Clock High Time
t
CKH
65
ns
Clock Setup Time
t
SU
, t
CLD
40
ns
Clock Hold Time
t
HD
, t
CLD
0
ns
CLBD (Note 6)
Output Rise Time
t
R
20
ns
Output Fall Time
t
F
20
ns
DABD (Note 6 & Note 11)
Data Setup Time
t
SU
, t
DATBD
40
ns
Data Hold Time
t
HD
, t
DATBD
60
ns
Note 6. Reference levels = 0.8V and 2.0V
Note 7. The signal CLAB can run at either 2.8MHz (
1
/
4
system clock) or 1.4MHz (
1
/
8
system clock)
under typical conditions. It does not have a minimum or maximum frequency, but is limited
to being
1
/
4
or
1
/
8
of the system clock frequency.
Note 8. Input setup and hold times measured with respect to clock input from Achip (CLAB). Refer-
ence levels = 0.8V and 2.0V.
Note 9. Input setup and hold times measured with respect to subcode burst clock input from Achip
(SCAB). Reference levels = 0.8V and 2.0V.
Note10. Output setup and hold times measured with respect to system clock output (XSYS).
Note 11. Output setup and hold times measured with respect to clock output (CLBD).
Timing Characteristics (Cont'd):
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
WSBD (Note 6 & Note 11)
Word Select Setup Time
t
SU
,
t
DATWSD
40
ns
Word Select Hold Time
t
SU
,
t
DATWSD
60
ns
DOBM (Note 12)
Output Rise Time
t
R
20
ns
Output Fall Time
t
F
20
ns
Data Bit 0 Pulse Width High
t
HIGH(0)
354
ns
Data Bit 0 Pulse Width Low
t
LOW(0)
354
ns
Data Bit 1 Pulse Width High
t
HIGH(1)
177
ns
Data Bit 1 Pulse Width Low
t
LOW(1)
177
ns
XSYS
Output Rise Time
t
R
Note 6
20
ns
Output Fall Time
t
F
Note 6
20
ns
Output High Time at 2V
(Relative to Clock Period)
t
HIGH
35
65
%
Note 6. Reference levels = 0.8V and 2.0V
Note 11. Output setup and hold times measured with respect to clock output (CLBD).
Note12. Output rise and fall times measured between the 10% and 90% levels; the data bit pulse
width measured at the 50% level.
Pin Connection Diagram
ATSB
MUSB
V
DD
V
SS
X
IN
X
OUT
X
SYS
WSAB
TEST
CLBD
N.C.
N.C.
SDAB
N.C.
N.C.
N.C.
SCAB
1
2
3
4
DAAB
EFAB
5
N.C.
6
7
24
23
22
21
20
19
18
8
9
17
16
10
11
12
15
14
13
DABD
DOBM
CLAB
WSDB
1
12
24
13
1.300 (33.02)
Max
.520
(13.2)
.600
(15.24)
1.100 (27.94)
.100 (2.54)
.225
(5.73)
Max
.126
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