NTE2053
Integrated Circuit
8Bit MPU Compatible A/D Converter
Description:
The NTE2053 is a CMOS 8bit successive approximation Analog to Digital converter in a 20Lead DIP
type package which uses a differential potentiometric ladder similar to the 256R products. This device
is designed to allow operation with the NSC800 and INS8080A derivative control bus, and TRISTATE
R
output latches directly drive the data bus. These A/Ds appear like memory locations or I/O ports to the
microprocessor and no interfacing logic is needed.
A new differential analog voltage input allows increasing the commonmode rejection and offsetting
the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow
encoding any similar analog voltage span to the full 8 bits of resolution.
Features:
D
Compatible With 8080 MPU Derivatives No Interfacing Logic Needed Access Time: 135ns
D
Easy Interface to all Microprocessors, or Operates "Stand Alone"
D
Differential Analog Voltage Inputs
D
Logic Inputs and Outputs Meet Both MOS and TTL Voltage Level Specifications
D
Works With 2.5V (NTE952) Voltage Reference
D
OnChip Clock Generator
D
0V to 5V Analog Input Voltage Range with Single 5V Supply
D
No Zero Adjust Required
D
Operates Ratiometrically or with 5V, 2.5V, or Analog Span Adjusts Voltage Reference
Absolute Maximum Ratings: (Note 1, Note 2)
Supply Voltage (Note 3), V
CC
6.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage at Logic Control Inputs
0.3V to +18V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage at All Other Inputs and Outputs
0.3V to V
CC
+0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
65
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (T
A
= +25
C), P
D
875mW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (During Soldering, 10sec), T
L
+300
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions: (Note 1, Note 2)
Operating Temperature Range, T
A
0
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage Range, V
CC
4.5V to 6.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Absolute Maximum Ratings are those values beyond which the life of the device may be im-
paired.
Note 2. All voltage are measured with respect to GND, unless otherwise specified. The separate
A GND point should always be wired to the D GND.
Note 3. A zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7V.
Electrical Characteristics: (V
CC
= 5V, T
A
= 0
to +70
C, f
CLK
= 640kHz unless otherwise specified)
Parameter
Test Conditions
Min
Typ
Max
Unit
Total Unadjusted Error (Note 4)
V
REF
/2 = 2.500V
1
/
2
LSB
V
REF
/2 Input Resistance
2.5
8.0
k
Analog Input Voltage Range
V(+) or V(), Note 5
GND0.05
V
CC
+0.05
V
DC CommonMode Error
Over Analog Input Voltage Range
1
/
16
1
/
8
LSB
Power Supply Sensitivity
V
CC
= 5V
10% Over Allowed
V
IN
(+) and V
IN
() Voltage Range,
Note 5
1
/
16
1
/
8
LSB
Note 4. The NTE2053 A/D does not require a zero adjust.
Note 5. For V
IN
()
V
IN
(+) the digital output code will be 0000 0000. Two onchip diodes are tied
to each analog input which will forward conduct for analog input voltages one diode drop bel-
wo GND or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct espe-
cially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec
allows 50mV forward bias of either diode. This means that as long as the analog V
IN
does
not exceed the supply voltage by more than 50mV, the output code will be correct. To
achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply
voltage of 4.950V over temperature variations, initial tolerance, and loading.
AC Electrical Characteristics: (V
CC
= 5V, T
A
= +25
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Conversion Time
T
C
f
CLK
= 640kHz, Note 7
103
114
s
Note 6, Note 7
66
73
1/f
CLK
Clock Frequency
f
CLK
V
CC
= 5V, Note 6
100
640
1460
kHz
Clock Duty Cycle
Note 6
40
60
%
Conversion Rate in FreeRunning
Mode
CR
INTR tied to WR with
CS = 0V, f
CLK
= 640kHz
8770
conv/s
Width of WR Input (Start Pulse Width)
t
W(WR)L
CS = 0, Note 8
100
ns
Access Time (Delay from Falling Edge
of RD to Output Data Valid)
t
ACC
C
L
= 100pF
135
200
ns
TRISTATE Control (Delay from Rising
Edge of RD to HiZ State)
t
1H
, t
0H
C
L
= 10pF, R
L
= 10k
125
200
ns
Delay from Falling Edge of WR or RD
to Reset of INTR
t
WI
, t
RI
300
450
ns
Input Capacitance of Logic
Control Inputs
C
IN
5
7.5
pF
TRISTATE Output Capacitance
(Data Buffers)
C
OUT
5
7.5
pF
Note 6. Accuracy is guaranteed at f
CLK
= 640kHz. At higher clock frequencies accuracy can de-
grade. For lower clock frequencies, the duty cycle limits can be extended so long as the mini-
mum clock high time interval or minimum clock low time interval is no less than 275ns.
Note 7. With an asynchronous start pulse, up to 8 clock periods may be required before the internal
clock phases are proper to start the conversion process. The start request is internally
latched.
Note 8. The CS input is assumed to bracket the WR strobe input and therefore timing is dependent
on the WR pulse width. An arbitrary wide pulse width will hold the converter on a reset mode
and the start of conversion is initiated by the low to high transition of the WR pulse.
Electrical Characteristics (Cont'd): (V
CC
= 5V, T
A
= 0
to +70
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Control Inputs (Note: CLK IN (Pin4) is the input of a Schmitt trigger circuit and is therefore specified separately)
Logical "1" Input Voltage
(Except Pin4 CLK IN)
V
IN
(1)
V
CC
= 5.25V
2.0
15
V
Logical "0" Input Voltage
(Except Pin4 CLK IN)
V
IN
(0)
V
CC
= 4.75V
0.8
V
Logical "1" Input Current (All Inputs)
I
IN
(1)
V
IN
= 5V
0.005
1
A
Logical "0" Input Current (All Inputs)
I
IN
(0)
V
IN
= 0V
1
0.005
A
CLOCK IN and CLOCK R
CLK IN (Pin4) Positive Going
Threshold Voltage
V
T
+
2.7
3.1
3.5
V
CLK IN (Pin4) Negative Going
Threshold Voltage
V
T
1.5
1.8
2.1
V
CLK IN (Pin4) Hysteresis (V
T
+)(V
T
)
V
H
0.6
1.3
2.0
V
Logical "0" CLK R Output Voltage
V
OUT
(0)
V
CC
= 4.75V, I
O
= 360
A
0.4
V
Logical "1" CLK R Output Voltage
V
OUT
(1)
V
CC
= 4.75V, I
O
= 360
A
2.4
V
Data Outputs and INTR
Logical "0" Output Voltage
Data Outputs
V
OUT
(0)
V
CC
= 4.75V, I
OUT
= 1.6mA
0.4
V
INTR Outputs
V
CC
= 4.75V, I
OUT
= 1.0mA
0.4
V
Logical "1" Output Voltage
V
OUT
(1)
V
CC
= 4.75V, I
O
= 360
A
2.4
V
V
CC
= 4.75V, I
O
= 10
A
4.5
V
TRISTATE Disable Output Leakage
I
OUT
V
OUT
= 0V
3
A
(All Data Buffers)
V
OUT
= 5V
3
A
Source Current
I
SOURCE
V
OUT
Short to GND,
T
A
= +25
C
4.5
6.0
mA
Sink Current
I
SINK
V
OUT
Short to V
CC
,
T
A
= +25
C
9.0
16
mA
Power Supply
Supply Current (Includes Ladder
Current)
I
CC
f
CLK
= 640kHz,
V
REF
/2 = NC. T
A
= +25
C,
CS = "1"
1.1
1.8
mA
Functional Description:
The NTE2053 contains a circuit equivalent to the 256R network. Analog switches are sequenced by
successive approximation logic to match the analog difference input voltage [V
IN
(+) V
IN
()] to a corre-
sponding tap on the R network. The most significant bit is tested first and after 8 comparisons (64 clock
cycles) a digital 8bit binary code (1111 1111 = fullscale) is transferred to an output latch and then an
interrupt is asserted (INTR makes a hightolow transition). A conversion in process can be interrupted
by issuing a second start command. The device may be operated in the freerunning mode by connect-
ing INTR to the WR input with CS = 0. To insure startup under all possible conditions, an external WR
pulse is required during the first powerup cycle.
On the hightolow transition of the WR input the internal SAR latches and the shift register stages are
reset. As long as the CS input and WR input remain low. the A/D will remain in a reset state. Conversion
will start from 1 to 8 clock periods after at least one of these inputs makes a lowtohigh transition.
Functional Description (Cont'd):
The converter is started by having CS and WR simultaneously low. This sets the start flipflop (F/F)
and the resulting "1" level resets the 8bit shift register, resets the interrupt (INTR) F/F and inputs a "1"
to the D flop, F/F1, which is at the input end of the 8bit shift register. Internal clock signals then transfer
this "1" to the Q output of F/F1. The AND gate, G1, combines this "1" output with a clock signal to provide
a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a "1") the start
F/F is reset and the 8bit shift register then can have the "1" clocked in, which starts the conversion
process. If the set signal were to still be present, this reset pulse would have no effect (both outputs
of the start F/F would momentarily be at a "1" level) and the 8bit shift register would continue to be held
in the reset mode. This logic therefore allows for wide CS and WR signals and the converter will start
after at least one of these signals returns high and the internal clocks again provide a reset signal for
the start F/F.
After the "1" is clocked through the 8bit shift register (which completes the SAR search) it appears as
the input to the Dtype latch, LATCH 1. As soon as this "1" is output from the shift register, the AND
gate, G2, causes the new digital word to transfer to the TRISTATE output latches. When LATCH 1
is subsequently enabled, the Q output makes a hightolow transition which causes the INTR F/F to
set. An inverting buffer then supplies the INTR input signal.
Note that the SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal
clocks run at
1
/
8
of the frequency of the external clock). If the data output is continuously enabled (CS
and RD both are held low), the INTR output will still signal the end of conversion (by a hightolow
transition), because the SET input can control the Q output of the INTR F/F even though the RESET
input is constant at a "1" level in this operating mode. This INTR output will therefore stay low for the
duration of the SET signal, which is 8 periods of the external clock frequency (assuming the A/D is
not started during this interval).
When operating in the freerunning or continuous conversion mode (INTR pin tied to WR and CS wired
low), the START F/F is SET by the hightolow transition of the INTR signal. This resets the SHIFT
REGISTER which causes the input to the Dtype latch, LATCH 1, to go low. As the latch enable input
is still present, the Q output will go high, which then allows the INTR F/F to be RESET. This reduces
the width of the resulting INTR output pulse to only a few propagation delays (approximately 300ns).
When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be
reset and the TRISTATE output latches will be enables to provide the 8bit digital outputs.
V
REF
/2
V
IN
()
V
IN
(+)
INTR
WR
RD
CS
V
CC
Pin Connection Diagram
A GND
CLK IN
DB2
DB5
DB0 (LSB)
1
2
3
4
5
6
7
20
19
18
17
CLK R
DB1
16
15
DB3
14
DB4
8
13
DB6
9
12
D GND
DB7 (MSB)
10
11
.280 (7.12) Max
.995 (25.3) Max
.300
(7.62)
.280
(7.1)
.100 (2.54)
.125 (3.17) Min
20
11
1
10
.385 (9.8)
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