NTE3880
Integrated Circuit
NMOS, 8Bit Microprocessor (MPU), 4MHz
Description:
The NTE3880 is a third generation single chip microprocessor with unrivaled computational power.
This increased computational power results in higher system throughput and more efficient memory
utilization when compared to second generation microprocessors. In addition it is very easy to imple-
ment into a system because of it's single voltage requirement plus all output signals are fully decoded
and timed to control standard memory or peripheral circuits. The circuit is implemented using an N
channel, ion implanted, silicon gate MOS process.
This device has an internal register configuration which contains 208 bits of Read/Write memory that
are accessible to the programmer. The registers include two sets of six general purpose registers that
may be used individually as 8bit registers or as 16bit register pairs. There are also two sets of accu-
mulator and flag registers. The programmer has access to either set of main or alternate registers
through a group of exchange instructions. This alternate set allows foreground/background mode of
operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16bit
stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine
nesting and simplification of many types of data handling.
The two 16bit index registers allow tabular data manipulation and easy implementation of relocat-
able code. The Refresh register provides for automatic, totally transparent refresh of external dynam-
ic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of
a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits
of the pointer. An indirect call is then made to this service address.
Features:
D
Single Chip, NChannel Silicon Gate
D
158 Instructions Includes all 78 of the 8080A Instructions with Total Software Compatibility. New
Instructions Include 4, 8 and 16Bit Operations with more useful Addressing Modes such as
Indexed, Bit and Relative
D
17 Internal Registers
D
Three Modes of Fast Interrupt Response plus a NonMaskable Interrupt
D
Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic
D
1.0
s Instruction Execution Speed
D
Single 5VDC Supply and SinglePhase 5V Clock
D
OutPerforms any other SinglePhase 5V Clock
D
All Pins TTL Compatible
D
BuiltIn Dynamic RAM Refresh Circuitry
Absolute Maximum Ratings:
Temperature Under Bias
0
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range
65
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage On Any Pin With Respect to GND
0.3V to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation
1.5W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only functional operation of the device at these
or any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics: (T
A
= 0
to 70
C, V
CC
= 5V
5% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Clock Input Low Voltage
V
ILC
0.3
0.80
V
Clock Input High Voltage
V
IHC
V
CC
0.6
V
CC
+3
V
Input Low Voltage
V
IL
0.3
0.8
V
Input High Voltage
V
IH
2.0
V
CC
V
Output Low Voltage
V
OL
I
OL
= 1.8mA
0.4
V
Output High Voltage
V
OH
I
OH
= 250
A
2.4
V
Power Supply Current
I
CC
90
200
mA
Input Leakage Current
I
L1
V
IN
= 0 to V
CC
10
A
TriState Output Leakage Current in Float
I
LOH
V
OUT
= 2.4 to V
CC
10
A
TriState Output Leakage Current in Float
I
LOL
V
OUT
= 0.4V
10
A
Data Bus Leakage Current in Input Mode
I
LD
0
V
IN
V
CC
10
A
Capacitance: (T
A
= +25
C, f = 1MHz, unmeasured pins to GND unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Clock Capacitance
C
35
pF
Input Capacitance
C
IN
5
pF
Output Capacitance
C
OUT
10
pF
AC Characteristics: (T
A
= 0
C to +70
C, V
CC
= +15V
5% unless otherwise specified)
Parameter
Symbol Signal Test Conditions
Min
Typ
Max
Unit
Clock Period
t
c
25
Note 2
s
Clock Pulse Width, Clock High
t
w
(
H)
110
Note 3
ns
Clock Pulse Width, Clock Low
t
w
(
L)
110
2000
ns
Clock Rise and Fall Time
t
r
, t
f
30
ns
Address Output Delay
t
D
(AD)
A
015
C
L
= 50pF
110
ns
Data to Float
t
F
(AD)
90
ns
Address Stable Prior to MRFQ (Memory Cycle)
t
acm
Note 4
ns
Address Stable Prior to IOFQ, RD or WR (I/O Cycle)
t
aci
Note 5
ns
Address Stable from RD, WR, IORQ, or MREQ
t
ca
Note 6
ns
Address Stable from RD or WR During Float
t
caf
Note 7
ns
Note 2. t
c
= t
w
(
H) + t
w
(
L) + t
r
+ t
f
.
Note 3. Although static by design, testing guarantees t
w
(
H) of 200
s maximum.
Note 4. t
acm
= t
w
(
H) + t
f
65.
Note 5. t
aci
= t
c
70.
Note 6. t
ca
= t
w
(
L) + t
r
50.
Note 7. t
caf
= t
w
(
L) + t
r
45.
AC Characteristics (Cont'd): (T
A
= 0
C to +70
C, V
CC
= +15V
5% unless otherwise specified)
Parameter
Symbol
Signal
Test Conditions
Min
Typ
Max
Unit
Data Output Delay
t
D
(D)
D
07
C
L
= 50pF
150
ns
Delay to Float During Write Cycle
t
F
(D)
90
ns
Data Setup Time to Rising Edge of Clock
During M
1
Cycle
t
S
(D)
35
ns
Data Setup Time to falling Edge of Clock
During M
2
to M
5
50
ns
Data Stable Prior to WR (Memory Cycle)
t
dcm
Note 8
ns
Data Stable Prior to WR (I/O Cycle)
t
dci
Note 9
ns
Data Stable From WR
t
cdf
Note 10
ns
Any Hold Time for Setup Time
t
H
0
ns
MREQ Delay From Falling Edge of Clock,
MREQ Low
t
DL
(MR)
MREQ
C
L
= 50pF
85
ns
MREQ Delay From Rising Edge of Clock,
MREQ High
t
DH
(MR)
85
ns
MREQ Delay From Falling Edge of Clock,
MREQ High
85
ns
Pulse Width, MREQ Low
t
w
(MRL)
Note 11
ns
Pulse Width, MREQ High
t
w
(MRH)
Note 12
ns
IORQ Delay From Rising Edge of Clock
IORQ Low
t
DL
(IR)
IORQ
C
L
= 50pF
75
ns
IORQ Delay From Falling Edge of Clock
IORQ Low
85
ns
IORQ Delay From Rising Edge of Clock
IORQ High
t
DH
(IR)
85
ns
IORQ Delay From Falling Edge of Clock
IORQ High
85
ns
RD Delay From Rising Edge of Clock,
RD Low
t
DL
(RD)
RD
C
L
= 50pF
85
ns
RD Delay From Falling Edge of Clock,
RD Low
95
ns
RD Delay From Rising Edge of Clock,
RD High
t
DH
(RD)
85
ns
RD Delay From Falling Edge of Clock,
RD High
85
ns
WR Delay From Rising Edge of Clock,
WR Low
t
DL
(WR)
WR
C
L
= 50pF
65
ns
WR Delay From Falling Edge of Clock,
WR Low
80
ns
WR Delay From Falling Edge of Clock,
WR High
t
DH
(WR)
80
ns
Pulse Width, WR Low
t
w
(WRL)
Note 13
ns
Note 8. t
dcm
= t
c
170.
Note 9. t
dci
= t
w
(
L) + t
r
170.
Note10. t
cdf
= t
w
(
L) + t
r
70.
Note 11. t
w
(MRL) = t
c
30.
Note12. t
w
(MRH) = t
w
(
H) + t
r
20.
Note13. t
w
(WRL) = t
c
30.
AC Characteristics (Cont'd): (T
A
= 0
C to +70
C, V
CC
= +15V
5% unless otherwise specified)
Parameter
Symbol
Signal
Test Conditions
Min
Typ
Max
Unit
M1 Delay From Rising Edge of Clock,
M1 Low
t
DL
(M1)
M1
C
L
= 50pF
100
ns
M1 Delay From Rising Edge of Clock,
M1 High
t
DH
(M1)
100
ns
RFSH Delay From Rising Edge of Clock,
RFSH Low
t
DL
(RF)
RFSH
C
L
= 50pF
130
ns
RFSH Delay From Rising Edge of Clock,
RFSH High
t
DH
(RF)
120
ns
WAIT Setup Time to Falling Edge of Clock
t
s
(WT)
WAIT
70
ns
HALT Delay Time From Falling Edge of Clock
t
D
(HT)
HALT
C
L
= 50pF
300
ns
INT Setup Time to Rising Edge of Clock
t
s
(IT)
INT
80
ns
Pulse Width, NM1 Low
t
w
(NML)
NM1
80
ns
BUSRQ Setup Time to Rising Edge of Clock
t
s
(BQ)
BUSRQ
50
ns
BUSAK Delay From Rising Edge of Clock,
BUSAK Low
t
DL
(BA)
BUSAK C
L
= 50pF
100
ns
BUSAK Delay From Rising Edge of Clock,
BUSAK High
t
DH
(BA)
100
ns
RESET Setup Time to Rising Edge of Clock
t
s
(RS)
RESET
60
ns
Delay to Float (MREQ, IORQ, RD and WR)
t
F
(C)
80
ns
M1 Stable Prior to IORQ (Interrupt Ack.)
t
mr
Note 14
ns
Note14. t
mr
= 2t
c
+ t
w
(
H) + t
f
65.
Note15. Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge
data should be enabled when M1 and IORQ are both active.
Note16. All control signals are internally synchronized, so they may be totally asynchronous with
respect to the clock.
Note17. The RESET signal must be active for a minimum of 3 clock cycles.
Note18. Output Delay vs. Loaded Capacitance
T
A
= +70
C
V
CC
= 5V
5%
Add 10ns delay for each 50pf increase in load up to maximum of 200pF for data bus and
100pF for address & control lines.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
RD
M
1
RFSH
RESET
BUSRQ
WAIT
BUSAK
WD
MREQ
HALT
NMI
INT
Pin Connection Diagram
IORQ
D
5
D
4
D
3
GND
(+) 5V
1
2
3
4
5
6
System Clock Input
7
8
40
39
38
37
36
35
34
33
9
32
10
11
31
30
12
29
13
28
14
27
15
26
16
17
25
24
18
23
19
22
20
21
D
0
D
1
D
2
D
7
D
6
A
11
A
12
A
13
A
14
A
15
.550 (13.9)
Max
.650 (16.5)
2.055 (52.2)
.155 (3.9)
.100 (2.54)
.019 (0.5)
.137
(3.5)
1
20
40
21
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