NTE6664
Integrated Circuit
64KBit Dynamic RAM
Description:
The NTE6664 is a 65,536 Bit, highspeed, dynamic Random Access Memory. Organized as 65,536
onebit words and fabricated using HMOS highperformance NChannel silicongate technology,
this 5V only dynamic RAM combines high performance with low cost and improved reliability.
By multiplying row and column address inputs, the NTE6664 requires only eight address lines and
permits packaging in a standard 16Lead DIP package. Complete address decoding is done on chip
with address latches incorporated. Data out is controlled by CAS allowing for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible. The NTE6664 incorporates a one
transistor cell design and dynamic storage techniques. In addition to the RASonly refresh mode,
the refresh control function available on Pin1 provides two additional modes of refresh, automatic and
self refresh.
Features:
D
Single +5V Operation (
10%)
D
Maximum Access Time: 150ns
D
Low Power Dissipation:
302.5mW Max (Active)
22mW Max (Standby)
D
Three State Data Output
D
EarlyWrite Common I/O Capability
D
128 Cycle, 2ms Refresh
D
Control on Pin1 for Automatic or Self Refresh
D
RASOnly Refresh Mode
D
CAS Controlled Output
D
Fast Page Mode Cycle Time
D
Low Soft Error Rate: < 0.1% per 1000 Hrs
Absolute Maximum Ratings: (Note 1)
Voltage on V
CC
Supply Relative to V
SS
, V
CC
2 to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Relative to V
SS
for Any Pin Except V
CC
, V
in
, V
out
1 to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Out Current (Short Circuit), I
out
50mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation, P
D
1W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range, T
A
0 to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
65
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
the device reliability.
Recommended Operating Conditions: (Note 2, T
A
= 0 to +70
C unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
V
CC
4.5
5.0
5.5
V
V
SS
0
0
0
V
Logic 1 Voltage, All Inputs
V
IH
2.4
6.5
V
Logic 0 Voltage, All Inputs (Note 3)
V
IL
1.0
0.8
V
Note 2. All voltages referenced to V
SS
.
Note 3. The device will withstand undershoots to the 2V level with a maximum pulse width 0f 20ns
at the 1.5V level. This is periodically sampled rather than 100% tested.
DC Characteristics: (V
CC
= 5V
10%, T
A
= 0 to +70
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
V
CC
Power Supply Current
I
CC1
t
RC
= 270ns, Note 4
55
mA
V
CC
Power Supply Current (Standby)
I
CC2
RAS = CAS = V
IH
4
mA
V
CC
Power Supply Current During
RAS only Refresh Cycles
I
CC3
t
RC
= 270ns, Note 4
45
mA
Input Leakage Current
Any Input Except REFRESH
I
lkg(L)
V
SS
< V
in
< V
CC
10
A
REFRESH Input Current
I
lkg(F)
V
SS
< V
in
< V
CC
20
A
Output Leakage Current
I
lkg(O)
CAS at Logic 1, 0
V
out
5.5V
10
A
Output Logic 1 Voltage
V
OH
I
out
= 4mA
2.4
V
Output Logic 0 Voltage
V
OL
I
out
= 4mA
0.4
V
Note 4. Current is a function of cycle rate and output loading; maximum current is measured at the
fastest cycle rate with the output open.
Capacitance: (V
CC
= 5V
10%, f = 1MHz, T
A
= +25
C, Note 5, Periodically Sampled Rather
Than 100% Tested)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Capacitance
A0 A7, D
RAS, CAS, WRITE, REFRESH
C
in
3
6
5
8
pF
Output Capacitance
Q
C
out
CAS = V
IH
to Disable Output
5
7
pF
Note 5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the
equation: C = I
t/
V.
Read, Write, and ReadModifyWrite Cycles: (V
CC
= 5V
10%, T
A
= 0 to +70
C unless other
wise specified, Notes 6, 7, and 8)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Random Read or Write Cycle Time
t
RC
Note 9, Note 10
270
ns
ReadWrite Cycle Time
t
RWC
Note 9, Note 10
280
ns
Access Time from RAS
t
RAC
Note 11, Note 13
150
ns
Access Time from CAS
t
CAC
Note 12, Note 13
75
ns
Output Buffer and TurnOff Delay
t
OFF
Note 19
0
30
ns
RAS Precharge Time
t
RP
100
ns
RAS Pulse Width
t
RAS
150
10000
ns
CAS Pulse Width
t
CAS
75
10000
ns
Read, Write, and ReadModifyWrite Cycles (Cont'd): (V
CC
= 5V
10%, T
A
= 0 to +70
C
unless otherwise specified, Notes 6, 7, and 8)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
RAS to CAS Delay Time
t
RCD
Note 14
25
75
ns
Row Address Setup Time
t
ASR
0
ns
Row Address Hold Time
t
RAH
20
ns
Column Address Setup Time
t
ASC
0
ns
Column Address Hold Time
t
CAH
35
ns
Column Address Hold Time Referenced to RAS
t
AR
Note 18
95
ns
Transition Time (Rise and Fall)
t
T
3
50
ns
Read Command Setup Time
t
RCS
0
ns
Read Command Hold Time Referenced to CAS
t
RCH
Note 15
0
ns
Read Command Hold Time Referenced to RAS
t
RRH
Note 15
0
ns
Write Command Hold Time
t
WCH
35
ns
Write Command Hold Time Referenced to RAS
t
WCR
Note 18
95
ns
Write Command Pulse Width
t
WP
35
ns
Write Command to RAS Lead Time
t
RWL
45
ns
Write Command to CAS Lead Time
t
CWL
45
ns
Data in Setup Time
t
DS
Note 16
0
ns
Data in Hold Time
t
DH
Note 16
35
ns
Data in Hold Time Referenced to RAS
t
DHR
Note 18
95
ns
CAS to RAS Precharge Time
t
CRP
10
ns
RAS Hold Time
t
RSH
75
ns
Refresh Period
t
RFSH
2
ms
Write Command Setup Time
t
WCS
Note 17
10
ns
CAS to Write Delay
t
CWD
Note 17
45
ns
RAS to Write Delay
t
RWD
Note 17
120
ns
CAS Hold Time
t
CSH
150
ns
CAS Precharge Time (Page Mode Cycle Only)
t
CP
60
ns
Page Mode Cycle Time
t
PC
145
ns
RAS to REFRESH Delay
t
RFD
10
ns
REFRESH Period (Battery Backup Mode)
t
FBP
2000
ns
REFRESH to RAS Precharge Time
(Battery Backup Mode)
t
FBR
320
ns
REFRESH Cycle Time (Auto Pulse Mode)
t
FC
270
ns
REFRESH Pulse Period (Auto Period Mode)
t
FP
60
2000
ns
REFRESH to RAS Setup Time (Auto Pulse Mode)
t
FSR
30
ns
REFRESH to RAS Delay Time (Auto Pulse Mode)
t
FRD
320
ns
REFRESH Inactive Time
t
FI
60
ns
RAS to REFRESH Lead Time
t
FRL
370
ns
RAS Inactive Time During REFRESH
t
FRI
370
ns
Note 6. V
IH
min and V
IL
max are reference levels for measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
.
Note 7. An initial pause of 100
s is required after powerup followed by 8 RAS cycles before proper
device operation is guaranteed.
Note 8. The transition time specification applies for all input signals. In addition to meeting the transi-
tion rate specification, all input signals must transmit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
Note 9. The specification for t
RC
(min) and t
RMW
(min) are used only to indicate cycle time at which
proper operation over the full temperature range (0
C
T
A
+70
C) is assured.
Note10. AC measurements t
T
= 5ns.
Note 11. Assumes that t
RCD
t
RCD
(max).
Note12. Assumes that t
RCD
t
RCD
(max).
Note13. Measured with a current load equivalent to 2 TTL (200
A, +4mA) loads and 100pF with the
data output trip points set at V
OH
= 2V and V
OL
= 0.8V.
Note14. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met, t
RCD
(max) is speci-
fied as a reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, then ac-
cess time is controlled exclusively by t
CAC
.
Note15. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
Note16. These parameters are referenced to CAS leading edge in random write cycles and to WRITE
leading edge in delayed write or readmodifywrite cycles.
Note17. t
WCS
, t
CWD
, and t
RWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t
WCS
t
WCS
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if t
CWD
t
CWD
(min) and t
RWD
t
RWD
(min), the cycle is readwrite cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
Note19. t
OFF
(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
Address Buf
fer/Counters/Multiplexers
I/O
T
iming Control and Refresh Control
Column Decoder
Column Decoder
Precharge
Clock
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Row Decoder
Row Decoder
Precharge
Clock
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Row Decoder
Row Decoder
A0
A1
A2
A3
A4
A5
A6
A7
RAS
CAS
Write, W
REFRESH
Data In, D
Output Data, Q
V
CC
V
SS
Block Diagram
CAS
V
SS
V
CC
RAS
W
* REFRESH
Pin Connection Diagram
A5
A7
A1
A0
A4
A3
A6
Q
A2
D
1
2
3
4
5
6
7
16
15
14
13
12
11
10
8
9
* If pin is not used, it should be connected to V
CC
through a 10k resistor.
.700 (17.78)
.100 (2.54)
1
8
16
9
.200
(5.08)
Max
.870 (22.0) Max
.260 (6.6)
Max
.099 (2.5) Min
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