NTE6821
Integrated Circuit
Peripheral Interface Adapter (PIA),
NMOS, 1MHz
Description:
The NTE6821 is a peripheral interface adapter (PIA) in a 40Lead DIP type package capable of inter-
facing the Microprocessing Unit (MPU) to peripherals through two 8Bit bidirectional peripheral data
buses and four control lines. No external logic is required for interfacing to most peripheral devices.
The functional configuration of the PIA is programmed by the MPU during system initialization. Each
of the peripheral data lines can be programmed to act as an input or output, and each of the four con-
trol/interrupt lines may be programmed for one of several control modes. This allows a high degree
of flexibility in the overall operation of the interface.
Features:
D
8Bit Bidirectional Data Bus for Communication with the MPU
D
Two Bidirectional 8Bit Buses for Interface to Peripherals
D
Two Programmed Control Registers
D
Two Programmed Data Direction Registers
D
Four IndividuallyControlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs
D
Handshake Control Logic for Input and Output Peripheral Operation
D
HighImpedance 3State and Direct Transistor Drive Peripheral Lines
D
Program Controlled Interrupt and Interrupt Disable Capability
D
CMOS Drive Capability on Side A Peripheral Lines
D
Two TTL Drive Capability on All A and B Side Buffers
D
TTL Compatible
D
Static Operation
Absolute Maximum Ratings: (Note 1)
Supply Voltage, V
CC
0.3 to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage, V
in
0.3 to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range, T
A
0
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
55
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance, Junction to Ambient, R
JA
82.5
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance.
Electrical Characteristics: (V
CC
= 5V
5%, V
SS
= 0, T
A
= 0
to +70
/
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Bus Control Inputs (R/W, Enable, Reset, RS0, RS1, CS0, CS1, CS2)
Input High Voltage
V
IH
V
SS
+2.0
V
CC
V
Input Low Voltage
V
IL
V
SS
0.3
V
SS
+0.8
V
Input Leakage Current
I
in
V
in
= 0 to 5.25V
1.0
2.5
A
Capacitance
C
in
V
in
= 0, T
A
= +25
C, f = 1MHz
7.5
pF
Interrupt Outputs (IRQA, IRQB)
Output Low Voltage
V
OL
I
Load
= 3.2mA
V
SS
+0.4
V
Output Leakage Current (Off State)
I
LOH
V
OH
= 2.4V
1.0
10
A
Capacitance
C
out
V
in
= 0, T
A
= +25
C, f = 1MHz
5.0
pF
Data Bus (D0 D7)
Input High Voltage
V
IH
V
SS
+2.0
V
CC
V
Input Low Voltage
V
IL
V
SS
0.3
V
SS
+0.8
V
ThreeState (Off State) Input Current
I
TSI
V
in
= 0.4 to 2.4V
2.0
10
A
Output High Voltage
V
OH
I
Load
= 205
A
V
SS
+2.4
V
Output Low Voltage
V
OL
I
Load
= 1.6mA
V
SS
+0.4
V
Capacitance
C
in
V
in
= 0, T
A
= +25
C, f = 1MHz
12.5
pF
Peripheral Bus (PA0 PA7, PB0 PB7, CA1, CA2, CB1, CB2)
Input Leakage Current
R/W, Reset, RS0, RS1, CS0,
CS1, CS2, CA1, CB1, Enable
I
in
V
in
= 0 to 5.25V
1.0
2.5
A
ThreeState (Off State) Input Current
PB0 PB7, CB2
I
TSI
V
in
= 0.4 to 2.4V
2.0
10
A
Input High Current
PA0 PA7, CA2
I
IH
V
IH
= 2.4V
200
400
A
Darlington Drive Current
PB0 PB7, CB2
I
OH
V
O
= 1.5V
1.0
10
mA
Input Low Current
PA0 PA7, CA2
I
IL
V
IL
= 0.4V
1.3
2.4
mA
Output High Voltage
PA0 PA7, PB0 PB7, CA2, CB2
V
OH
I
Load
= 200
A
V
SS
+2.4
V
PA0 PA7, CA2
I
Load
= 10
A
V
CC
1.0
V
Output Low Voltage
V
OL
I
Load
= 3.2mA
V
SS
+0.4
V
Capacitance
C
in
V
in
= 0, T
A
= +25
C, f = 1MHz
10
pF
Power Requirements
Power Dissipation
P
D
550
mW
Bus Timing Characteristics: (V
CC
= 5V
5%, V
SS
= 0, T
A
= 0
to +70
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Enable Cycle Time
t
cycE
1000
ns
Enable Pulse Width, High
PW
EH
450
ns
Enable Pulse Width, Low
PW
EL
430
ns
Enable Pulse Rise and Fall Times
t
Er
, t
Ef
25
ns
Bus Timing Characteristics (Cont'd): (V
CC
= 5V
5%, V
SS
= 0, T
A
= 0
to +70
C unless otherwise
specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Setup Time, Address and R/W Valid to
Enable Positive Transition
t
AS
160
ns
Address Hold Time
t
AH
10
ns
Data Delay Time, Read
t
DDR
320
ns
Data Hold Time, Read
t
DHR
10
ns
Data Setup Time, Write
t
DSW
195
ns
data Hold Time, Write
t
DHW
10
ns
Peripheral Timing Characteristics:
(V
CC
= 5V
5%, V
SS
= 0, T
A
= 0
to +70
C unless otherwise
specified)
Parameter
Symbol
Min
Max
Unit
Peripheral Data Setup Time
t
PDSU
200
ns
Peripheral Data Hold Time
t
PDH
0
ns
Delay Time, Enable negative transition to CA2 negative transition
t
CA2
1.0
s
Delay Time, Enable negative transition to CA2 positive transition
t
RS1
1.0
s
Rise and fall Times for CA1 and CA2 input signals
t
r
, t
f
1.0
s
Delay Time from CA1 active transition to CA2 positive transition
t
RS2
2.0
s
Delay Time, Enable negative transition to Peripheral Data Valid
t
PDW
1.0
s
Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0 PA7, CA2
t
CMOS
2.0
s
Delay Time, Enable positive transition to CB2 negative transition
t
CB2
1.0
s
Delay Time, Peripheral Data Valid to CB2 negative transition
t
DC
20
ns
Delay Time, Enable positive transition to CB2 postivie transition
t
RS1
1.0
s
Peripheral Control Output Pulse Width, CA2/CB2
PW
CT
550
ns
Rise and Fall Time for CB1 and CB2 input signals
t
r
, t
f
1.0
s
Delay Time, CB1 active transition to CB2 positive transition
t
RS2
2.0
s
Interrupt Release Time, IRQA and IRQB
t
IR
2.0
s
Interrupt Response Time
t
RS3
1.0
s
Interrupt Input Pulse Width
PW
I
500
ns
Reset Low Time (Note 2)
t
RL
1.0
s
Note 2. The Reset line must be high a minimum of 1.0
s before addressing the PIA.
R/W
CS2
RESET
IRQB
IRQA
Expanded Block Diagram
Pin Connection Diagram
IRQA
38
D0
33
V
CC
=
PIN20
V
SS
=
PIN1
CS0
22
Data Bus
Buffers
(DBB)
Bus Input
Register
(BIR)
Chip
Select
and
R/W
Control
IRQB
37
Control
Register A
(CRA)
D1
32
D2
31
D3
30
D4
29
D5
28
D6
27
D7
26
CS1
24
CS2
23
RS0
36
RS1
35
R/W
21
Enable
25
Reset
34
Output
Register A
(ORA)
Output
Register B
(ORB)
Control
Register B
(CRB)
Output Bus
Input Bus
Interrupt Status
Control A
Interrupt Status
Control B
Data Direction
Register A
(DDRA)
Data Direction
Register B
(DDRB)
Peripheral
Interface
A
Peripheral
Interface
B
40
CA1
39
CA2
2
PA0
3
PA1
4
PA2
5
PA3
6
PA4
7
PA5
8
PA6
9
PA7
10
PB0
11
PB1
12
PB2
13
PB3
14
PB4
15
PB5
16
PB6
17
PB7
18
CB1
19
CB2
V
CC
V
SS
PA4
PA2
PA6
D2
PB1
CS0
CS1
E
D7
D6
D5
D4
D3
D1
D0
RS1
RS0
CA2
PA1
PA0
PA7
PB7
PB2
1
2
3
4
5
PA3
6
7
PA5
8
40
39
38
37
36
35
34
33
9
32
10
PB0
11
31
30
12
29
13
PB3
28
14
PB4
27
CB1
15
PB5
26
16
PB6
17
25
24
18
23
19
CB2
22
20
21
CA1
.550 (13.9)
Max
.650 (16.5)
2.055 (52.2)
.155 (3.9)
.100 (2.54)
.019 (0.5)
.137
(3.5)
1
20
40
21
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