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Электронный компонент: NTE6860

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NTE6860
Integrated Circuit
NMOS FSK Digital Modem, 600bps
Description:
The NTE6860 is a MOS subsystem in a 24Lead DIP type plastic package designed to be integrated
into a wide range of equipment utilizing serial data communications.
The modem provides the necessary modulation, demodulation and supervisory control functions to
implement a serial data communications link, over a voice grade channel, utilizing frequency shift key-
ing (FSK) at bit rates up to 600 bps. The NTE6860 can be implemented into a wide range of data
handling systems, including stand alone modems, data storage devices, remote data communication
terminals and I/O interfaces for minicomputers.
Nchannel silicongate technology permits the NTE6860 to operate using a singlevoltage supply
and be fully TTL compatible.
The modem is compatible with the NTE6860 microcomputer family, interfacing directly with the
Asynchronous Communications Interface Adapter to provide lowspeed data communications capa-
bility.
Features:
D
Originate and Answer Mode
D
Crystal or External Reference Control
D
Modem Self Test
D
Terminal Interfaces TTLCompatible
D
FullDuplex or HalfDuplex Operation
D
Automatic Answer and Disconnect
D
Compatible Functions for 100 Series Data Sets
D
Compatible Functions for 1001A/B Data Couplers
Absolute Maximum Ratings:
Supply Voltage, V
CC
0.3 to +7.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage, V
in
0.3 to +7.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range, T
A
0
to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, T
stg
55
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance, JunctiontoAmbient, R
thJA
+120
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage
level (e.g. either V
SS
or V
CC
).
Power Considerations:
The average chipjunction temperature, T
J
, in
C can be obtained from:
1. T
J
= T
A
+ (P
D
R
JA
)
Where:
T
A
5
Ambient Temperature,
C
R
JA
5
Package Thermal Resistance, Junction to Ambient,
C/W
P
D
5
P
INT
+ P
PORT
P
INT
5
i
CC
x V
CC
, Watts Chip Internal Power
P
PORT
5
Port Power Dissipation, Watts User Determined
For most applications P
PORT
P
INT
and can be neglected. P
PORT
may become significant if the de-
vice is configured to drive Darlington bases or sink LED loads.
An approximate relationship between P
D
and T
J
(if P
PORT
is neglected) is:
2. P
D
= K
B
(T
J
+ 273
C)
Solving equations 1 and 2 for K gives:
3. K = P
D
(T
A
+ 273
C) + R
JA
P
D
2
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by mea-
suring P
D
(at equilibrium) for a known T
A
. Using this value of K the values of P
D
and T
J
can be obtained
by solving equations 1 and 2 iteratively for any value of T
A
.
DC Electrical Characteristics:
(V
CC
= 5V
5%, all voltages referenced to V
SS
= 0, T
A
= 0
to +70
C
unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input High Voltage
V
IH
All Inputs Except Crystal
2.0
V
CC
V
Input Low Voltage
V
IL
All Inputs Except Crystal
V
SS
0.80
V
Crystal Input Voltage
V
in
Crystal Input Driven from an External Reference, Input
Coupling Capacitor = 200pF, Duty Cycle = 50
5%
1.5
2.0
V
PP
Input Current
I
in
V
in
= V
SS
All Inputs Except Rx Car, Tx Data, TD, TST,
RI, SH
0.2
mA
RI, SH Inputs
1.6
mA
Input Leakage Current
I
IL
V
in
= 7V, V
CC
= V
SS
, T
A
= +25
C
1.0
A
Output High Voltage
V
OH1
All Outputs Except An Ph and Tx Car, I
OH1
= 0.04mA,
Load A
2.4
V
CC
V
Output Low Voltage
V
OL1
All Outputs Except An Ph and Tx Car, I
OL1
= 1.6mA,
Load A
V
SS
0.40
V
V
OL2
An Ph, I
OL2
= 0, Load B
V
SS
0.30
V
Output High Current
I
OH2
An Ph, V
OH2
= 0.8V, Load B
0.30
mA
Input Capacitance
C
in
f = 0.1Mhz, T
A
= +25
C
5.0
pF
Output Capacitance
C
out
f = 0.1Mhz, T
A
= +25
C
10
pF
Transmit Carrier Output
Voltage
V
CO
Load C
0.20
0.35
0.50 V
RMS
Transmit Carrier Output
2
nd
Harmonic
V
2H
Load C
25
32
dB
Input Transition Times
t
r
All Inputs Except Crystal, Operating in the Crystal Input
1.0
s
t
f
Mode; from 10% to 90% Points, Note 2
1.0
s
t
r
Ctystal Input, Operating in External Input Reference
30
s
t
f
Mode
30
s
Output Transistion Times
t
r
All Outputs Except Tx Car, From 10% to 90% Points
5.0
s
t
f
5.0
s
Internal Power Dissipation
P
INT
All Inputs at V
SS
and All Outputs Open, T
A
= 0
C
340
mW
Note 2. Maximum Input Transition Times are
0.1 x Pulse Width or the specified maximum of 1
s,
whichever is smaller.
C
T
= 20pF = total parasitic capacitance, which includes probe, wiring, and load capacitance
Output Test Loads
Load A:
TTL Output Load for Receive Break, Digital
Carrier, Mode, CleartoSend, and Receive
Data Outputs
Load B:
Answer Phone Load
Load C:
Transmit Carrier Load
Pin Connection Diagram
ST
RI
DTR
SH
ESD
CTS
TD
V
CC
Brk R
Tx Brk
ESS
ELS
V
SS
TST
Rx Data
Rx Car
1
2
3
4
Tx Data
Rx Brk
An Ph
5
6
7
8
24
23
22
21
20
19
18
17
9
16
Mode
Rx Rate
10
Tx Car
11
FO
15
14
X'tal
12
13
V
CC
Test
Point
V
I
R
1
= 2.5k
C
T
Simulated TTL Load
R
L
= 60k
1%
MMD6150
or Equiv
MMD7000
or Equiv
Test
Point
R
L
= 2.67k
1%
C
T
C
T
1.0
F
100k
100k
1k
NTE778A
or Equiv
+
1
12
24
13
1.300 (33.02)
Max
.520
(13.2)
.600 (15.24)
1.100 (27.94)
.100 (2.54)
.225
(5.73)
Max
.126
(3.22)
Min