PRODUCT SPECIFICATION
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 1 of 10
February 7
th
2002
10-Bit 80MSPS 0.18
m
Analog-to-Digital Converter IP
FEATURES
1.8V power supply
SNR typ 59dB for (f
in
= 10MHz)
Low power (50mW @ 1.8V and
80MSPS)
Compact area (0.86mm
2
)
Frequency dependent biasing
Differential input
Low input capacitance
Three power saving idle modes
APPLICATIONS
Imaging
Wireless communication
WLAN/IEEE 802.11x
DVB receivers
Powerline communication
Video products
GENERAL DESCRIPTION
The nAD1080-18 is a compact, high-speed, low power 10-bit monolithic analog-to-
digital converter, implemented in a 0.18
m single poly CMOS process with MiM
capacitor option. The converter includes a high bandwidth sample and hold. Using
internal references, the full scale range is
0.75V. The full scale range can be set
between
0.5V and
0.75V using external references. It operates from a single 1.8V
supply. Its low distortion and high dynamic range offers the performance needed for
demanding imaging, multimedia, telecommunications and instrumentation
applications. The bias current level for the ADC is automatically adjusted based on
the clock input frequency. Hence, the power dissipation of the device is continuously
minimised for the current operation frequency.
The nAD1080-18 has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 9 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD1080-18 is compact. The core occupies
less than 0.9mm
2
of die area in a standard single poly 0.18
m CMOS process with
MiM capacitor option. The fully differential architecture makes it insensitive to
substrate noise. Thus it is ideal as a mixed signal ASIC macro cell.
QUICK REFERENCE DATA
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
DD
Supply voltage
1.6
1.8
2.0
V
P
D
Power dissipation
(80 MSPS)
Except digital
output drivers
50
mW
DNL
Differential nonlinearity
f
IN
=0.9991MHz
0.5
LSB
INL
Integral nonlinearity
f
IN
=0.9991MHz
0.75
LSB
SNR
Signal to noise ratio
f
IN
=10MHz
56
59
dB
SFDR
Spurious free dynamic
range
f
IN
=10MHz
70
dB
Table 1: Quick reference data
nAD1080-18
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 2 of 10
February 7
th
2002
ELECTRICAL SPECIFICATIONS
(
At T
A
= 25
C, V
DD
= 1.8V, Sampling Rate = 80MHz, Input frequency = 10MHz, Differential input
signal, 50% duty cycle clock and 300nF Reference decoupling unless otherwise noted
)
Symbol Parameter (condition)
Test
Level
Min.
Typ.
Max.
Units
DC Accuracy
DNL
Differential Nonlinearity
f
IN
= 0.9991 MHz
IV
0.5
LSB
INL
Integral Nonlinearity
f
IN
= 0.9991 MHz
IV
0.75
LSB
V
OS
Midscale offset
1
%FS
CMRR
Common Mode Rejection Ratio
-59
dB
G
Gain Error
1
%FS
Dynamic Performance
SNR
Signal to Noise Ratio (without
harmonics)
f
IN
= 10 MHz
IV
56
59
dBFS
f
IN
= 40 MHz
IV
55
58.5
dBFS
f
IN
= 72 MHz
1)
IV
51.5
55.5
dBFS
SINAD
Signal to Noise and Distortion Ratio
f
IN
= 10 MHz
IV
58
dBFS
SFDR
Spurious Free Dynamic Range
f
IN
= 10 MHz
IV
70
dB
f
IN
= 40 MHz
IV
57
dB
f
IN
= 72 MHz
IV
53.5
dB
Analog Input
V
FSR
Input Voltage Range (differential)
IV
0.75
V
V
CMI
Analog input common mode voltage
IV
0.8
0.9
1.0
V
C
INA
Input Capacitance (from each input to
ground)
1.5
pF
Input signal attenuation @ 70MHz
0.35
dB
Reference Voltages
V
REFN
Internal reference voltage on pin 10
IV
0.525
V
V
REFP
Internal reference voltage on pin 11
IV
1.275
V
Internal reference voltage drift
100
ppm/
C
V
REFN
Negative Input Voltage (external ref)
IV
0.525
V
V
REFP
Positive Input Voltage (external ref)
IV
1.275
V
V
RR
Reference input voltage range
2)
IV
0.75
V
V
CM
Common mode voltage output
IV
0.9
V
Switching Performance
F
S max
Maximum Conversion Rate
IV
80
105
MSPS
F
S min
Minimum Conversion Rate
10
MSPS
Pipeline Delay
IV
6
Clocks
t
AP
Aperture delay, IP
V
0.9
ns
t
h
Output hold time, IP (0.1 - 0.8 pF load)
V
0.5
1
2.3
ns
t
d
Output delay time, IP (0.1 - 0.8 pF load)
V
1.1
2
2.6
ns
t
AP
Aperture delay, with bonding pad
V
1.0
ns
t
h
Output hold time, with bonding pad
V
1.0
ns
t
d
Output delay time, with bonding pad
V
4.0
ns
Digital Inputs
V
IL
Logic "0" voltage
IV
0.4
V
V
IH
Logic "1" voltage
IV
AV
DD
0.4
V
I
IL
Logic "0" current (V
I
=V
SS
)
IV
10
A
I
IH
Logic "1" current (V
I
=V
DD
)
IV
10
A
C
IND
Input Capacitance
IV
0.03
0.1
pF
(table continued on next page)
1)
Requires clock source jitter in the order of 1ps.
2)
See Figure 5.
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 3 of 10
February 7
th
2002
Digital Outputs
V
OL
Logic "0" voltage (I = 2 mA)
IV
0.2
0.4
V
V
OH
Logic "1" voltage (I = 2 mA)
IV
85% OV
DD
90% OV
DD
V
Power Supply
V
DD
Supply voltage
V
1.6
1.8
2.0
V
I
DD
Supply current (except digital output)
IV
27.8
mA
V
SS
Supply voltage
GND
P
D
Power dissipation (except digital output)
(active 10 MSPS)
IV
8
mW
P
D
Power dissipation (except digital output)
(active 80 MSPS)
IV
50
mW
P
D
Power dissipation (except digital output)
Power Down Mode
IV
45
W
P
D
Power dissipation (except digital output)
Sleep Mode
IV
2.2
mW
P
D
Power dissipation (except digital output)
Standby Mode
IV
8.5
mW
t
start
Start-up time from Power down
1.3
ms
t
start
Start-up time from Sleep mode
2
s
t
start
Start-up time from Stand By
8
clock cycles
OV
DD
Output driver supply voltage
1.6
1.8
3.6
V
T
Junction operating temperature
-40
+125
C
Table 2: Electrical specifications
Test Levels
Test Level I: 100% production tested at +25C
Test Level II: 100% production tested at +25C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterization testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25C. Guaranteed by design and
characterization testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
V
DD
............................... - 0.2V to +2.2V
OV
DD
.............................. - 0.2V to 3.6V
Input voltages
Analog In ............ - 0.2V to V
DD
+ 0.2V
Digital In ........................ - 0.2V to 3.6V
REF
P
.................... - 0.2V to V
DD
+ 0.2V
REF
N
................... - 0.2V to V
DD
+ 0.2V
CLOCK.......................... - 0.2V to 3.6V
Temperatures
Operating Temperature....-40 to +125
C
Storage Temperature.. - 65 to +125
C
Note: Stress above one or more of the limiting values may cause permanent damage
to the device.
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 4 of 10
February 7
th
2002
PIN FUNCTIONS
Table 3: Pin functions
IP BLOCK LAYOUT
IP_footprint
REFP
REFN
B
I
A
S
1
B
I
A
S
0
P
D
V
C
M
I
N
P
I
N
N
CLOCK
O
V
R
B
I
T
O
[
9
:
0
]
AVSS
AVDD
AVSS
AVDD
VDD
Y
=
7
1
1
u
m
AVSS
AVDD
AVSS
AVDD
VDD
VDD
VDD
E
X
T
R
E
F
R
B
I
A
S
BIAS_CLOCK
X=1208um
Figure 1: Size and pin placement for nAD1080-18 IP
FUNCTIONAL BLOCK DIAGRAM
CURRENT
BIAS
VOLTAGE
REFERENCE
DIGITAL
CLOCK
DRIVER
PIPELINE CHAIN
INN
INP
REFP
REFN
E
X
T
R
E
F
R
B
I
A
S
B
I
A
S
0
B
I
A
S
1
P
D
B
I
A
S
_
C
L
O
C
K
C
L
O
C
K
B
I
T
O
[
9
:
0
]
O
V
R
VCM
Figure 2: Functional Block diagram nAD1080-18
Pin Name
Description
INP, INN
Differential input signal pins. Common mode voltage: V
CMI
(See Electrical specifications)
REFP, REFN
Reference pins (output/bypass). Bypass with 300nF capacitors close to the pins. (See Application
Information)
BIAS0, BIAS1,
RBIAS, PD
Operating mode and bias control pins. (See Modes of operation)
CLOCK
ADC Clock
BIAS_CLOCK
Clock used for bias current generation
VCM
Common mode voltage output
BITO[15:0]
Digital outputs ( MSB to LSB)
OVR
Over-Range flag
EXTREF
Disables internal voltage references when high. External voltages must be applied to REFN and REFP.
VDD
Digital power
AVDD
Analog power
AVSS
Analog and digital ground
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 5 of 10
February 7
th
2002
MODES OF OPERATION
The ADC has four different modes of operation, controlled as described in Table 4:
Digital control and clock settings
Mode of operation
BIAS0
BIAS1
RBIAS
PD
BIAS_CLOCK
CLOCK
Active
HIGH
HIGH
LOW
LOW
Running
Running
Standby
LOW
LOW
LOW
LOW
Running
Stopped
Sleep
LOW
LOW
HIGH
LOW
Stopped
Stopped
Power down
LOW
LOW
LOW
HIGH
Stopped
Stopped
Table 4: Control settings for ADC operational modes
Active mode
In the active mode, the ADC is fully functional.
A performance versus power consumption trade off can be made by adding or
subtracting 12.5% of the pipeline bias current with the bias1 and bias0 pins:
BIAS0
BIAS1
CURRENT
1
0
-12.5%
0
1
+12.5%
1
1:
Typical
Idle modes
In the three idle modes, the ADC is not functional. The different modes are
distinguished primary by power consumption and start-up time. Start-up time is
defined as the time it takes for the ADC to reach full performance in active mode
when switched from an idle mode. Refer to `Electrical Specifications' for power
consumption and start-up times for the different modes.
While the start-up times for standby and sleep modes are constant, the start-up time in
power down mode will be proportional to Off-Chip REFP,REFN decoupling. The
amount of decoupling on the REFP and REFN will have impact on the performance
(see Characterization report).
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 6 of 10
February 7
th
2002
TIMING DIAGRAM
DATA
CLOCK
S
A
M N - 1
P
L
E
S
A
M N + 1
P
L
E
S
A
M N
P
L
E
Data
N
Data
N-1
Data
N+1
t
d
t
AP
S
A
M N + 2
P
L
E
t
h
Figure 3: Timing diagram
INPUT SIGNAL RANGE
V
REFP
V
REFN
V
CMI
V
INP
V
INN
V
INP
-V
INN
V
RR
+V
RR
-V
RR
V
FSR
Figure 4: Definition of full scale range
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 7 of 10
February 7
th
2002
DEFINITIONS
Data sheet status
Objective product specification
This datasheet contains target specifications for product development.
Preliminary product
specification
This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.
Product specification
This datasheet contains final product specifications.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 5: Definitions
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree fully indemnify Nordic VLSI ASA for
any damages resulting from such improper use or sale.
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 8 of 10
February 7
th
2002
APPLICATION INFORMATION
References
The nAD1080-18 has a differential analog input. The input full scale range is equal to
(V
REFP
-V
REFN
) which is the voltage difference between the reference pins REFP and
REFN. See
Figure 4
for details. Reference voltages are generated internally for a full
scale range of
0.75V. The reference voltages can be set externally by setting the
EXTREF pin high. Use an appropriate operation amplifier to drive the voltages on
pins REFP and REFN. A design example can be found in the Evaluation Board user
Guide. Externally generated reference voltages connected to REFP and REFN
should
be symmetrical around 0.9V. The input full scale range can be defined between
0.5V
and
0.75V. The references should be bypassed to ground as close to the converter
pins as possible using at least 300nF capacitors in parallel with smaller capacitors (e.g.
1nF).
Analog input
The input of the nAD1080-18 can be configured in various ways - dependent upon
whether a single ended or differential, AC- or DC-coupled input is wanted.
AC-coupled input is most conveniently implemented using a transformer with a center
tapped secondary winding. The center tap is connected to the VCM pin as shown in
figure 6. In order to obtain low distortion, it is important that the selected transformer
does not exhibit core saturation at full-scale. Excellent results are obtained with the
Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input
signal purity. A small capacitor across the inputs attenuates kickback-noise from the
sample and hold. Series resistors as shown in Figure 6 may be advantageous to
improve linearity. The VCM-node should be bypassed to ground as closed to the
converter pin as possible using 100nF capacitors in parallel with a small one.
INP
INN
VCM
Mini Circuits
T1-6T
V
in
ADC
51
50
50
22pF
Figure 5: Example of AC coupled input using transformer configuration
If a DC-coupled single ended input is wanted, a solution based on operational
amplifiers is usually preferred. Using the AD8138 single ended to differential
amplifier gives excellent results. However, low cost operational amplifiers may be
used if the requirements are less strict.
Clock
In order to preserve accuracy at high input frequency, it is important that the clock has
low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 9 of 10
February 7
th
2002
possible. Overshoot should be avoided. Low jitter is especially important when
converting high frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB.
It is therefore recommended that the clock trace on the PCB is made as short as
possible. Make sure that noise from the digital output bits does not couple into the
clock power supply. The harmonic distortion of the ADC will in that case increase
since the output bits are input signal dependent.
The SNR caused by clock jitter can be calculated by equation 1 where clock jitter is
the only source of noise. This equation applies to any number of bits and sampling
frequencies.
)
2
log(
20
rms
in
f
SNR
-
=
(1)
rms
is the RMS value of the total system jitter measured in seconds. f
in
is the input
signal frequency.
Digital outputs
The digital output data appears in offset binary code at CMOS logic levels. Full-scale
negative input results in output code 000...0. Full-scale positive input results in output
code 111...1. Output data are available 6 clock cycles after the data are sampled. The
analog input is sampled one aperture delay (t
AP
) after the high to low clock transition.
Output data should be sampled as shown in the timing diagram.
PCB layout and decoupling
A well designed PCB is necessary to get good spectral purity from any high
performance ADC. A multilayer PCB with a solid ground plane is recommended for
optimum performance. If the system has a split analog and digital ground plane, it is
recommended that all ground pins on the ADC are connected to the analog ground
plane. It is our experience that this gives the best performance. The power supply pins
should be bypassed using 100nF in parallel with 1nF surface mounted capacitors as
close to the package pins as possible. Analog and digital supply pins should be
separately filtered.
Dynamic testing
Careful testing using high quality instrumentation is necessary to achieve accurate test
results on high speed A/D-converters. It is important that the clock source and signal
source has low jitter. A spectrally pure, low noise RF signal generator - such as the
HP8662A or HP8644B is recommended for the test signal. Low pass filtering or band
pass filtering of the input signal is usually necessary to obtain the required spectral
purity (SFDR > 75dB). The clock signal can be obtained from either a crystal
oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can
be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used.
The most consistent results are obtained if the clock signal is phase locked to the input
signal. Phase locking allows testing without windowing of output data. A logic
analyzer with deep memory - such as the HP16500-series, is recommended for test
data acquisition.
PRODUCT SPECIFICATION
nAD1080-18: 10 Bit 80 MSPS 0.18
m ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 4.1
Page 10 of 10
February 7
th
2002
DESIGN CENTER
Nordic VLSI ASA
Vestre Rosten 81
N-7075 TILLER
NORWAY
Telephone:
+47 72898900
Telefax:
+47 72898989
E-mail: For further information regarding our state of the art data converters, please e-
mail us at datacon@nvlsi.no.
World Wide Web/Internet: Visit our site at http://www.nvlsi.no.
ORDERING INFORMATION
Type number
Description
Price
nAD1080-18-IC
nAD1080-18 sample in SSOP28 package
(limited availability)
USD 50
nAD1080-18-EVB
nAD1080-18 evaluation board including
characterisation report and user guide
USD 300
Table 6: Ordering information
Product Specification. Revision Date: February 7
th
, 2002
All rights reserved . Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder. Company and product names referred to in
this datasheet belong to their respective copyright/trademark holders.
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