PRELIMINARY PRODUCT SPECIFICATION
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 1 of 11
November 15th, 2001
12-Bit 60MSPS Sampling
Analog-to-Digital Converter IP
FEATURES
2.5V power supply
SNR typ 66dB for (f
in
= 10MHz)
Low power (150mW@2.5V)
Sample rate: 10-60MSPS
Frequency dependent biasing
Internal/sample hold
Differential input
Low input capacitance
APPLICATIONS
Imaging
Test equipment
Computer scanners
Communications
Set top boxes
Video products
GENERAL DESCRIPTION
The nAD1260-25 is a compact, high-speed, low power 12-bit monolithic analog-to-
digital converter, implemented in the TSMC Mixed-Signal MiM CMOS process.
Versions with metal3 to metal5 as top metal are available. The MiM capacitor uses
metal2 as bottom plate as standard configuration. It has 12-bit resolution with close to
11 effective bits, and close to 12 bit dynamic range for video frequency signals. The
converter includes a high bandwidth sample and hold. The full scale range is
1V.
The full scale range can be set between
0.5V and
1V. It operates from a single
2.5V supply. Its low distortion and high dynamic range offers the performance needed
for demanding imaging, multimedia, telecommunications and instrumentation
applications.
The bias current level for the ADC is automatically adjusted based on the clock input
frequency. Hence, the power dissipation of the device is continuously minimised for
the current operation frequency.
QUICK REFERENCE DATA
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
DD
Supply voltage
2.25
2.5
2.75
V
I
DD
Supply current
(60 MSPS)
60
mA
P
D
Power dissipation
(60 MSPS)
Except digital
output drivers
150
mW
P
D
Power dissipation
(10 MSPS)
Except digital
output drivers
30
mW
P
D
Power dissipation
(sleep mode)
Except digital
output drivers
1.5
mW
DNL
Differential
nonlinearity
f
IN
=0.9991MHz
1
LSB
INL
Integral nonlinearity
f
IN
=0.9991MHz
3
LSB
f
S
Conversion rate
10
60
MHz
N
Resolution
12
bit
Table 1. Quick reference data
nAD1260-25
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 2 of 11
November 15th, 2001
GENERAL DESCRIPTION (Continued)
The nAD1260-25 has a pipelined architecture - resulting in low input capacitance.
Digital error correction of the 11 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The nAD1260-25 is compact. The core occupies
1,65mm
2
die area in TSMC Mixed Signal MiM 0.25
m CMOS process. The fully
differential architecture makes it insensitive to substrate noise. Thus it is ideal as a
mixed signal ASIC macro cell.
BLOCK DIAGRAM
Figure 1. Block diagram nAD1260-25
BGREF
STAGE3
STAGE10
2B_FLASH
DIGITAL DELAYS, ERROR CORRECTION AND OUTPUT REGISTER
CLOCKDR
BIT(11:0)
REFP
REFN
INP
INN
CLK
BIASCELL
RBIAS_CTR
REFBUF
BIAS1
BIAS0
STAGE2
STAGE1
CM
OR
OUTEN
REFBUF
REFPFB
REFNFB
EXTREF
PD
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 3 of 11
November 15th, 2001
ELECTRICAL SPECIFICATIONS
(
At T
A
= 25
C, V
DD
= 2.5V, Sampling Rate = 60MHz, Input frequency = 10MHz dBFS, Differential
input signal, 50% duty cycle clock unless otherwise noted).
Symbol Parameter (condition)
Test
Level
Min.
Typ.
Max.
Units
DC Accuracy
DNL
Differential Nonlinearity
f
IN
= 0.9991 MHz
III
0.5
1.0
LSB
INL
Integral Nonlinearity
f
IN
= 0.9991 MHz
III
1.0
3.0
LSB
V
OS
Midscale offset
III
TBD
mV
CMRR
Common Mode Rejection Ratio (of V
OS
)
TBD
dB
Dynamic Performance
SINAD
Signal to Noise and Distortion Ratio
f
IN
= 10 MHz
III
66
dBFS
f
IN
= 40 MHz
III
60
dBFS
SNR
Signal to Noise Ratio (without
harmonics)
f
IN
= 10 MHz
III
66
dBFS
SFDR
Spurious Free Dynamic Range
f
IN
= 10 MHz
III
75
dBFS
f
IN
= 40 MHz
III
60
70
dBFS
PSRR
Power Supply Rejection Ratio (of V
OS
)
III
-55
dB
Analog Input
V
FSR
Input Voltage Range (differential)
IV
+0.5
1.0
V
V
CMI
Common mode input voltage
III
1
1.15
1.3
V
C
INA
Input Capacitance (differential)
III
2.5
pF
Reference Voltages
V
REFN
Negative Input Voltage
III
0.65
V
V
REFP
Positive Input Voltage
III
1.65
V
V
RR
Reference input voltage range
1
III
0.5
1
1.05
V
V
CM
Common mode output voltage
III
1.15
V
Digital Inputs
V
IL
Logic "0" voltage
IV
0.4
V
V
IH
Logic "1" voltage
IV
AV
DD
-0.4
V
I
IL
Logic "0" current (V
I
=V
SS
)
IV
10
A
I
IH
Logic "1" current (V
I
=V
DD
)
IV
10
A
C
IND
Input Capacitance
IV
5
pF
Digital Outputs
V
OL
Logic "0" voltage (I = 2 mA)
IV
0.2
0.4
V
V
OH
Logic "1" voltage (I = 2 mA)
IV
85% OV
DD
90% OV
DD
V
t
H
Output hold time
V
1.9
ns
t
D
Output delay time
V
7.2
ns
(table continued on next page)
1
See "Input Signal Range" section
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 4 of 11
November 15th, 2001
Switching Performance
f
S
Conversion Rate
V
10
60
MSPS
Pipeline Delay
IV
7
Clocks
AP
Aperture jitter
V
TBD
ps
t
AP
Aperture delay
V
0.8
ns
Power Supply
V
DD
supply voltage
V
2.25
2.5
2.75
V
I
DD
supply current (except digital output)
IV
60
mA
P
D
power dissipation (except digital output)
(60 MSPS)
IV
150
mW
P
D
power dissipation (except digital output)
(10 MSPS)
IV
30
mW
P
D
power dissipation (except digital output)
(sleep mode)
1)
IV
1.5
mW
V
SS
supply voltage
GND
AV
DD
-
DV
DD1
analog power digital power pins
-0.2
+0.2
V
OV
DD
Output driver supply voltage
III
2.25
2.5/3.0
3.3
V
T
Ambient operating temperature
IV
-40
+85
C
Table 3. Electrical specifications
1)
Power Down Mode ("zero" power dissipation) available for IP version of nAD1260-25
Test Levels
Test Level I: 100% production tested at +25C
Test Level II: 100% production tested at +25C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterisation testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25C. Guaranteed by design and
characterisation testing for industrial temperature range
ABSOLUTE MAXIMUM RATINGS
Supply voltages
AV
DD
............................... - 0.3V to +3V
DV
DD1
................. - 0.3V to V
DD
+ 0.3V
OV
DD
................... - 0.3V to V
DD
+ 0.3V
Input voltages
Analog In ......... - 0.3V to AV
DD
+ 0.3V
Digital In ............. - 0.3V to V
DD
+ 0.3V
REF
P
................. - 0.3V to AV
DD
+ 0.3V
REF
N
................ - 0.3V to AV
DD
+ 0.3V
CLOCK............... - 0.3V to V
DD
+ 0.3V
Temperatures
Operating Temperature....-40 to +85
C
Storage Temperature.....-65 to +125
C
Note: Stress above one or more of the
limiting values may cause permanent
damage to the device.
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 5 of 11
November 15th, 2001
PIN FUNCTIONS
Bondpad
Pin Name
Description
Package
Pin number(s)
INP, INN
Differential input signal pins.
23,22
REFP, REFN
Reference input pins. Decouple assording to Application-
Information.
19,18
CLK
ADC clock.
28
BIAS0,BIAS1
Package Pin name: BIAS01
BIAS01=0: Sleep mode
BIAS01=1: Normal operation
Note: BIAS01 is a double bonding of the bondpad
signals: BIAS0 and BIAS1.
See Integration Instruction for more detailed information
26
RBIAS_CTR
Adds a clock input independent bias current.
This signal will allow power up even if the Clock is
stopped.
See Integration Instruction for more detailed information
27
CM
Common mode voltage output
20
BIT11 - BIT0
Digital outputs (MSB to LSB)
1-6, 9-14
OR
Over Range Available with bonding option.
NC
OE
Output enable Available with bonding option.
NC
EXTREF
Disables internal references when high
17
PD
Power Down when high. Available with bonding option
NC
AVDD
Analog power pins
25,16
VDD
Digital power pin
16
OVDD
Output driver power pin
7
AVSS
Ground pins
15,8,21.
Table 1. Pin functions for nAD1260-25
PIN ASSIGNMENT
Figure 2. Pin assignment for the 28 pin package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BIT11
BIT10
BIT9
BIT8
BIT7
BIT4
BIT3
BIT2
BIT1
BIT0
BIT5
V
SS
OV
DD
BIT6
CM
BIAS01
REFN
REFP
CLK
RBIAS_CTR
INP
INN
EXTREF
V
SS
V
DD
V
SS
V
DD
V
SS
nAD1260-025
28 PIN SSOP
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 6 of 11
November 15th, 2001
IP BLOCK OUTLINE
The height and width of the layout is: X =1642
m and Y=1000
m respectively
Figure 2. IP block outline and pin placement for nAD1260-25
TIMING DIAGRAM
Figure 4. Timing diagram
Y
=
1
0
0
0
u
m
X=1642um
CLK
I
N
P
I
N
N
C
M
R
B
I
A
S
_
C
T
R
B
I
A
S
0
B
I
A
S
1
E
X
T
R
E
F
P
D
REFP
REFN
REFPFB
REFNFB
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
VDD
VDD
OUTEN
OR
BIT(11:0)
IP_nAD1260_25_tsmc
DATA
CLOCK
Data
Data
N-2
Data
N
t
d
t
AP
t
h
S
A
M N - 1
P
L
E
S
A
M N
P
L
E
S
A
M N + 1
P
L
E
S
A
M N + 2
P
L
E
INPUT
N-1
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 7 of 11
November 15th, 2001
INPUT SIGNAL RANGE
Figure 5. Definition of full scale range
DEFINITIONS
Data sheet status
Objective product specification
This datasheet contains target specifications for product development.
Preliminary product
specification
This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.
Product specification
This datasheet contains final product specifications.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 5. Definitions
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA
for any damages resulting from such improper use or sale.
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 8 of 11
November 15th, 2001
APPLICATION INFORMATION
References
The nAD1260-25 has a differential analog input. The input range is determined by the
voltages on the reference pins REFP and REFN respectively, and is equal to
(VREFP-VREFN). Externally generated reference voltages connected to REFP and
REFN
should be symmetric around 1.15V. The input range can be defined between
0.5V and
1.0V. The references should be bypassed as close to the converter pins as
possible using 1
F capacitors in parallel with smaller capacitors (e.g. 1nF). There
should be decoupling between the references, and from each reference to ground.
Analog input
The input of the nAD1260-25 can be configured in various ways - dependent upon
whether a single ended or differential, AC- or DC-coupled input is wanted.
AC-coupled input is most conveniently implemented using a transformer with a centre
tapped secondary winding. The centre tap is connected to the CM-node, as shown in
figure 6. In order to obtain low distortion, it is important that the selected transformer
does not exhibit core saturation at full-scale. Excellent results are obtained with the
Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input
signal purity. A small capacitor (typ. 21pF) across the inputs attenuates kickback-
noise from the sample and hold. The CM-pin should be decoupled as close to the
package as possible with a 100nF capacitor in parallel with a 1nF capacitor.
21pF
INP
INN
CM
Mini Circuits
T1-6T
V
in
ADC
51
Figure 6. AC coupled input using transformer
If a DC-coupled single ended input is wanted, a solution based on operational
amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for
low distortion and video bandwidth. Lower cost operational amplifiers may be used if
the demands are less strict. A good alternative for high performance applications is to
use AD8138 single ended to differential amplifier.
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 9 of 11
November 15th, 2001
AD826
AD826
51
51
470
470
100
100
470
470
AD826
51
IN
P
IN
N
51
470
Input
offset
Video
in
ADC
15pF
Figure 7. DC-coupled single ended to differential conversion (power supplies and
bypassing not shown)
Clock
In order to preserve accuracy at high input frequency, it is important that the clock has
low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever
possible. Overshoot should be avoided. Low jitter is especially important when
converting high frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB.
It is therefore recommended that the clock trace on the PCB is made as short as
possible.
Digital outputs
The digital output data appears in offset binary code. Full-scale negative input results
in output code 000...0. Full-scale positive input results in output code 111...1. Output
data are available 7 clock cycles after the data are sampled. The analog input is
sampled one aperture delay (t
AP
) after the high to low clock transition. Output data
should be sampled as shown in the timing diagram.
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 10 of 11
November 15th, 2001
PCB layout and decoupling
A well designed PCB is necessary to get good spectral purity from any high
performance ADC. A multilayer PCB with a solid ground plane is recommended for
optimum performance. If the system has a split analog and digital ground plane, it is
recommended that all ground pins on the ADC are connected to the analog ground
plane. It is our experience that this gives the best performance. The power supply pins
should be bypassed using 100nF || 1nF surface mounted capacitors as close to the
package pins as possible. Analog and digital supply pins should be separately filtered.
Dynamic testing
Careful testing using high quality instrumentation is necessary to achieve accurate test
results on high speed A/D-converters. It is important that the clock source and signal
source has low jitter. A spectrally pure, low noise RF signal generator - such as the
HP8662A or HP 8644B is recommended for the test signal. Low pass filtering or band
pass filtering of the input signal is usually necessary to obtain the required spectral
purity (SFDR > 75dB). The clock signal can be obtained from either a crystal
oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can
be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used.
The sinewave clock must then be applied to an ultra high-speed comparator (e.g.
MAX961) before application to the converter. The most consistent results are
obtained if the clock signal is phase locked to the input signal. Phase locking allows
testing without windowing of output data. A logic analyser with deep memory - such
as the HP16500-series, is recommended for test data acquisition.
PRELIMINARY PRODUCT SPECIFICATION
nAD1260-25 12 Bit 60 MSPS Sampling ADC IP
Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 2.0
Page 11 of 11
November 15th, 2001
DESIGN CENTER
Nordic VLSI ASA
Vestre Rosten 81
N-7075 TILLER
NORWAY
Telephone:
+47 72898900
Telefax:
+47 72898989
E-mail: For further information regarding our state of the art data converters, please e-
mail us at datacon@nvlsi.no.
World Wide Web/Internet: Visit our site at http://www.nvlsi.no.
ORDERING INFORMATION
Type number
Description
Price
Available
nAD1260-25-IC
nAD1260-25 sample in SSOP28
package (limited availability)
USD 50
February 15
th
,
2002
nAD1260-25-EVB
nAD1260-25 evaluation board
including characterisation report and
user guide
USD 300
February 15
th
,
2002
Table 6. Ordering information
Revision Date: November 15
th
2001.
All rights reserved . Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder. Company and product names referred to in
this datasheet belong to their respective copyright/trademark holders.
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