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1/19
Semiconductor
MSM81C55-5RS/GS/JS
GENERAL DESCRIPTION
The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses
silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum,
while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5
can be used in an MSM80C85AH system without using wait states. The parallel I/O consists
of two 8-bit ports and one 6-bit port (both general purpose).
The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for
sequence-wave generation or terminal count-pulsing.
FEATURES
High speed and low power achieved with silicon gate CMOS technology
256 words x 8bits RAM
Single power supply, 3 to 6 V
Completely static operation
On-chip address latch
8-bit programmable I/O ports (port A and B)
TTL Compatible
RAM data hold characteristic at 2 V
6-bit programmable I/O port (port C)
14-bit programmable binary counter/timer
Multiplexed address/data bus
Direct interface with MSM80C85AH
40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS)
44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS)
44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K)
FUNCTIONAL BLOCK DIAGRAM
Semiconductor
MSM81C55-5RS/GS/JS
2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER
IO/M
AD
0 - 7
CE
ALE
RD
WR
RESET
TIMER IN
TIMER OUT
Timer
256 8
Static
RAM
A
B
C
8
8
6
Port A
Port B
Port C
PA
0 - 7
PB
0 - 7
PC
0 - 5
V
CC
(+5 V)
GND (0 V)
E2O0014-27-X2
This version: Jan. 1998
Previous version: Aug. 1996
2/19
Semiconductor
MSM81C55-5RS/GS/JS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
44 pin Plastic QFP
16
15
14
13
PC
3
TIMER IN
RESET
TIMER OUT
IO/M
CE
RD
WR
ALE
20
19
18
17
GND
PC
2
PC
1
PC
0
PB
7
PB
6
PB
5
PB
4
PB
3
PB
2
PB
1
PB
0
PA
7
PA
6
PA
5
PA
4
1
2
3
4
5
6
7
8
9
10
11
12
32
31
30
29
28
27
26
37
38
39
40
36
35
34
33
25
PA
3
PA
2
PA
1
PA
0
24
23
22
21
V
CC
AD
7
AD
6
AD
5
PC
4
PC
5
AD
4
AD
3
AD
2
AD
1
AD
0
39
38
37
36
35
34
33
PB
6
PB
5
PB
4
PB
3
PB
2
NC
PB
1
TIMER OUT
IO/M
CE
RD
WR
NC
ALE
18
19
20
21
22
23
24
AD
4
NC
AD
5
AD
6
AD
7
GND
PA
0
6
5
4
3
2
1
44
PC
5
RESET
TIMER IN
PC
4
PC
3
NC
7
8
9
10
11
12
13
32
31
30
29
PB
0
PA
7
PA
6
AD
0
AD
1
AD
2
AD
3
14
15
16
17
PA
5
V
CC
25
26
27
28
PA
1
PA
2
PA
3
PA
4
43
42
41
40
PC
2
PC
1
PC
0
PB
7
44 pin Plastic QFJ
33
32
31
30
29
28
27
PB
6
PB
5
PB
4
PB
3
PB
2
PB
1
PB
0
TIMEROUT
IO/M
CE
RD
WR
ALE
AD
0
12
13
14
15
16
17
18
AD
4
AD
5
AD
6
AD
7
GND
V
CC
PA
0
44
43
42
41
40
39
38
PC
5
RESET
TIMER IN
PC
4
PC
3
V
CC
1
2
3
4
5
6
7
26
25
24
23
PA
7
PA
6
PA
5
AD
1
AD
2
AD
3
NC
8
9
10
11
PA
4
NC
19
20
21
22
PA
1
PA
2
PA
3
NC
37
36
35
34
PC
2
PC
1
PC
0
PB
7
3/19
Semiconductor
MSM81C55-5RS/GS/JS
ABSOLUTE MAXIMUM RATING
55 to +150
MSM81C55-5RS
Power Supply Voltage
V
CC
0.5 to +7
V
Input Voltage
V
IN
0.5 to V
CC
+0.5
V
Output Voltage
V
OUT
0.5 to V
CC
+0.5
V
Storage Temperature
T
STG
C
Power Dissipation
P
D
0.7
W
Parameter
Unit
Symbol
Referenced
to GND
--
Ta = 25C
Conditions
Rating
MSM81C55-5GS
MSM81C55-5JS
1.0
1.0
OPERATING CONDITION
Range
Power Supply Voltage
V
CC
3 to 6
V
Operating Temperature
T
OP
40 to +85
C
Parameter
Unit
Symbol
RECOMMENDED OPERATING CONDITIONS
Typ.
Power Supply Voltage (81C55)
V
CC
5
V
T
OP
+25
"L" Level Input
V
IL
--
"H" Level Input
V
IH
--
Min.
4.5
40
0.3
2.2
Max.
5.5
+85
+0.8
V
CC
+0.3
Parameter
Unit
Symbol
C
V
V
Supply Voltage (81C55-5)
V
CC
5
4.75
5.25
V
Operating Temperature (81C55-5)
V
OP
+25
40
+70
C
Operating Temperature (81C55)
DC CHARACTERISTICS
Typ.
Max.
"L" Level Output Voltage
V
OL
--
0.45
V
"H" Level Output Voltage
V
OH
--
--
V
--
--
V
Parameter
Unit
Symbol
Min.
--
2.4
4.2
I
OL
= 2 mA
I
OH
= 400 mA
I
OH
= 40 mA
Condition
V
CC
= 4.5 V to 5.5 V
Ta
= 40C to 85C
Input Leak Current
I
LI
--
10
mA
Output Leak Current
I
LO
--
10
mA
10
10
0 V
IN
V
CC
0 V
OUT
V
CC
CE V
CC
0.2 V
V
IH
V
CC
0.2 V
V
IL
0.2 V
Standby Current
Mean Operating
Current
I
CCS
0.1
100
mA
--
5
mA
--
--
Memory cycle
time: 1 ms
I
CC
4/19
Semiconductor
MSM81C55-5RS/GS/JS
AC CHARACTERISTICS
Parameter
Symbol
Unit
Remarks
Max.
Min.
V
CC
= 4.75 V to 5.25 V,
Ta = 40 to +70C
80C85AH 5MHz I/F
Max.
Min.
V
CC
= 4.5 V to 5.5 V,
Ta = 40 to +80C
80C85AH 3MHz I/F
Address/latch Setup Time
t
AL
ns
Latch/address Holt Time
t
LA
ns
37
--
30
--
50
--
30
--
Read/output Delay Time
Latch/read (write) Delay Time
t
LC
ns
40
--
100
--
Address/output Delay Time
t
RD
ns
--
140
--
170
Latch Width
t
AD
ns
--
330
--
400
Read/data Bus Floating Time
t
LL
t
RDF
ns
70
--
100
--
Read (write)/latch Delay Time
t
CL
ns
0
80
0
100
Read (write) Width
t
CC
ns
20
--
20
--
Data In/write Setup Time
t
DW
ns
200
--
250
--
Write/data-in Hold Time
t
WD
ns
100
--
150
--
Recovery Time
t
RV
ns
25
--
0
--
Write/port Output Delay Time
t
WP
ns
200
--
300
--
t
PR
ns
--
300
--
400
Port Input/read Setup Time
Load capaci-
tance: 150 pF
t
RP
ns
Read/port Input Hold Time
t
SBF
ns
50
--
10
--
70
--
50
--
Strobe Width
Strobe/buffer Full Delay Time
t
SS
ns
--
300
--
400
Strobe/buffer Empty Delay Time
t
RBE
ns
150
--
200
--
Strobe/interrupt-on Delay Time
t
SI
ns
--
300
--
400
t
RDI
ns
--
300
--
400
Read/interrupt-off Delay Time
Port Input/strobe Setup Time
t
PSS
ns
--
300
--
400
Strobe/port-input Hold Time
t
PHS
ns
20
--
50
--
Strobe/buffer-empty Delay Time
t
SBE
ns
100
--
120
--
Write/buffer-full Delay Time
t
WBF
ns
--
300
--
400
t
WI
ns
--
300
--
400
Write/interrupt-off Delay Time
ns
Time Output Delay Time Low
t
TL
ns
--
300
--
400
Time Output Delay Time High
t
TH
ns
--
300
--
400
t
RDE
ns
--
300
--
400
Read/data Buse Enable Delay Time
Timer Cycle Time
t
CYC
ns
10
--
10
--
t
r
,
t
f
ns
320
--
320
--
Timer Input Rise and Fall Times
Timer Input Low Level Time
t
1
ns
--
80
--
80
t
2
ns
40
--
80
--
Timer Input High Level Time
WRITE to TIMER-IN
for writes which start counting
t
WT
ns
70
--
120
--
t
TW
ns
200
--
200
--
TIMER-IN to WRITE
for writes which start counting
ns
0
--
0
--
Note: Timings are measured wth V
L
= 0.8 V and V
H
= 2.2 V for both input and output.
5/19
Semiconductor
MSM81C55-5RS/GS/JS
TIMING DIAGRAM
Read Cycle
CE
t
AD
Address
Data Valid
t
AL
t
LA
t
LL
t
LC
t
CC
t
RV
t
CL
t
RDE
t
RDF
t
RD
IO/M
AD
0 - 7
ALE
RD
CE
t
AL
t
LA
t
LL
t
CC
t
RV
t
WD
IO/M
AD
0 - 7
ALE
WR
t
LC
t
DW
t
CL
Address
Data Valid
Write Cycle