OKI Semiconductor

FEDSMS81V26000-02

Issue Date: Dec 15, 2004

MS81V26000

1,114,112-Word

24-Bit Field Memory

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GENERAL DESCRIPTION

The OKI MS81V26000 is a high performance 26-Mbit, 1,100K

24-bit, Field Memory. It is especially designed

for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and
Multi-media systems. MS81V26000 is a FRAM for wide or low end use in general commodity TVs and VTRs
exclusively. MS81V26000 is not designed for the other use or high end use in medical systems, professional
graphics systems which require long term picture storage, data storage systems and others. More than two
MS81V26000s can be cascaded directly without any delay devices among the MS81V26000s. (Cascading of
MS81V26000 provides larger storage depth or a longer delay).

Each of the 24-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data
rates between write and read data streams.

The MS81V26000 provides high speed FIFO, First-In First-Out, operation without external refreshing:
MS81V26000 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.

The MS81V26000's function is simple, and similar to a digital delay device whose delay-bit-length is easily set by
reset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.

Additionally, the MS81V26000 has write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to
MS81V26000. The input enable (IE) function allows the user to write into selected locations of the memory only,
leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture"
on a TV screen.

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MS81V26000

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FEATURES

Single power supply: 3.3 V

0.3 V

1,114,112

words

24 bits

Fast FIFO (First-In First-Out) operation

High speed asynchronous serial access

Read/write cycle time 12 ns

Access

time

Randomly accessible leading address

Variable length delay bit (350 to 1,114,112)

Write/Read start address settable

Write mask function (Input enable control)

Data skipping function (Output enable control)

Self refresh (No refresh control is required)

Package

options:

100-pin plastic TQFP

(TQFP100-P-1414-0.50-K) (MS81V26000-xxTB)

xx indicates speed rank.

PRODUCT FAMILY

Family

Access Time (Max.)

Cycle Time (Min.)

Package

MS81V26000-12TB

9 ns

12 ns (83 MHz)

100-pin TQFP

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PIN CONFIGURATION (TOP VIEW)

Pin Name

Function

SWCK

Serial Write Clock

SRCK

Serial Read Clock

WE Write

Enable

RE Read

Enable

IE Input

Enable

OE Output

Enable

RSTW

Write Reset Clock

RSTR

Read Reset Clock

WAD

Write Address Input

RAD

Read Address Input

0 to 23

Data Input

OUT

0 to 23

Data Output

Power Supply (3.3 V)

Ground (0 V)

Power Supply for output

Ground for output

NC No

Connection

Note: The same power supply voltage must be provided to every V

pin and V

Q pin, and the same

GND voltage level must be provided to every V

pin and V

Q pin.

DI4

DI5

DI6

DI7

DI8

DI9

DI10

DI1

DO1

DO10

DO9

DO8

DO7

DO6

100-Pin TQFP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DI3
DI2
DI1
DI0

WAD

RSTW

SWCK

SRCK

RSTR

RAD

DI12
DI13
DI14
DI15

100

DI16

DI17

DI18

DI19

DI20

DI21

DI22

DI23

DO23

DO22

DO21

DO20

DO19

DO18

DO5
DO4
V

DO3
DO2
V

DO1
DO0
V

DO12
DO13
V

DO14
DO15
V

DO16
DO17
V

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PIN DESCRIPTION

Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.

Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.

Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS81V26000 is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.

Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4.

Write Address Input: WAD
These pins are used for write address input.

Data Inputs: (DI0-23)
These pins are used for serial data inputs.

Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.

Data Out: (DO0-23)
These pins are used for serial data outputs.

Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS81V26000.

Read Reset: RSTR
RSTR is used to set the internal read address pointer. RSTR setup and hold times are referenced to the rising edge
of SRCK. The SWCK latches the read address data (21bits serial LSB) from RAD.

Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.

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The latency for the read operation control by RE is 4. After read reset, RE must remain low for more than 1600 ns
(tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought
high.
After read reset, RE should be remained high for 2 cycles after driving RE high first.

Output Enable: OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced
to the rising edge of SRCK. The latency for the read operation control by OE is 4.

Read Address Input: RAD
These pins are used for read address input.

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ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter Symbol

Conditon

Rating Unit

Power Supply Voltage

0.5 to +4.6

Input Output Voltage

at Ta = 25

C, V

0.5 to +4.6

Output Current

C 50

Power Dissipation

C 1

Operating Temperature

opr

0 to 70

Storage Temperature

stg

55 to +150

Recommended Operating Conditions

Parameter Symbol

Min.

Typ

Max. Unit

Power Supply Voltage

3.0

3.3

3.6

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

+0.8 V

DC Characteristics

Parameter Symbol

Condition Min.

Max.

Unit

Input Leakage Current

0 < V

< V

+ 0.3 V, Other Pins Tested at V = 0 V

+10

µA

Output Leakage Current

0 < V

< V

+10

µA

Output "H" Level Voltage

= 2 mA

2.4

Output "L" Level Voltage

= 2 mA

0.4

Operating Current

CC1

Minimum Cycle Time, Output Open

200

Standby Current

CC2

Input Pin = V

Capacitance

= 3.3 V

0.3 V, Ta = 25

C, f = 1 MHz)

Parameter Symbol

Max.

Unit

Input Capacitance

6 pF

Output Capacitance

7 pF

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MS81V26000

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AC Characteristics

= 3.3 V

0.3 V, Ta = 0 to 70

MS81V26000-12

Parameter Symbol

Min. Max.

Unit

Access Time from SRCK

-- 9

OUT

Hold Time from SRCK

DDCK

3 --

OUT

Enable Time from SRCK

DECK

3 9

SWCK "H" Pulse Width

WSWH

4 --

SWCK "L" Pulse Width

WSWL

4 --

Input Data Setup Time

Input Data Hold Time

WE Enable Setup Time

WENS

3 --

WE Enable Hold Time

WENH

1 --

WE Disable Setup Time

WDSS

3 --

WE Disable Hold Time

WDSH

1 --

IE Enable Setup Time

IENS

3 --

IE Enable Hold Time

IENH

1 --

IE Disable Setup Time

IDSS

3 --

IE Disable Hold Time

IDSH

1 --

WE "H" Pulse Width

WWEH

4 --

WE "L" Pulse Width

WWEL

4 --

IE "H" Pulse Width

WIEH

4 --

IE "L" Pulse Width

WIEL

4 --

RSTW Setup Time

RSTWS

3 --

RSTW Hold Time

RSTWH

1 --

SRCK "H" Pulse Width

WSRH

4 --

SRCK "L" Pulse Width

WSRL

4 --

RE Enable Setup Time

RENS

3 --

RE Enable Hold Time

RENH

1 --

RE Disable Setup Time

RDSS

3 --

RE Disable Hold Time

RDSH

1 --

OE Enable Setup Time

OENS

3 --

OE Enable Hold Time

OENH

1 --

OE Disable Setup Time

ODSS

3 --

OE Disable Hold Time

ODSH

1 --

RE "H" Pulse Width

WREH

4 --

RE "L" Pulse Width

WREL

4 --

OE "H" Pulse Width

WOEH

4 --

OE "L" Pulse Width

WOEL

4 --

RSTR Setup Time

RSTRS

3 --

RSTR Hold Time

RSTRH

1 --

SWCK Cycle Time

SWC

12 --

SRCK Cycle Time

SRC

12 --

Transition Time (Rise and Fall)

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MS81V26000-12

Parameter Symbol

Min. Max.

Unit

WE "L" Period before W Reset

LWE

4 --

clk

RE "L" Period before R Reset

LRE

4 --

clk

RE Delay after Reset

FRD

1,600 -- ns

WE Delay after Reset

FWD

1,600 -- ns

Write address input period

WAE

21 --

Clk

Read address input period

RAE

21 --

clk

Latency

Parameter Symbol MS81V26000-12

Unit

Write Latency

clk

Read Latency

clk

WE Write Control Latency

WEL

clk

IE Write Control Latency

IEL

clk

RE Read Control Latency

REL

clk

OE Read Control Latency

OEL

clk

AC Characteristic Measuring Conditions

Output Compare Level

1.4 V

Output Load

1 TTL + 30 pF

Input Signal Level

2.4 V/0.4 V

Input Signal Rise/Fall Time

1 ns

Input Signal Measuring Reference Level

1.4 V

Note: When transition time t

becomes 1 ns or more, the input signal reference levels for the parameter

measurement are V

(min.) and V

(max.).

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OPERATION MODE

Write Operation Cycle
The write operation is controlled by four control signals, SWCK, RSTW, WE and IE. The write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
RSTW must be performed for internal circuit initialization before write operation. WE must be low before and
after the reset cycle (t

LWE

+ t

WAE

+ t

FWD

Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles
while WE and IE are high.

Settings of WE and IE to the operation mode of Write address pointer and Data input.

Internal Write address pointer

Data input (Latency 4)

H H

Input

H L

Incremented

L X

Halted

Not input

X indicates "don't care"

Read Operation Cycle
The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is
accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or
RSTR.
Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles
while RE and OE are high. RE must be low before and after the reset cycle (t

LRE

+ t

RAE

+ t

FWD

Settings of RE and OE to the operation mode of read address pointer and Data output.

Internal Read address pointer

Data output (Latency 4)

H H

Output

H L

Incremented

High impedance

L H

Output

L L

Halted

High impedance

Power-up and Initialization
To assure proper operation of this Memory, place an interval of at least 200

s after Vcc has stabilized to a value

within the range of recommended operating conditions after power-up prior to the operation start. After this 200

stabilization interval, the following initialization sequence must be performed. Because the read and write address
pointers are undefined after power-up, a minimum of 150 dummy write operations (SWCK cycles) and read
operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to
properly initialize the write and the read address pointer.

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MS81V26000

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New Data Read Access
In order to read out "new data," i.e., to read out data that has been written in a follow-up manner, read reset must be
input after write address 150 and the difference between the read address and the write address must be 350 or
more but 1,114,111 or less.

Old Data Read Access
In order to read out "old data," i.e., to read out data that was written prior to the write operation being carried out,
the difference between the read address and the write address must be 0 or more but 30 or less. If the difference
between the read address and the write address is between 31 and 349 or 1,114,112 or more, it is unpredictable
whether the new data is output or whether the old data is output. In this case, however, the write data will be written
normally.

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Read

/
Wri

t
e Cycle

Timing (Ne

Data Re

ad)

SWCK

RSTW

DI 0-23

+ t

Xn-3

Xn-2

148

149 150

151 152

"H"

SRCK

RSTR

DO 0-23

LRE

RAE

+ t

0 1

"H"

4 5

Read

Rese

t sh

ould

inpu

afte

r wri

t
e addre

s
s 150.

ddress differe

n
ce

is 3

50 o

r
more

and 1

,
114

,111

ss.

Xn-1

0 1

he setting ad

dress for read

i
ng an

d that for writing ar

e the

same.

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PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).

TQFP100-P-1414-0.50-K

Mirror finish

Package material

Epoxy resin

Lead frame material

42 alloy

Pin treatment

Solder plating (

5µm)

Package weight (g)

0.55 TYP.

Rev. No./Last Revised

4/Oct. 28, 1996

(Unit: mm)

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MS81V26000

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NOTICE

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an explanation

for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted

by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

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