OKI Semiconductor

FEDS82V16520A-01

Issue Date:Jun. 25, 2002

MS82V16520A

262,144-Word

× 32-Bit × 2-Bank SGRAM

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GENERAL DESCRIPTION

The MS82V16520A is a 16-Mbit system clock synchronous dynamic random access memory.

FEATURES

· 262,144 words

× 32 bits × 2 banks memory (1,024 rows × 256 columns × 32 bits × 2 banks)

· Single 3.3 V

±0.3 V power supply

· LVTTL compatible inputs and outputs
· Programmable burst length (1, 2, 4, 8 and full page)
· Programmable

CAS latency (2, 3)

· Power Down operation and Clock Suspend operation
· 2,048 refresh cycles/32 ms
· Auto refresh and self refresh capability
· Package:

100-pin plastic QFP (QFP100-P-1420-0.65-BK4)

(MS82V16520A-xGA)

x indicates speed rank.

PRODUCT FAMILY

Family

Max. Operating Frequency

Access Time

Package

MS82V16520A-7

143 MHz

6 ns

MS82V16520A-8

125 MHz

6.5 ns

100-pin Plastic QFP

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PIN CONFIGURATION (TOP VIEW)

100

DQ3

VccQ

DQ4
DQ5

VssQ

DQ6
DQ7

VccQ

DQ16
DQ17

VssQ

DQ18
DQ19

VccQ

Vcc

Vss

DQ20

DQ21

VssQ

DQ22
DQ23

VccQ

DQM0
DQM2

CAS
RAS

BA(A10)

DQ28

VccQ
DQ27
DQ26
VssQ
DQ25
DQ24

VccQ

DQ15
DQ14

VssQ

DQ13
DQ12
VccQ

Vss
Vcc

DQ11
DQ10
VssQ
DQ9
DQ8

VccQ

NC
DQM3
DQM1
CLK
CKE
NC
NC

DQ2

VssQ

DQ1

DQ0

Vcc

Vss

DQ31

DQ30

VssQ

DQ29

Vcc

Vss

100-Pin Plastic QFP

Pin Name

Function

Pin Name

Function

A0 to A9

Row Address Inputs

Write Enable

A0 to A7

Column Address Inputs

DQM0 to DQM3

DQ Mask Enable

BA (A10)

Bank Address

DQ0 to DQ31

Data Inputs/outputs

CLK

System Clock Input

Supply

Voltage

CKE Clock

Enable

Ground

Chip Select

Supply Voltage for DQ

RAS

Row Address Strobe

Ground for DQ

CAS

Column Address Strobe

No Connection

Note: The same power supply voltage level must be provided to every V

pin and V

Q pin.

The same GND voltage level must be provided to every V

pin and V

Q pin.

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BLOCK DIAGRAM

Timing

Column

Decoders

Sense

Amplifiers

DQ0

to DQ31

RAS

CAS

A0 to A9

Bank

Controller

Internal

Col.

Address

Counter

I/O

Controller

Column

Address

Buffers

Internal

Row

Address

Counter

Row

Address

Buffers

Row

Decoders

Word

Drivers

8Mb

Memory Cells

Bank A

Read

Data

Output

Buffers

Column

Decoders

Sense

Amplifiers

Input

Data

Input

Buffers

CKE

CLK

DQM0 to

DQM3

32 32

Row

Decoders

Word

Drivers

8Mb

Memory Cells

Bank B

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PIN DESCRIPTION

CLK

Fetches all inputs at the "H" edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.

CKE

Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.

Address

Row & column multiplexed.
Row address: RA0 to RA9, Column address: CA0 to CA7

Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA = "L": Bank A

BA = "H": Bank B

RAS
CAS
WE

Functionality depends on the combination. For details, see the function truth table.

DQM0 to
DQM3

Masks the read data of two clocks later when DQM0 to DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 to DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.

DQ0 to
DQ31

Data inputs/outputs are multiplexed on the same pin.

*Notes: 1. When

is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,

DQM0, DQM1, DQM2, and DQM3 are invalid.

2. When issuing an active, read or write command, the bank is selected by BA.

Active, read or write

0 Bank

1 Bank

3. The auto precharge function is enabled or disabled by the A9 input when the read or write

command is issued.

A9 BA

Operation

After the end of burst, bank A holds the active status.

After the end of burst, bank A is prechaged automatically.

0 1

After the end of burst, bank B holds the active status.

After the end of burst, bank B is prechaged automatically.

4. When issuing a precharge command, the bank to be precharged is selected by the A9 and

BA inputs.

A9 BA

Operation

Bank A is precharged.

Bank B is precharged.

Both banks are precharged.

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COMMAND OPERATION

Mode Register Set Command (

CS, RAS, CAS, WE = "Low")

The MS82V16520A has the mode register that defines the operation mode "

CAS Latency, Burst Length, Burst

Sequence". The Mode Register Set command should be executed just after the MS82V16520A is powered on.
Before entering this command, all banks must be precharged. Next command can be issued after t

RSC

Auto Refresh Command (

CS, RAS, CAS = "Low", WE, CKE = "High")

The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be
performed 2,048 times within 32 ms and the next command can be issued after t

from last Auto Refresh

command. Before entering this command, all banks must be precharged.

Self Refresh Entry/Exit Command (

CS, RAS, CAS, CKE = "Low", WE = "High")

The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left "low".
This operation terminates by making CKE level "high". The self refresh operation is performed automatically by
the internal address counter on the MS82V16520A chip.
In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be
precharged. Next command can be issued after t

Single Bank Precharge Command (

CS, RAS, WE, A9 = "Low", CAS = "High")

The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA.

All Bank Precharge Command (

CS, RAS, WE = "Low", CAS, A9 = "High")

The All Bank Precharge command triggers precharge of both Bank A and Bank B.

Bank Active Command (

CS, RAS = "Low", CAS, WE = "High")

The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to
conventional DRAM's

RAS falling operation. Row addresses "A0 to A9 and BA" are strobed.

Write Command (

CS, CAS, WE, A9 = "Low", RAS = "High")

The Write command is required to begin burst write operation. Then burst access initial bit column address is
strobed.

Write with Auto Precharge Command (

CS, CAS, WE = "Low", RAS, A9 = "High")

The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after
the burst write. Any command that interrupts this operation cannot be issued.

Read Command (

CS, CAS, A9 = "Low", RAS, WE = "High")

The Read command is required to begin burst read operation. Then burst access initial bit column address is
strobed.

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Read with Auto Precharge Command (

CS, CAS = "Low", RAS, WE, A9 = "High")

The Read with Auto Precharge command is required to begin burst read operation with automatic precharge after
the burst read. Any command that interrupts this operation cannot be issued.

No Operation Command (

CS = "Low", RAS, CAS, WE = "High")

The No Operation command does not trigger any operation.

Device Deselect Command (

CS = "High")

The Device Deselect command disables the

RAS, CAS, WE and Address input. This command does not trigger

any operation.

Data Write/Output Enable Command (DQMi = "Low")

The Data Write/Output Enable command enables DQ0 to DQ31 in read or write.
The each DQM0, 1, 2 and 3 corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31
respectively.

Data Mask/Output Disable Command (DQMi = "High")

The Data Mask/Output Disable command disables DQ0 to DQ31 in read or write. In read cycle output buffers are
disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3
corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31 respectively.

Burst Stop Command (

CS, WE = "Low", RAS, CAS = "High")

The Burst Stop command stops burst access when the access is in full page. After the Burst Stop command is
entered, the output buffer goes into high impedance state.

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TRUTH TABLE

Command Truth Table

Address

Function

CS RAS CAS WE

A8 to A0

Device Deselect

No Operation

Mode Register Set

OP. CODE

Auto

Refresh

L L L H

Bank Activate

Read

CA (A7 to A0)

Read with Auto Precharge

CA (A7 to A0)

Write

CA (A7 to A0)

Write with Auto Precharge

CA (A7 to A0)

Precharge Select Bank

Precharge All Banks

Burst

Stop

L H H L

DQM Truth Table

Function DQMi

Data Write/Output Enable

Data Mask/Output Disable

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Function Truth Table (1/2)

Note 1

Current State

CS RAS CAS WE

BA Address

Action

Note

NOP

L H H H

NOP

L H H L BA

ILLEGAL 2

L H L

BA CA,

A9 ILLEGAL

L L H H BA RA Row

Active

L L L L L

Op-Code

Mode

Write

L L H L BA A9 NOP

Idle

L L L H

Auto Refresh/Self refresh

NOP

L H H

NOP

L H L H BA

CA,

Read

L H L L BA

CA,

Write

L L H H BA RA ILLEGAL

L L H L BA A9 Precharge

Active (ACT)

L L L

ILLEGAL

NOP (Continue Row Active after Burst ends)

L H H H

NOP (Continue Row Active after Burst ends)

L H H L

1,2,4,8 Burst Length : ILLEGAL
Full Page Burst : Burst Stop

Row Active

CA, A9 Term Burst, new Read

CA, A9 Term Burst, start Write

L L H H BA RA ILLEGAL

Term Burst, execute Precharge

Read (RD)

L L L

ILLEGAL

NOP (Continue Row Active after Burst ends)

L H H H

NOP (Continue Row Active after Burst ends)

L H H L

1,2,4,8 Burst Length : ILLEGAL
Full Page Burst : Burst Stop

Row Active

CA, A9 Term Burst, start Read

CA, A9 Term Burst, new Write

L L H H BA RA ILLEGAL

Term Burst, execute Precharge

Write (WT)

L L L

ILLEGAL

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Function Truth Table (2/2)

Note 1

Current State

CS RAS CAS WE

BA Address

Action

Note

NOP (Continue Burst to End and enter Row Precharge)

L H H H

NOP (Continue Burst to End and enter Row Precharge)

L H H L

ILLEGAL

L H L H BA

CA,

ILLEGAL

L H L L BA

CA,

ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A9 ILLEGAL

Read with Auto
Precharge
(RAP)

L L L

ILLEGAL

NOP (Continue Burst to End and enter Row Precharge)

L H H H

NOP (Continue Burst to End and enter Row Precharge)

L H H L

ILLEGAL

L H L H BA

CA,

ILLEGAL

L H L L BA

CA,

ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A9 ILLEGAL

Write with Auto
Precharge
(WAP)

L L L

ILLEGAL

NOP

Idle after t

L H H H

NOP

Idle after t

L H H L BA

ILLEGAL 2

L H L

BA CA,

A9 ILLEGAL

L L H H BA A9 ILLEGAL

Precharging
(PRE)

L L H L BA

NOP 4

NOP

Idle after t

L H H H

NOP

Idle after t

L H H L

ILLEGAL

L H L

BA CA,

A9 ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A9 ILLEGAL

Refreshing
(REF)

L L L

ILLEGAL

ABBREVIATIONS
BA = Bank Address

RA = Row Address

CA = Column Address

NOP = No Operation command

Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.

2. Illegal to bank in specified state, but may be legal in some cases depending on the state of

bank selection.

3. To avoid bus contention, satisfy t

CCD

and t

DPL

4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A9.

5. Illegal if any bank is not idle.

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Function Truth Table for CKE

Current State (n) CKEn-1 CKEn

CS RAS CAS WE

Address Action Note

INVALID

L H

Exit Self Refresh

ABI

L H L H H H

Exit Self Refresh

ABI

L H

ILLEGAL

L H

ILLEGAL

L H

ILLEGAL

Self Refresh
(SREF)

L L

NOP (Maintain Self Refresh)

INVALID

L H

Exit Self Refresh

ABI

L H L H H H

Exit Self Refresh

ABI

L H

ILLEGAL

L H

ILLEGAL

L H

ILLEGAL

Power Down
(PD)

L L

NOP (Continue power down mode)

H H

Refer to Truth Table

H L

Enter Power Down

H L L H H H

Enter Power Down

H L L

ILLEGAL 6

H L L

ILLEGAL 6

H L L

ILLEGAL 6

H L L L L H

Enter Self Refresh

H L L L L L

ILLEGAL 6

All Banks Idle
(ABI)

L L

NOP 6

H H

Refer to Truth Table

H L

Begin Clock Suspend Next Cycle

L H

Enable Clock of Next Cycle

Any State Other
than Listed Above

L L

Continue Clock Suspension

Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state.

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Mode Set Address Keys

Operation Code

CAS

Latency

Burst Type

Burst Length

A8 A7

A6 A5 A4

A2 A1 A0

0 0 Mode

Setting 0 0 0 Reserved 0 Sequential 0 0 0

Reserved

0 1

0 0 1 Reserved 1 Interleave 0 0 1

Reserved

1 0

0 1 0

1 1

Vender

Use

Only

0 1 1

Write

Burst

Length 1 0 0 Reserved

1 0 0 Reserved Reserved

Length

1 0 1 Reserved

1 0 1 Reserved Reserved

Burst

1 1 0 Reserved

1 1 0 Reserved Reserved

1 Single

Bit 1

Reserved

1 1 1 Full

Page Reserved

POWER ON SEQUENCE

1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and

start the system clock.

2. After the V

voltage has reached the specified level, pause for 200

s or more with the input

kept in NOP state.

3. Issue the precharge all bank command.

4. Apply an Auto-refresh 2 or more times.

5. Enter the mode register command.

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Burst Length and Sequence

BL = 2

Starting Address

(column address A0, binary)

Sequential Type

Interleave Type

0, 1

Not supported

1, 0

Not supported

BL = 4

Starting Address

(column address A1, A0, binary)

Sequential Type

Interleave Type

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

BL = 8

Starting Address

(column address A2 to A0, binary)

Sequential Type

Interleave Type

000

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

BL = Full: Sequential only

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BURST TERMINATION

Burst Read Termination by Precharging in READ Cycle

Burst Write Termination by Precharging in WRITE Cycle

Note: The burst write operation is unfinished, the input data must be masked by means of DQM
for assurance of the CLK by t

DPL

CLK

CL = 2

0 1 2 3 4 5 6 7 8

PRE

CL = 3

PRE

Hi-Z

BL = 2, 4, 8, Full

ACT

CLK

CL = 2

0 1 2 3 4 5 6 7 8

PRE

CL = 3

PRE

Hi-Z

BL = 2, 4, 8, Full

ACT

DQM

DPL

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ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter Symbol

Rating

Unit

Voltage on Power Supply Pin Relative to GND

0.5 to 4.6

Voltage on Input Pin Relative to GND

, V

OUT

0.5 to V

+ 0.5

4.6

Short Circuit Output Current

50 mA

Power Dissipation

* 1 W

Operating Temperature

opr

0 to 70

°C

Storage Temperature

stg

55 to 150

°C

*: Ta = 25 °C

Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the

operational section of this specification. Exposure to Absolute Maximum Ratings conditions for
extended periods may affect device reliability.

Recommended Operating Conditions

(Ta = 0 to 70°C)

Parameter Symbol

Min.

Typ.

Max.

Unit

3.0 3.3 3.6 V

Power Supply Voltage

0 0 0 V

Input High Voltage

2.0 --

+ 0.3

Input Low Voltage

0.3 -- 0.8 V

Capacitance

= 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)

Parameter Symbol

Min.

Max.

Unit

Input Capacitance (A0 to A9, BA)

IN1

-- 5 pF

Input Capacitance
(CLK, CKE,

RAS

CAS

DQM0 to DQM3)

IN2

-- 5 pF

Output Capacitance
(DQ0 to DQ31)

OUT

-- 6 pF

*: This parameter is sampled and not 100% tested.

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DC Characteristics

Test Condition

MS82V16520A-7 MS82V16520A-8

Parameter Symbol

CKE Other

Min.

Max.

Min.

Max.

Unit Note

Output High Voltage

= 2.0 mA

2.4

Output Low Voltage

-- I

= 2.0 mA

0.4

Input Leakage Current

-- 10

Output Leakage Current

-- 10

Operating Current
(1 Bank)

CC1

CKE

= min.

No Burst

-- 190 -- 170 mA 1,

CC2P

CKE

= min.

Precharge Standby Current in
Power Down Mode

CC2PS

CKE

CLK

-- 2 -- 2 mA 2

CC2N

CKE

= min.

-- 40 -- 40 mA 2

Precharge Standby Current in
Non Power Down Mode

CC2NS

CKE

CLK

-- 20 -- 20 mA

CC3P

CKE

= min.

Active Standby Current in
Power Down Mode

CC3PS

CKE

CLK

-- 3 -- 3 mA 3

CC3N

CKE

= min.

-- 50 -- 50 mA 3

Active Standby Current in Non
Power Down Mode

CC3NS

CKE

CLK

-- 30 -- 30 mA 3

Operating Current
(Burst Mode)

CC4

CKE

= min.

240

200

1, 2

Refresh Current

CC5

CKE

min.

170

150

Self Refresh Current

CC6

CKE

0.2V

-- --

Notes 1. The maximum value of power supply current is obtained with the output open.

2. Address and data are changed only one time during one cycle.
3. Address and data are changed only one time during two cycles.

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AC Characteristics

Test conditions

· AC measurements assume t

= 1 ns.

· Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between V

and

· If t

is longer than 1 ns, reference level for measuring timing of input signals is V

IH (MIN.)

and V

IL (MAX)

· An access time is measured at 1.4 V.
· Input levels at the AC testing are 2.4 V/0.4 V.

Setup

Hold

CLK

Input

Output

2.4 V

1.4 V

0.4 V

2.4 V

1.4 V

0.4 V

1.4 V

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Synchronous Characteristics

MS82V16520A-7 MS82V16520A-8

Parameter Symbol

Min. Max. Min. Max.

Unit Note

CAS

Latency = 3

CK3

7 -- 8 --

Clock Cycle Time

CAS

Latency = 2

CK2

10 -- 12 -- ns

CAS

Latency = 3

AC3

-- 6 -- 6.5

Access Time from CLK

CAS

Latency = 2

AC2

-- 8 -- 9 ns

CLK High Level Width

2.5 -- 3 --

CLK Low Level Width

2.5 -- 3 --

Data-out Hold Time

2 -- 2 --

Data-out Low-impedance Time

0 -- 0 --

Data-out High-impedance Time

-- 5 -- 6 ns

Data-in Setup Time

2 -- 2.5 -- ns

Data-in Hold Time

1 -- 1 --

Address Setup Time

2 -- 2.5 -- ns

Address Hold Time

1 -- 1 --

CKE Setup Time

CKS

2 -- 2.5 -- ns

CKE Hold Time

CKH

1 -- 1 --

Command (

RAS

CAS

, DQM) Setup

Time

CMS

2 -- 2.5 -- ns

Command (

RAS

CAS

, DQM) Hold

Time

CMH

1 -- 1 --

Note 1. Output load.

Z = 50

1.4 V

Output

30 pF

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Asynchronous Characteristics

MS82V16520A-7 MS82V16520A-8

Parameter Symbol

Min. Max. Min. Max.

Unit Note

REF to REF/ACT Command Period

63 -- 72 -- ns

ACT to PRE Command Period

RAS

42 120k 48 120k ns

PRE to ACT Command Period

21 -- 24 -- ns

Delay Time ACT to READ/WRITE Command

RCD

21 -- 24 -- ns

ACT (A) to ACT (B) Command Period

RRD

14 -- 16 -- ns

READ/WRITE to READ/WRITE Command
Period

CCD

7 -- 8 -- ns

Data-in to PRE Command Period

DPL

14 -- 16 -- ns

Data Output to WRITE Command Input Time

OWD

14 -- 16 -- ns

Mode Register Set Cycle Time

RSC

14 -- 16 -- ns

Transition Time

1 30 1 30

Refresh Time

REF

-- 32 -- 32 ms

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PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

QFP100-P-1420-0.65-BK4

Mirror finish

Package material

Epoxy resin

Lead frame material

42 alloy

Pin treatment

Solder plating (

5µm)

Package weight (g)

1.54 TYP.

Rev. No./Last Revised

4/Nov. 28, 1996

(Unit: mm)

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REVISION HISTORY

Page

Document

No.

Date

Edition

Current

Edition

Description

PEDS82V16520A-01

Nov. 2001

Preliminary first edition

1 1

Changed the subtitle from "2262,144-Word

32-Bit

2-Bank SDRAM" to "262,144-Word

32-Bit

2-Bank SGRAM".

Changed the table in "PRODUCT FAMILY"

4 4

Changed Note 3 to Note 4 and added Note 3.

5 5

Added symbol "CKE" in headers "Auto
Refresh Command" and "Self Refresh
Entry/Exit Command".
Added Section "Write with Auto Precharge
Command (

CS,

CAS,

= "Low",

RAS

, A9 =

"High").

6 6

Added Sections "Read with Auto Precharge
Command (

CS,

CAS

= "Low",

RAS

, A9 =

"High") and "Burst Stop Command (

"Low",

RAS

CAS

= "High").

7 7

Added the contents of Functions "Read with
Auto Precharge" and "Write with Auto
Precharge".

8 8

Partially changed the contents of Column
"Address".

8 9

Current State "Precharging (PRE)" has been
moved to page 9 and changed partially.
Added Current States "Read with Auto Pre-
charge (RAP)" and "Write with Auto Pre-
charge (WAP)".

9 9

Partially changed the content of Column
"Address" in Current State "Refreshing
(REF)".

11 11

Partially changed the content of POWER ON
SEQUENCE 4.

15 15

Changed the heading from "Burst Read
Termination ---" to "Burst Write Termination
---" and partially changed the timing diagram.
Changed the content of Note.

16 16

Changed "BL = 2, 4, 8, Full" to "BL = Full" in
two diagrams.

Added Section "AUTO PRECHARGE".

PEDS82V16520A-02

Apr. 26, 2002

17 18

Added Sentences shown with "Caution" in the
Absolute Maximum Ratings section.
Added asterisks "*" in the symbol column in
the table of the Capacitance section and
added the sentence shown with asterisk "*".

FEDS82V16520A-01

OKI Semiconductor

MS82V16520A

39/40

Page

Document

No.

Date

Previou

Edition

Current

Edition

Description

Changed a family device name from MS82V
16520A-10 to MS82V16520A-7 shown in the
table and added related values.
Partially changed Max. values of MS82V
16520A-75 and MS82V16520A-8.

18 19

Partially changed Test Condition "Other" of
Symbols I

CC2N

, I

CC3P

, and I

CC3N

Added 1 in Column "Note" of Symbol I

CC4

Changed a family device name from MS82V
16520A-10 to MS82V16520A-7 shown in the
table and added related values.

20 21

Partially changed Max. and Min. values of
MS82V16520A-75 and MS82V16520A-8.
Changed a family device name from MS82V
16520A-10 to MS82V16520A-7 shown in the
table and added related values.

21 22

Change the Min. values of Symbol t

DPL

26 27

Changed timings of DQM and DQ between
CLK pulses 4 and 6.

PEDS82V16520A-02 Apr. 26, 2002

Added Section "Auto Prechaged (BL = 4, CL =
3)".

First

edition

1 1

Partially changed the table of "PRODUCT
FAMILY"
Partially changed the content of "Package" in
the FEATURES section.

FEDS82V16520A-01 Jun. 25, 2002

19,21,22 19,21,22

Partially changed the tables of "DC Charac-
teristics", "Synchronous Characteristics", and
"Asynchronous Characteristics".

FEDS82V16520A-01

OKI Semiconductor

MS82V16520A

40/40

NOTICE

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an

explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is

granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FEDS82V16520A-01

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FEDS82V16520A-01