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MSM7705-01/02/03
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Semiconductor
MSM7705-01/02/03
4ch Single Rail CODEC
GENERAL DESCRIPTION
The MSM7705-01/02/03 are four-channel CODEC CMOS ICs for voice signals ranging from 300
to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain four-channel A/D and D/A converters in a single chip and achieve a reduced footprint
and a reduced number of external components.
The MSM7705-01/02/03 are best suited for digital telephone terminals, digital PABXs, and push-
button phones.
FEATURES
Single power supply: +5 V
Power consumption
Operating mode:
70 mW Typ.
140 mW Max.
Power-saving mode:
14 mW Typ.
32 mW Max.
Power-down mode:
0.05 mW Typ.
0.3 mW Max.
Conforms to ITU-T Companding law
MSM7705-01:
m/A-law pin-selectable
MSM7705-02:
m-law
MSM7705-03:
A-law
Built-in PLL eliminates a master clock
The PCM interface can be switched between 4 channel serial/parallel
Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544 kHz
(During 4 channel serial mode, the 64, 96, 128, and 192 kHz clocks are
disabled)
Transmit gain adjustable for each channel
Built-in reference voltage supply
Analog output can directly drive a 600 W line transformer
Package:
44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name : MSM7705-01GS-2K)
(Product name : MSM7705-02GS-2K)
(Product name : MSM7705-03GS-2K)
E2U0042-28-81
This version: Aug. 1998
Previous version: Nov. 1996
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BLOCK DIAGRAM
AIN1
GSX1
AIN2
GSX2
AOUT1
AOUT2
SGC
XSYNC
DOUT1
DOUT2
BCLK
RSYNC
(ALAW)
DIN1
DIN2
PDN
V
DD
AG
DG
+
+
+
+
RC
LPF
8th
BPF
RC
LPF
8th
BPF
5th
LPF
S&H
5th
LPF
S&H
SG
GEN
VR
GEN
AD
CONV.
TCONT
AUTO
ZERO
DA
CONV.
PLL
RTIM
RCONT
PWD
Logic
AIN3
GSX3
AIN4
GSX4
+
+
RC
LPF
8th
BPF
RC
LPF
8th
BPF
AD
CONV.
AUTO
ZERO
AOUT3
AOUT4
+
+
5th
LPF
S&H
5th
LPF
S&H
DA
CONV.
DOUT3
DOUT4
CHPS
DIN3
DIN4
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PIN CONFIGURATION (TOP VIEW)
V
DD
, DG, and AG have two pins each. Each of these pairs are internally connected with
each other.
* The ALAW pin is only supported by MSM7705-01GS-2K.
1
2
3
4
5
6
7
8
9
10
11
23
24
25
26
27
28
29
30
31
32
33
NC
NC
NC
V
DD
V
DD
NC
NC
DIN4
DIN3
DIN2
DIN1
RSYNC
XSYNC
BCLK
NC
DG
DG
NC
DOUT4
DOUT3
DOUT2
DOUT1
CHPS
PDN
(ALAW)*
NC
NC
NC
NC
AIN1
GSX1
GSX2
AIN2
AIN3
GSX3
GSX4
AIN4
SGC
AG
AG
AOUT1
AOUT2
AOUT3
AOUT4
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC : No connect pin
(
(
(
44-Pin Plastic QFP
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PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, AIN3, AIN4, GSX1, GSX2, GSX3, GSX4
AIN1, AIN2, AIN3, and AIN4 are the transmit analog inputs for channels 1, 2, 3 and 4
respectively.
GSX1, GSX2, GSX3, and GSX4 are the transmit level adjustments for channels 1, 2, 3 and 4
respectively.
AIN1, AIN2, AIN3, and AIN4 are connected to the inverting inputs for the op-amps. GSX1, GSX2,
GSX3, and GSX4 are connected to the outputs for the op-amps. They are used to adjust levels as
shown below, and are connected to the outputs of the op-amps.
During power saving mode and power down mode, the GSX1, GSX2, GSX3, and GSX4 outputs
are at 0 V.
When these pins are not used, connect AIN1 to GSX1, AIN2 to GSX2, AIN3 to GSX3, and AIN4
to GSX4.
CHn
Analog Input
+
AINn
C1n
R1n
R2n
GSXn
CHn Gain
Gain = R2n/R1n 10
R1n: Variable
R2n > 20 kW
C1n > 1/(2 3.14 30 R1n) (F)
AOUT1, AOUT2, AOUT3, AOUT4
AOUT1, AOUT2, AOUT3, and AOUT4 are the receive filter outputs for channels 1, 2, 3, and 4
respectively.
When the digital signal of +3 dBm0 is input to DIN1, DIN2, DIN3, and DIN4, the output signal
has an amplitude of 3.4 V
PP
above and below the signal ground voltage (SG : 1/2 V
DD
). The
output can drive a load of 600 W or more.
During power saving or power down mode, these outputs are at the voltage level of SG with a
high impedance.
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DIN1, DIN2, DIN3
PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected.
D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals
synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are
output from AOUT1, AOUT2, and AOUT3 pins, respectively.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).
DIN4
PCM signal input for channel 4 when the parallel mode is selected.
D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous
with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4
pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input.
BCLK
Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4.
The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit
and receive circuits to the power saving state.
RSYNC
Receive synchronizing signal input.
Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3,
and DIN4 pins by the receive synchronizing signal.
All timing signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same clock source as
BCLK). The frequency should be 8 kHz
50 ppm to guarantee the AC characteristics which are
mainly the frequency characteristics of the receive section.
However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics
of the system used are strictly specified, but the electrical characteristics specified in the data
sheet are not guaranteed.
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