1/15
Semiconductor
MD51V65805
DESCRIPTION
The MD51V65805 is a 8,388,608-word
8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MD51V65805 achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MD51V65805 is available in a 32-pin plastic SOJ or 32-pin plastic TSOP.
FEATURES
8,388,608-word
8-bit configuration
Single 3.3 V power supply,
0.3 V tolerance
Input
: LVTTL compatible, low input capacitance
Output
: LVTTL compatible, 3-state
Refresh
:
RAS-only refresh
: 4096 cycles/64 ms
CAS before RAS refresh, hidden refresh
: 4096 cycles/64 ms
Fast page mode with EDO, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Package options:
32-pin 400 mil plastic SOJ
(SOJ32-P-400-1.27)
(Product : MD51V65805-xxJA)
32-pin 400 mil plastic TSOP
(TSOPII32-P-400-1.27-K) (Product : MD51V65805-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Semiconductor
MD51V65805
8,388,608-Word
8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
84 ns
504 mW
Family
Access Time (Max.)
Cycle Time
(Min.)
Standby (Max.)
Power Dissipation
MD51V65805-50
t
RAC
50 ns
t
AA
25 ns
t
CAC
13 ns
t
OEA
13 ns
MD51V65805-60
60 ns
104 ns
432 mW
30 ns
15 ns
15 ns
Operating (Max.)
1.8 mW
E2G0142-18-11
This version: Mar. 1998
2/15
Semiconductor
MD51V65805
PIN CONFIGURATION (TOP VIEW)
3
4
5
9
10
11
12
13
DQ2
DQ3
DQ4
RAS
A0
A1
A2
A3
30
29
28
24
23
22
21
20
DQ7
DQ6
DQ5
NC
A11R
A10
A9
A8
2
DQ1
31 DQ8
1
V
CC
32 V
SS
32-Pin Plastic SOJ
3
4
5
9
10
11
12
13
30
29
28
24
23
22
21
20
2
31
1
32
32-Pin Plastic TSOP
(K Type)
6
NC
27 V
SS
27
8
WE
25
OE
25
6
8
7
V
CC
26
CAS
26
7
14
A4
19 A7
14
19
DQ2
DQ3
DQ4
RAS
A0
A1
A2
A3
DQ1
V
CC
NC
WE
V
CC
A4
DQ7
DQ6
DQ5
NC
A11R
A10
A9
A8
DQ8
V
SS
V
SS
OE
CAS
A7
Pin Name
Function
A0 - A10, A11R
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 - DQ8
Data Input/Data Output
OE
Output Enable
WE
Write Enable
V
CC
Power Supply (3.3 V)
NC
No Connection
15
A5
18 A6
15
18
16
V
CC
17 V
SS
16
17
A5
V
CC
A6
V
SS
V
SS
Ground (0 V)
Note :
The same power supply voltage must be provided to every V
CC
pin, and the same GND
voltage level must be provided to every V
SS
pin.
3/15
Semiconductor
MD51V65805
BLOCK DIAGRAM
Timing
Generator
Refresh
Control Clock
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Row
Deco-
ders
Word
Drivers
Memory
Cells
Sense Amplifiers
Column Decoders
I/O
Controller
I/O
Selector
Output
Buffers
Input
Buffers
On Chip
V
BB
Generator
On Chip
IV
CC
Generator
V
CC
DQ1 - DQ8
CAS
WE
A0 - A10
11
11
8
8
8
8
8
8
12
11
OE
RAS
V
SS
1
A11R
4/15
Semiconductor
MD51V65805
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Recommended Operating Conditions
Capacitance
*: Ta = 25
C
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
T
Symbol
I
OS
P
D
*
T
opr
T
stg
0.5 to 4.6
50
1
0 to 70
55 to 150
Rating
mA
W
C
C
Parameter
V
Unit
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
Symbol
V
SS
V
IH
V
IL
3.3
0
--
--
Typ.
Parameter
3.0
0
2.0
0.3
Min.
3.6
0
V
CC
+ 0.3
0.8
Max.
(Ta = 0C to 70C)
V
Unit
V
V
V
Input Capacitance (A0 - A10, A11R)
Input Capacitance (
RAS, CAS, WE, OE)
Output Capacitance (DQ1 - DQ8)
C
IN1
Symbol
C
IN2
C
I/O
5
7
7
Max.
pF
Unit
pF
pF
Parameter
(V
CC
= 3.3 V 0.3 V, Ta = 25C, f = 1 MHz)
--
--
--
Typ.
5/15
Semiconductor
MD51V65805
DC Characteristics
Notes : 1. I
CC
Max. is specified as I
CC
for output open condition.
2. The address can be changed once or less while
RAS = V
IL
.
3. The address can be changed once or less while
CAS = V
IH
.
Parameter
Symbol
Condition
MD51V65805
-60
MD51V65805
-50
(V
CC
= 3.3 V 0.3 V, Ta = 0C to 70C)
I
OH
= 2.0 mA
Output High Voltage
I
OL
= 2.0 mA
Output Low Voltage
0 V
V
I
V
CC
+ 0.3 V;
All other pins not
Input Leakage Current
under test = 0 V
DQ disable
Output Leakage Current
0 V
V
O
V
CC
RAS, CAS cycling,
Average Power
t
RC
= Min.
Supply Current
(Operating)
RAS, CAS = V
IH
Power Supply
RAS, CAS
Current (Standby)
RAS cycling,
Average Power
CAS = V
IH
,
Supply Current
t
RC
= Min.
(
RAS-only Refresh)
RAS = V
IH
,
Power Supply
CAS = V
IL
,
Current (Standby)
DQ = enable
Average Power
CAS before RAS
Supply Current
(
CAS before RAS Refresh)
RAS = V
IL
,
Average Power
CAS cycling,
Supply Current
t
HPC
= Min.
(Fast Page Mode)
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC5
I
CC6
I
CC7
V
CC
0.2 V
Min.
2.4
0
10
10
--
--
--
--
--
--
--
Max.
V
CC
0.4
10
10
120
1
0.5
120
5
120
120
Min.
2.4
0
10
10
--
--
--
--
--
--
--
Max.
V
CC
0.4
10
10
140
1
0.5
140
5
140
140
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
Note
1, 2
1
1, 2
1
1, 2
1, 3
RAS cycling,
6/15
Semiconductor
MD51V65805
AC Characteristics (1/2)
Parameter
MD51V65805
-60
MD51V65805
-50
(V
CC
= 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Access Time from
RAS
Access Time from
CAS
Access Time from Column Address
Access Time from
CAS Precharge
CAS to Data Output Buffer Turn-off Delay Time
Transition Time
RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode with EDO)
RAS Hold Time
CAS Pulse Width
CAS Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address to
RAS Lead Time
Access Time from
OE
OE to Data Output Buffer Turn-off Delay Time
Refresh Period
RAS Hold Time referenced to OE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RAS Hold Time from CAS Precharge
Symbol
t
RC
t
RWC
t
HPC
t
HPRWC
t
RAC
t
CAC
t
AA
t
CPA
t
CEZ
t
T
t
RP
t
RAS
t
RASP
t
RSH
t
CAS
t
CSH
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
OEA
t
OEZ
t
REF
t
ROH
t
RHCP
Note
4, 5, 6
4, 5
4, 6
4
7, 8
5
6
4
7
3
Output Low Impedance Time from
CAS
ns
t
CLZ
4
CAS Precharge Time (Fast Page Mode with EDO)
ns
t
CP
ns
Data Output Hold After
CAS Low
WE to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
ns
ns
ns
t
DOH
t
WEZ
t
REZ
7, 8
7
OE Hold Time from CAS (DQ Disable)
ns
Min.
84
110
20
58
--
--
--
--
0
1
30
50
50
7
7
35
11
9
5
0
7
0
7
25
--
0
--
7
0
7
30
5
0
0
5
Max.
--
--
--
--
50
13
25
30
13
50
--
10,000
100,000
--
10,000
--
37
25
--
--
--
--
--
--
13
13
64
--
--
--
--
--
13
13
--
t
CHO
Min.
104
135
25
68
--
--
--
--
0
1
40
60
60
10
10
40
14
12
5
0
10
0
10
30
--
0
--
10
0
10
35
5
0
0
5
Max.
--
--
--
--
60
15
30
35
--
15
50
--
10,000
100,000
--
--
10,000
--
45
30
--
--
--
--
--
--
15
15
64
--
--
--
15
15
--
7/15
Semiconductor
MD51V65805
AC Characteristics (2/2)
MD51V65805
-60
MD51V65805
-50
Write Command Pulse Width
Write Command to
CAS Lead Time
Write Command to
RAS Lead Time
Data-in Set-up Time
CAS to WE Delay Time
RAS to WE Delay Time
Column Address to
WE Delay Time
RAS to CAS Hold Time (CAS before RAS)
CAS Active Delay Time from RAS Precharge
Data-in Hold Time
Write Command Hold Time
OE Command Hold Time
OE to Data-in Delay Time
(V
CC
= 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3
Write Command Set-up Time
t
WP
t
CWL
t
RWL
t
DS
t
CWD
t
RWD
t
AWD
t
CHR
t
RPC
t
DH
t
WCH
t
OEH
t
OED
t
WCS
Parameter
Symbol
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit Note
11
10
10
10
11
10
RAS to CAS Set-up Time (CAS before RAS) t
CSR
ns
WE to RAS Precharge Time (CAS before RAS) t
WRP
ns
WE Hold Time from RAS (CAS before RAS) t
WRH
ns
CAS Precharge WE Delay Time
t
CPWD
10
ns
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to
RAS
ns
ns
ns
t
RCS
t
RCH
t
RRH
9
9
OE Precharge Time
WE Pulse Width (DQ Disable)
t
OEP
t
WPE
ns
ns
OE Command Hold Time
t
OCH
Min.
10
10
10
0
34
79
49
10
5
10
10
10
15
0
5
10
10
54
0
0
0
10
10
10
Max.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
Min.
7
7
7
0
30
67
42
10
5
7
7
7
13
0
5
10
10
47
0
0
0
7
7
7
Max.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
8/15
Semiconductor
MD51V65805
Notes:
1. A start-up delay of 200
s is required after power-up, followed by a minimum of eight
initialization cycles (
RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 2 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V
OH
= 2.0 V and V
OL
= 0.8 V.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then the access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t
WCS
t
WCS
(Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
CWD
t
CWD
(Min.) , t
RWD
t
RWD
(Min.),
t
AWD
t
AWD
(Min.) and t
CPWD
t
CPWD
(Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the
CAS leading edge in an early write cycle, and
to the
WE leading edge in an OE control write cycle, or a read modify write cycle.
9/15
Semiconductor
MD51V65805
,
"H" or "L"
RAS
CAS
V
IH
V
IL
V
IH
V
IL
DQ
V
OH
V
OL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
,,
,
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
Row
Column
t
RCS
t
RRH
t
RCH
t
AA
t
ROH
t
OEA
t
CAC
t
RAC
t
OEZ
t
CEZ
Open
t
CLZ
Valid Data-out
t
REZ
"H" or "L"
RAS
CAS
V
IH
V
IL
V
IH
V
IL
DQ
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
,
,,,
t
RC
t
RAS
t
RP
t
CRP
t
RCD
t
CSH
t
RSH
t
CRP
t
CAS
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
Row
Column
t
WCS
t
WCH
t
DS
t
DH
Valid Data-in
t
WP
t
RAL
,,
Open
t
RWL
t
CWL
TIMING WAVEFORM
Read Cycle
Write Cycle (Early Write)
E2G0115-17-41S
10/15
Semiconductor
MD51V65805
Read Modify Write Cycle
,
"H" or "L"
RAS
CAS
V
IH
V
IL
V
IH
V
IL
DQ
V
I/OH
V
I/OL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
t
RWC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
CRP
t
RSH
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
Row
Column
t
CWD
t
CWL
t
RWD
t
RWL
t
WP
t
AA
t
AWD
t
OEA
t
OED
t
CAC
t
RAC
t
OEZ
t
DS
t
DH
t
CLZ
Valid
Data-out
Valid
Data-in
t
RAD
t
RCS
t
OEH
11/15
Semiconductor
MD51V65805
Fast Page Mode Read Cycle (Part-1)
Fast Page Mode Read Cycle (Part-2)
V
IH
RAS
Address
WE
DQ
CAS
OE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Row
Column
t
CRP
t
CRP
t
RP
t
RASP
t
CAS
t
CSH
"H" or "L"
Column
Column
t
RCD
t
CP
t
CAS
t
CAS
t
HPC
t
CP
t
CAH
t
ASC
t
RAD
t
RCS
t
RCH
t
RAC
t
AA
,
,
t
CAC
t
CLZ
t
WEZ
t
OEA
Valid
Data-out
Valid
Data-out
Valid
Data-out
t
RAH
t
ASR
t
CAH
t
ASC
t
CAH
t
ASC
t
CAC
t
AA
t
DOH
t
CEZ
t
CPA
t
AA
t
CAC
t
RCS
t
WPE
t
RHCP
V
IH
RAS
Address
WE
DQ
CAS
OE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
,
,
Row
Column
t
CRP
t
RP
t
RASP
t
CAS
t
CSH
"H" or "L"
,
Column
,
Column
t
RCD
t
CP
t
CAS
t
CAS
t
HPC
t
CAH
t
RAD
t
RCS
t
AA
t
RRH
t
CAC
t
CLZ
t
CPA
t
OEA
Valid
Data-out
Valid*
Data-out
t
RAH
t
ASR
t
CAH
t
ASC
t
CAH
t
ASC
t
RAC
Valid
Data-out
t
AA
t
CAC
t
DOH
Valid*
Data-out
t
CAC
t
REZ
t
OEZ
t
OEZ
t
CHO
t
OCH
t
AA
t
OEA
t
OEP
t
OEP
t
OEA
* : Same Data,
t
CP
t
RHCP
t
ASC
12/15
Semiconductor
MD51V65805
Fast Page Mode Write Cycle (Early Write)
Fast Page Mode Read Modify Write Cycle
V
IH
RAS
Address
WE
DQ
CAS
OE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
I/OH
V
I/OL
t
ASR
Row
Column
t
RASP
t
CWD
t
RAH
Column
t
RCD
t
CP
t
ASC
t
CAH
t
CPA
t
ASC
t
RAD
t
RWD
"H" or "L"
Valid
Data-out
t
OEZ
t
OED
t
DS
t
WP
t
AWD
t
RCS
t
CWD
t
RWL
t
CAC
,
t
AWD
t
RAC
t
WP
t
CLZ
t
DH
t
OEH
Valid
Data-in
t
OEA
Valid
Data-out
t
OEZ
t
OED
t
CAC
t
DH
t
OEH
Valid
Data-in
t
OEA
t
CLZ
,
t
DS
t
AA
t
AA
t
RCS
t
CAH
t
CPWD
t
HPRWC
t
CRP
t
CWL
V
IH
RAS
Address
WE
DQ
CAS
OE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
,
,
t
ASR
Row
Column
t
CRP
t
RP
t
RASP
t
CAS
t
CSH
t
RAH
,
Column
Column
t
RCD
t
CP
t
CAS
t
CAS
t
HPC
t
CP
t
HPC
t
ASC
t
CAH
t
CAH
t
CAH
t
ASC
t
ASC
t
RAD
,
"H" or "L"
t
DH
t
DS
t
WCH
Valid
Data-in
t
DS
t
DH
t
DS
t
DH
t
WCH
t
WCH
t
RSH
Valid
Data-in
Valid
Data-in
t
WCS
t
WCS
t
WCS
13/15
Semiconductor
MD51V65805
RAS-Only Refresh Cycle
CAS before RAS Refresh Cycle
RAS
CAS
V
IH
V
IL
V
IH
V
IL
Address
V
IH
V
IL
,
t
RC
t
RAS
t
RP
t
CRP
t
RPC
t
ASR
t
RAH
Row
DQ
V
OH
V
OL
Note:
WE, OE = "H" or "L"
t
CEZ
Open
"H" or "L"
-
9
B
C
D
E
?
V
IH
V
IL
RAS
t
RP
CAS
V
IH
V
IL
V
IH
V
IL
WE
V
V
"H" or "L"
t
RC
t
RAS
t
RPC
t
CHR
t
RP
t
RPC
t
CP
t
CSR
t
WRP
t
WRH
t
CEZ
t
WRP
Open
OL
OH
DQ
Note:
OE, Address = "H" or "L"
14/15
Semiconductor
MD51V65805
Hidden Refresh Read Cycle
Hidden Refresh Write Cycle
V
IH
RAS
Address
WE
DQ
CAS
OE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
,
,,
t
ASR
Row
Column
t
CRP
t
RC
t
ASC
t
RP
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
RAH
t
RAL
t
RWL
t
CHR
t
RAS
t
RC
t
RP
t
DS
t
WP
t
WCH
t
DH
Valid Data-in
t
WCS
RAS
CAS
Address
OE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
WE
V
IH
V
IL
DQ
V
OH
V
OL
,
,
,,
,,
,
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
CRP
t
RCD
t
RSH
t
CHR
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
Row
Column
t
RCS
t
RAL
t
RRH
t
AA
t
ROH
t
OEA
t
CAC
t
RAC
t
CLZ
t
OEZ
Valid Data-out
Open
t
CEZ
t
REZ
t
WRH
t
WRP
15/15
Semiconductor
MD51V65805
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
SOJ32-P-400-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5
mm or more
1.42 TYP.
Mirror finish
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