I
I
Oki Semiconductor
CONTENTS
Description ................................................................................................................................................................1
Features ..................................................................................................................................................................... 1
MG73Q/74Q and MSM98Q/99Q Family Masterslices...................................................................................... 2
Array Architecture................................................................................................................................................... 3
CSA Layout Methodology .............................................................................................................................. 4
Electrical Characteristics ......................................................................................................................................... 5
Macro Library ........................................................................................................................................................... 8
Macrocells for Driving Clock Trees............................................................................................................... 9
Oki Advanced Design Center CAD Tools.......................................................................................................... 10
Oki Design Kit Availability .......................................................................................................................... 10
Design Process................................................................................................................................................ 11
Automatic Test Pattern Generation............................................................................................................. 12
Floorplanning Design Flow.......................................................................................................................... 12
IEEE JTAG Boundary Scan Support............................................................................................................ 13
Package Options..................................................................................................................................................... 14
1
Oki Semiconductor
MG73Q/74Q and MSM98Q/99Q
0.35m Customer Structured Arrays
DESCRIPTION
Oki's 0.35m Application-Specific Integrated Circuit (ASIC) products are available in Customer Struc-
tured Array (CSA) architectures with 0.60-m or 100-m I/O pad pitch. Both the MG73Q000 and the
MSM98Q000 series use a three-layer metal process on 0.35m drawn (0.27m L-effective) CMOS technol-
ogy. The MG74Q and MSM99Q series uses the same base-array architecture as the MG73Q or MSM99Q
series respectively, but offers four metal layers instead of three. The semiconductor process is adapted
from Oki's production-proven 64-Mbit DRAM manufacturing process.
The 0.35-m family provides significant performance, density, and power improvement over previous
0.4 and 0.5m technologies. The Oki 0.35-m family operates using 3-V V
DD
core with optimized 3-V I/O
buffers and 3-V I/O buffers that are 5-V tolerant. The MG73Q/74Q series contains 21 array bases, offer-
ing up to 868 I/O pads and over 2 M raw gates. The MSM98Q/99Q series contains 18 array bases,
offering up to 432 I/O pads and over 1.4M raw gates. These CSA array sizes are designed to fit the most
popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array
(PBGA) packages.
The 3-layer-metal MG73Q and MSM98Q and 4-layer-metal MG74Q and MSM99Q CSA series offer a
wide span of gate and I/O counts. Oki uses the Artisan Components memory compiler which provides
high performance, embedded synchronous single- and dual-port RAM macrocells for CSA designs. As
such, the MG73Q/74Q and MSM98Q/99Q series is suited to memory-intensive ASICs and high-volume
designs where fine tuning of package size produces significant cost or real-estate savings.
FEATURES
0.35m drawn 3-, and 4-layer metal CMOS
Optimized 3.3-V core
Optimized 3-V I/O and 3-V I/O that is 5-V
tolerant
0.60-m and 100-m I/O pitch
CSA architecture
77-ps typical gate propagation delay (for a 4x-
drive inverter gate with a fan-out of 2 and 0 mm
of wire, operating at 3.3 V)
Up to 2.0 M raw gates and 868 I/O pads
User-configurable I/O with V
SS
, V
DD
, TTL,
3-state, and 1- to 24-mA options
Slew-rate-controlled outputs for low-radiated
noise
Clock tree drivers which reduces the maximum
skew for clock signals
User-configurable single- and dual-port
memories
Specialized macrocells including phase-locked
loop (PLL), LVDS, pseudo-emitter coupled
logic (PECL), and peripheral component
interconnect (PCI) cells
Floorplanning for front-end simulation, back-
end layout controls, and link to synthesis
Joint Test Action Group (JTAG) boundary scan
and scan path Automatic Test Pattern
Generation (ATPG)
Support for popular CAE systems including
Cadence, Exemplar, Gambit, IKOS, Mentor
Graphics, Model Technology, Inc. (MTI), Zycad,
Synopsys, and VIEWLogic
I
MG73Q/74Q and MSM98Q/99Q
I
3
Oki Semiconductor
ARRAY ARCHITECTURE
The primary components of a 0.35m MG73Q/74Q and MSM98Q/99Q circuit include:
I/O base cells: 60-m staggered I/O pitch (MG73Q/74Q) or 100-m In-Line I/O pitch
(MSM98Q/99Q)
Configurable I/O pads for V
DD
, V
SS
, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)
V
DD
and V
SS
pads dedicated to wafer probing
Separate power bus for output buffers
Separate power bus for internal core logic and input buffers
Core base cells containing N-channel and P-channel pairs, arranged in column of gates
Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (V
DDC
and V
SSC
)
and output drive transistors (V
DDO
and V
SSO
).
Figure 7. MSM98Q000 Array Architecture
Core base cell
with 4 transistors
Separate power bus (V
DDO
, V
SSO
)
over I/O cell for output buffers(2nd
metal/3rd metal)
V
DD
, V
SS
pads (4) in each
corner for
wafer probing only
Configurable I/O pads
for V
DD
, V
SS
, or I/O
Separate power bus (V
DDC
, V
SSC
) for
internal core logic (2nd metal/3rd metal
I/O base cells
Up to 3- or 4-layer metal
interconnection in core
area
PDF 
ZIP
