OKI Semiconductor
FEDL2240DIGEST-02
Issue Date: July 12, 2004
ML2240
4-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
1/24
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or
representative.
GENERAL DESCRIPTION
The ML2240 is a 4-channel mixing speech synthesis device which connects an external ROM expanded up to
128-Mbit (maximum). This ML2240 allows to select the playback method from the 8-bit PCM, non-linear 8-bit
PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms. And the sound volume is adjustable as well.
The ML2240 incorporates a 14-bit D/A converter, and low-pass filter.
It is easy to configure a speech synthesizer by externally connecting a power amplifier and a CPU to the ML2240.
FEATURES
Non-linear 8-bit PCM, 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms
Serial input/parallel input selectable
Phrase control table function i.e., user definable phrase control table function
4 channels mixing function
Master clock frequency:
4.096 MHz
Sampling frequency:
4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz,
16.0 kHz, 21.3 kHz, 25.6 kHz, 32.0 kHz, 42.7 kHz, 48 kHz
Maximum number of phrases:
256 phrases
Sound volume adjustment function built in (4 sounds independently adjustable in 29 steps)
External voice data can be input
14-bit D/A converter built in
Built-in low-pass filter:
Digital filter
Package:
80-pin plastic TQFP (TQFP80-P-1212-0.50-K) (ML2240TB)
FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
2/24
BLOCK DIAGRAM
OPT
A
N
A
R
D
SERIAL
D7
/DI
D6
/SC
K
D5
/DO
D4/STASEL
D3
/STA3
D2
/STA2
D1
/STA1
D0
/STA0
W
R
C
S
RO
E
RC
S
XT
X
T
OSC
CPU
interface
2bit ADPCM
2
4bit ADPCM
2
Synthesizer
D
i
gital Filter
8bit PC
M
16bit PC
M
Synthesizer&2ch Mix
Timing C
ontroller
DV
DD
DGND
DAOR
RE
S
E
T
TEST
23bit Address
Controller
C
o
mmand
C
ontoroller
Volum
e
23bit Multiplexer
A22
A0
16bit Latch
RD1
4
RD0
BY
TE
R
D
15/A-1
AOUTR
DAOL
AOUTL
AV
DD
AGND
1
4
b
i
t
DAC
DASEL
DASD
DASCK
FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
3/24
PIN CONFIGURATION (TOP VIEW)
80-pin plastic TQFP
NC: No Connection
DV
DD
RA
1
3
RA
1
4
RA
1
5
XT
NC
X
T
RA
1
6
RA
1
7
RA
1
8
DGND
RA
1
9
RA
2
0
RA
2
1
RA
2
2
RE
S
E
T
W
R
R
D
C
S
OP
T
A
N
A
RD13
RD6
RD14
DGND
RD7
RD15/A-1
BYTE
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
RA12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
SERIAL
ROE
DGND
RCS
AV
DD
AOUTR
DAOR
NC
AOUTL
DAOL
AGND
D7/DI
D6/SCK
D5/DO
D4/STASEL
D3/STA3
D2/STA2
D1/STA1
D0/STA0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RD
5
RD
1
2
RD
4
RD
1
1
RD
3
RD
1
0
RD
2
RD
9
DV
DD
DV
DD
DV
DD
DGND
RD
1
RD
8
RD
0
TEST
DA
SEL
DA
SD
DA
SCK
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
4/24
PIN DESCRIPTIONS
80-pin Plastic TQFP
Pin Symbol
Type
Description
1-3, 5, 66-68,
73-80
RD14-RD0 I
Data pins to connect an external memory.
Data is input when the
ROE
pin is at "L" level. Input data from outside
is not accepted when the
ROE
pin is at "H" level. The RD14-RD8 pins
do not accept input data from outside when the
BYTE
pin is at "L"
level.
6 RD15/A-1
I/O
Data pin of the externally connected memory when
BYTE
pin is at "H"
level.
The data is input when the
ROE
pin output is at "L" level. When the
ROE
pin output is at "H" level, input data from outside is not accepted.
This pin becomes an address A-1 output pin when the device is in byte
mode. The address is output when the
RCS
pin is at "L" level. When
the
RCS
pin is at "H" level, this pin is in a high impedance state.
7
BYTE
I
Word/byte switching pin of the externally connected memory.
When
BYTE
pin = "L" level: Byte mode
When
BYTE
pin = "H" level: Word mode
8-20, 22-24,
28-30, 32-35
RA22-RA0 O
Address pins of an externally connected memory.
When
RCS
pin = "H": High impedance
25 XT
I
Wired to a crystal or ceramic oscillator.
Contains a feedback resistor of around 1 M
between this XT pin and
XT
pin (pin 27).
When using an external clock, input the clock from this pin.
27
XT
O
Wired to a crystal or ceramic oscillator.
When using an external clock, keep this pin open.
36
RESET
I
When "L" level is input to this pin, the device is reset to the initial state.
The oscillation stops, and AOUT output goes into "GND" level.
37
WR
I
CPU interface write signal.
When
CS
pin is at "H" level, the
WR
signal cannot be input to the
device.
38
RD
I
CPU interface read signal.
For parallel input interface, a status signal for each channel is output
from the D0-D7 pins when the
RD
pin is at "L" level. For the serial
input interface, a status signal for each channel is output from the
D5/D0 pin. This pin has a pull-up resistor built-in.
39
CS
I
CPU interface chip select pin.
When
CS
pin is at "H" level, the
WR
, and
RD
signals cannot be input to
the device.
41-44
D3/STA3
D2/STA2
D1/STA1
D0/STA0
I/O
CPU interface data bus pins in the parallel input interface become
data input pins when
WR
is at "L" level.
They become channel status output pins in the serial input interface.
These pins also become channel status output pins when
RD
is at "L"
level.
FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
5/24
Pin No.
Pin Symbol
I/O
Description
45 D4/STASEL
I/O
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when
WR
is at "L" level. It becomes
a channel status output pin when
RD
is at "L" level. It outputs a
BUSY
signal for channel 1. For the serial input interface, it becomes a
channel status changeover pin. When D4/STASEL is at "L" level, the
D3/STA3-D0/STA0 pins output the NCR (Next Command Request)
for each channel. When the D4/STASEL is at "H" level, the
D3/STA3-D0/STA0 pins output
BUSY
signals for their corresponding
channels.
46 D5/DO
I/O
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when
WR
is at "L" level. It becomes
a channel status output pin when
RD
is at "L" level. This pin outputs 2
channels of
BUSY
signal.
When
CS
and
RD
are at "L" level, this D5/DO pin serially outputs the
status of each channel in synchronization with D6/SCK clock.
47 D6/SCK
I/O
CPU interface data bus pin in the parallel input interface.
This pin becomes a data input pin when
WR
is at "L" level. It becomes
a channel status output pin when
RD
is at "L" level. It outputs a
BUSY
signal for channel 3.
This pin becomes a serial clock input pin for the serial input interface.
When the SCK pin input is at "L" level on the falling edge of the
CS
pin
signal, the DI pin input signal goes into the device on at the rising edge
of the SCK clock, and the data is output from the DO pin. When the
SCK pin input is at "H" level on the falling edge of the
CS
pin signal,
the DI pin input signal goes into the device on the falling edge of the
SCK clock, and the data is output from the DO pin.
48 D7/DI
I/O
CPU interface data bus pin in the parallel input interface.
When
WR
is at "L" level, it becomes a data input pin. When
RD
is at
"L" level, it becomes a channel status output pin. It outputs a
BUSY
signal for channel 4.
For the serial input interface, this pin becomes a serial data input pin.
Works as serial data input pin in the serial input interface.
50
DAOL
O
Outputs the left 14-bit DAC analog signal.
51
AOUTL
O
Outputs the left 14-bit DAC analog signal via voltage follower.
53
DAOR
O
Outputs the right 14-bit DAC analog signal.
54
AOUTR
O
Outputs the right 14-bit DAC analog signal via voltage follower.
56
RCS
I
"L" level: RA22-0, A-1, and
ROE
pins output the address data and the
output enable signal.
"H" level: RA22-0, A-1, and
ROE
pins are in high impedance.
58
ROE
O
Output enable pin for an externally connected memory.
RCS
pin = "H" level: High impedance
59 SERIAL
I
CPU interface switching pin.
"H" level: Serial input interface, "L" level: Parallel input interface
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