FEDL63193-04
1Semiconductor
This version: Sep. 2001
Previous version: Mar. 2000
ML63193
4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Driver and Melody Circuit.
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GENERAL DESCRIPTION
The ML63193 is CMOS 4
-
bit microcontroller with built-in 1024-dot matrix LCD drivers (64 SEG. 16 COM.),
and operates at 0.9 V (Min). The ML63193 is suitable for applications as games, toys, watches, remote controller,
etc. Which are provided with a LCD display.
The ML63193 is an M6318x series mask ROM-version product of OLMS-63K family, which employs Oki's
original CPU core nX-4/250.
FEATURES
Extensive instruction set
408 instructions:
Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations,
bit operations, ROM table reference, stack operations, flag operations, jump, conditional branch, call/return,
control
Wide variety of addressing modes
Indirect addressing mode for 4 types of data memory with current bank register, extra bank register,
HL register and XY register
Data memory bank internal direct addressing mode
Processing speed
2 clocks per machine cycle, with most instructions executed in 1 machine cycle
Minimum instruction execution time : 61
s (@ 32.768 kHz system clock)
: 1
s (@ 2 MHz system clock)
Clock generation circuit
Low-speed clock
: Crystal oscillation or RC oscillation selected with mask option
(30 kHz to 80 kHz)
High-speed clock
: Ceramic oscillation or RC oscillation selected with software
(2 MHz max)
Program memory space
64 K words
Basic instruction length is 16 bits/1word.
Data memory space
2048 nibbles
Stack level
Call stack level
: 16 levels
Register stack level
: 16 levels
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1Semiconductor
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I/O Ports
Input ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
I/O ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/
CMOS output.
Can be interfaced with external peripherals that use a different power supply than this device uses.V
DDI
is the
power supply pin for ports.
Number of ports:
Input port
: 1 port 4 bits
Input-output port
: 5 ports 4 bits
Melody output
Melody frequency
: 529 Hz to 2979 Hz
Tone length
: 63 varieties
Tempo
: 15 varieties
Melody data
: Stored in program memory
Buzzer driver signal output : 4 kHz
LCD driver
Number of segments
: 1024 Max. (64 SEG. 16 COM.)
Duty
: Selectable as 1/1 to 1/16 duty
Bias
: Selectable as 1/4 or 1/5 bias (regulator built-in)
Frame frequency
: ex. 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty), 256 Hz (at 1/4 duty),
512 Hz (at 1/2 duty), 1024 Hz (at 1/1 duty)
Contrast
: 16 levels adjustable
Display modes
: Selectable as all-ON mode/all-OFF mode/power down mode/
normal display mode
Multiplier/divider circuit
Multiplier
: (8 bits)
(8 bits)
Product (16 bits)
Divider
: (16 bits)
/
(8 bits)
Quotient (16 bits), Remainder (8 bits)
System reset function
System reset through RESET pin (selectable as built-in 2 kHz RESET-Sampling circuit by mask option)
System reset by power-on detection (When not using 2 kHz RESET-Sampling circuit)
System reset by low-speed oscillation halt
Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of BLDCON).
LD1
LD0
Judgment Voltage (V)
Remarks
0
0
1.05
0.10
Ta = 25
C
0
1
1.20
0.10
Ta = 25
C
1
0
1.80
0.10
Ta = 25
C
1
1
2.40
0.10
Ta = 25
C
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1Semiconductor
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Timers and Counter
8-bit timer
: 4
Selectable as auto-reload mode/capture mode/
clock frequency measurement mode
Watchdog timer
: 1
100 Hz timer
: 1
Measurable in steps of 1/100 sec.
15-bit time-base counter
: 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
Serial port
Mode
: Selectable as UART mode, synchronous mode
UART communication speed
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
Clock frequency in synchronous mode : Internal clock mode (32.768 kHz), External clock frequency
Data length
: 5 to 8 bits
Shift register
Shift clock
: 1
or 1/2
system clock, timer 1 overflow, external clock
Data length
: 8 bits
Interrupt factors
External interrupt
: 4
Internal interrupt
: 14 (watchdog timer interrupt is a nonmaskable interrupt)
Operating temperature
: 20 to +70
C
Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum.
Power supply voltage
When backup used
: 0.9 V to 2.7 V (Operating frequency: 30 k to 80 kHz)
1.2 V to 2.7 V (Operating frequency: 300 k to 500 kHz)
1.5 V to 2.7 V (Operating frequency: 200 k to 1 MHz)
When backup not used
: 1.8 V to 5.5 V (Operating frequency: 200 k to 2 MHz)
Package:
Chip (128 pads)
: (Product name: ML63193-xxxWA)
144-pin plastic LQFP (LQFP144-P-2020-0.50-K) : (Product name: ML63193-xxxTC)
xxx indicates a code number.
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1Semiconductor
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MASK OPTION
In the ML63193 uses the mask option to specify the following functions:
Low-Speeed clock oscillation circuit
Specify the crystal oscillation circuit or the RC oscillation circuit for the low-speed clock oscillation
circuit.
Reset signal sampling
Specify whether or not the reset signal will be sampled at 2 kHz.
When specifying "will carry out 2 kHz sampling," hold the RESET pin at a "H" level for 1 ms or more.
To use the mask option, assign mask option data in the application program in accordance with the formats below.
The mask option area is an application program execution disabled area.
Mask Option Data Assignment Format
Function
Mask option area
bit
data
Option to be selected
0
Crystal oscillation circuit
Low-speed clock oscillation circuit
(crystal oscillation circuit/RC oscillation circuit)
bit 0
1
RC oscillation circuit
0
Will carry out 2 kHz sampling
Reset signal sampling
(will/will not carry out 2 kHz sampling)
0FFE0H
bit 1
1
Will not carry out 2 kHz sampling
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1Semiconductor
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BLOCK DIAGRAM
Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( )
Indicate interface signals of the V
DDI
power supply system.
CPU core nX-4/250
TIMING
CON-
TROL
CBR
EBR
H
L
X
Y
RA
MIE
A
INSTRUCTION
DECODER
IR
BUS
CON-
TROL
ROM
64KW
SP
RSP
C
G
Z
STACK
CAL.S:16-level
REG.S:16-level
PC
ALU
RAM
2048N
INT193
TBC
RST
TST
XT0
XT1
OSC0
OSC1
OSC
RESET
TM0CAP/TM1CAP*
TIMER
8bit (4ch)
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
RXC*
TXC*
MELODY
MD
V
DDH
BACK
UP
V
DD
INT
4
RXD*
LCD
&
DSPR
COM1 - 16
INT
4
TST2
DATA BUS
SEG0 - 63
BLD
WDT
INT
1
TST1
CB1
CB2
MDB
100HzTC
INT
1
V
DD1
BIAS
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDL
V
DDI
V
SS
INPUT
PORT
INT
1
P0.0 - P0.3
I/O
PORT
P9.0 - P9.3
PA.0 - PA.3
PB.0 - PB.3
PC.0 - PC.3
INT
3
INT
1
INT
2
MULDIV
TXD*
SFT
SCLK*
SIN*
SOUT*
INT
1
PE.0 - PE.3
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1Semiconductor
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PIN CONFIGURATION (TOP VIEW)
144-Pin Plastic LQFP
(TC: LQFP144-P-2020-0.50-K)
Note: Pins marked as (NC) are no-connection pins which are left open.
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
102 101 100
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
37
38
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
65
66
67
68
69
70
71
72
105 104 103
108 107 106
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
PC.3
PC.2
PC.1
PC.0
PE.3
PE.2
PE.1
PE.0
V
DDI
MDB
MD
TST2
TST1
XT0
XT1
RESET
OSC0
OSC1
V
DDL
V
DD
CB2
CB1
V
DDH
C2
C1
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
V
SS
(NC)
SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47
SEG48
SEG49
SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG39
SEG38
PB.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P0.0
P0.1
P0.2
P0.3
V
SS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
PB.2 PB.1 PB.0
(NC)
SEG40
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC) (NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
FEDL63193-04
1Semiconductor
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PAD CONFIGURATION
Pad Layout
Chip size
: 5.72 mm
5.72 mm
Chip thickness
: 350
m (280
m: available as required)
Coordinate origin
: center of chip
Pad hole size
: 100
m
100
m
Pad size
: 110
m
110
m
Minimum pad pitch : 140
m
Note: The chip substrate voltage is V
SS
.
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PB.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P0.0
P0.1
P0.2
P0.3
V
SS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PB.2 98
PB.1 97
PB.0 96
ML63193
95
PC.3 PC.2
94
PC.1
93 92
PC.0
91
PE.
3
90
PE.
2
89
PE.
1
88
PE.
0
87
V
DDI
86
MDB
85
MD
8
4
TS
T2
8
3
TS
T1
82
X
T0
81
X
T1
80
RES
E
T
79
O
S
C0
78
O
S
C1
77
V
DDL
76
V
DD
75
CB2
74
CB1
73
V
DDH
72
C2
71
C1
70
V
DD5
69
V
DD4
68
V
DD3
67
V
DD2
66
V
DD1
65
V
SS
SEG
8
1
SEG
9
2
SEG
1
0
3
SEG
1
1
4
SEG
1
2
5
SEG
1
3
6
SEG
1
4
7
SEG
1
5
8
SEG
1
6
9
SEG
1
7
10
SEG
1
8
1
1
SEG
1
9
12
SEG
2
0
13
SEG
2
1
14
SEG
2
2
15
SEG
2
3
16
SEG
2
4
17
SEG
2
5
18
SEG
2
6
19
SEG
2
7
20
SEG
2
8
21
SEG
2
9
22
SEG
3
0
23
SEG
3
1
24
SEG
3
2
25
SEG
3
3
26
SEG
3
4
27
SEG
3
5
28
SEG
3
6
29
SEG
3
7
30
SEG
3
8
31
SEG
3
9
32
Y
X
(0,0)
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1Semiconductor
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Pad Coordinates
Center of chip: X = 0, Y = 0
Pad No.
Pad
Name
X (
m)
Y (
m)
Pad No.
Pad
Name
X (
m)
Y (
m)
1
SEG8
2204
2714
44
SEG51
2714
604
2
SEG9
2063
2714
45
SEG52
2714
464
3
SEG10
1923
2714
46
SEG53
2714
323
4
SEG11
1783
2714
47
SEG54
2714
183
5
SEG12
1642
2714
48
SEG55
2714
43
6
SEG13
1502
2714
49
SEG56
2714
98
7
SEG14
1361
2714
50
SEG57
2714
238
8
SEG15
1221
2714
51
SEG58
2714
379
9
SEG16
1081
2714
52
SEG59
2714
519
10
SEG17
940
2714
53
SEG60
2714
659
11
SEG18
800
2714
54
SEG61
2714
800
12
SEG19
659
2714
55
SEG62
2714
940
13
SEG20
519
2714
56
SEG63
2714
1081
14
SEG21
379
2714
57
COM9
2714
1221
15
SEG22
238
2714
58
COM10
2714
1361
16
SEG23
98
2714
59
COM11
2714
1502
17
SEG24
43
2714
60
COM12
2714
1642
18
SEG25
183
2714
61
COM13
2714
1783
19
SEG26
323
2714
62
COM14
2714
1923
20
SEG27
464
2714
63
COM15
2714
2063
21
SEG28
604
2714
64
COM16
2714
2204
22
SEG29
745
2714
65
V
SS
2152
2714
23
SEG30
885
2714
66
V
DD1
2011
2714
24
SEG31
1025
2714
67
V
DD2
1871
2714
25
SEG32
1166
2714
68
V
DD3
1730
2714
26
SEG33
1306
2714
69
V
DD4
1590
2714
27
SEG34
1447
2714
70
V
DD5
1450
2714
28
SEG35
1587
2714
71
C1
1309
2714
29
SEG36
1727
2714
72
C2
1169
2714
30
SEG37
1868
2714
73
V
DDH
1028
2714
31
SEG38
2008
2714
74
CB1
888
2714
32
SEG39
2149
2714
75
CB2
748
2714
33
SEG40
2714
2149
76
V
DD
607
2714
34
SEG41
2714
2008
77
V
DDL
467
2714
35
SEG42
2714
1868
78
OSC1
326
2714
36
SEG43
2714
1727
79
OSC0
186
2714
37
SEG44
2714
1587
80
RESET
46
2714
38
SEG45
2714
1447
81
XT1
95
2714
39
SEG46
2714
1306
82
XT0
235
2714
40
SEG47
2714
1166
83
TST1
376
2714
41
SEG48
2714
1025
84
TST2
516
2714
42
SEG49
2714
885
85
MD
656
2714
43
SEG50
2714
745
86
MDB
797
2714
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1Semiconductor
ML63193
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Center of chip: X = 0, Y = 0
Pad No.
Pad
Name
X (
m)
Y (
m)
Pad No.
Pad
Name
X (
m)
Y (
m)
87
V
DDI
937
2714
108
P0.0
2714
562
88
PE.0
1078
2714
109
P0.1
2714
421
89
PE.1
1218
2714
110
P0.2
2714
281
90
PE.2
1358
2714
111
P0.3
2714
140
91
PE.3
1499
2714
112
V
SS
2714
0
92
PC.0
1639
2714
113
COM1
2714
140
93
PC.1
1780
2714
114
COM2
2714
281
94
PC.2
1920
2714
115
COM3
2714
421
95
PC.3
2060
2714
116
COM4
2714
562
96
PB.0
2714
2246
117
COM5
2714
702
97
PB.1
2714
2106
118
COM6
2714
842
98
PB.2
2714
1966
119
COM7
2714
983
99
PB.3
2714
1825
120
COM8
2714
1123
100
PA.0
2714
1685
121
SEG0
2714
1264
101
PA.1
2714
1544
122
SEG1
2714
1404
102
PA.2
2714
1404
123
SEG2
2714
1544
103
PA.3
2714
1264
124
SEG3
2714
1685
104
P9.0
2714
1123
125
SEG4
2714
1825
105
P9.1
2714
983
126
SEG5
2714
1966
106
P9.2
2714
842
127
SEG6
2714
2106
107
P9.3
2714
702
128
SEG7
2714
2246
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1Semiconductor
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PIN DESCRIPTIONS
The basic functions of each pin of the ML63193 are described in Table 1.
A symbol with a slash "/" denotes a pin that has a secondary function. Refer to Table 2 for secondary functions.
For type, "--" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an input-output pin.
Table 1 Pin Descriptions (Basic Functions)
Function
Symbol
Pin No.
Pad No.
Type
Description
V
DD
50
76
--
Positive power supply pin
V
SS
39,91
65,112
--
Negative power supply pin
V
DD1
40
66
V
DD2
41
67
V
DD3
42
68
V
DD4
43
69
V
DD5
44
70
--
Power supply pins for LCD bias (internally
generated):
Capacitors (0.1
F) should be connected between
these pins and V
SS
.
C1
45
71
C2
46
72
--
Capacitor connection pins for LCD bias generation:
A capacitor (0.1
F) should be connected between
C1 and C2.
V
DDI
61
87
--
Positive power supply pin for external interface
(Power supply for input, and input-output
ports)
V
DDL
51
77
--
Positive power supply pin for internal logic
(internally generated):
A capacitor (0.1
F) should be connected between
this pin and V
SS
.
V
DDH
47
73
--
Voltage multiplier pin for power supply backup
(internally generated):
A capacitor (1.0
F) should be connected between
this pin and V
SS
.
CB1
48
74
Power
Supply
CB2
49
75
--
Pins to connect a capacitor for voltage multiplier.
A capacitor (1.0
F) should be connected between
CB1 and CB2.
XT0
56
82
I
XT1
55
81
O
Low-speed clock oscillation pins:
An option for using crystal oscillation or RC
oscillation is chosen by the mask option.
If the crystal oscillation is chosen, a crystal should
be connected between XT0 and XT1, and capacitor
(C
G
) should be connected between XT0 and V
SS
.
If the RC oscillation is chosen, external oscillation
resistor (R
OSL
) should be connected between XT0
and XT1.
OSC0
53
79
I
Oscillation
OSC1
52
78
O
High-speed clock oscillation pins:
A ceramic resonator and capacitors (C
L0
, C
L1
) or
external oscillation resistor (R
OSH
) should be
connected to these pins.
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1Semiconductor
ML63193
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
TST1
57
83
I
Test
TST2
58
84
I
Input pins for testing.
A pull-down resistor is internally connected to these pins.
The user cannot use these pins.
Reset
RESET
54
80
I
System reset input pin.
Setting this pin to "H" level puts this device into a
reset state. Then, setting this pin to " L" level starts
executing an instruction from address 0000H.
An option for using RESET sampling circuit or not using is
chosen by the mask option.
When using RESET sampling circuit, the system reset
mode is entered by holding the RESET pin at a " H" level
for 1ms or more.
A pull-down resistor is internally connected to this pin.
MD
59
85
O
Melody output pin (non-inverted output)
Melody
MDB
60
86
O
Melody output pin (inverted output)
FEDL63193-04
1Semiconductor
ML63193
12/37
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
P0.0/INT5
87
108
P0.1/INT5
88
109
P0.2/INT5
89
110
P0.3/INT5
90
111
I
4-bit input port:
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
P9.0
83
104
P9.1
84
105
P9.2
85
106
P9.3
86
107
I/O
PA.0
79
100
PA.1
80
101
PA.2
81
102
PA.3
82
103
I/O
PB.0/INT0/
TM0CAP/
TM0OVF
75
96
PB.1/INT0/
TM1CAP/
TM1OVF
76
97
PB.2/INT0/
T02CK
77
98
PB.3/INT0/
T13CK
78
99
I/O
PC.0/INT1/
RXD
66
92
PC.1/INT1/
TXC
67
93
PC.2/INT1/
RXC
68
94
PC.3/INT1/
TXD
69
95
I/O
PE.0/SIN
62
88
PE.1/SOUT
63
89
PE.2/SCLK
64
90
Port
PE.3/INT2
65
91
I/O
4-bit input output ports:
In input mode, pull-up resister input, pull-down
resister input, or high-impedance input is selectable
for each bit.
In output mode, P-channel open drain output, N-
channel open drain output, CMOS output, or high-
impedance
output is selectable for each bit.
FEDL63193-04
1Semiconductor
ML63193
13/37
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
COM1
92
113
COM2
93
114
COM3
94
115
COM4
95
116
COM5
96
117
COM6
97
118
COM7
98
119
COM8
99
120
COM9
27
57
COM10
28
58
COM11
29
59
COM12
30
60
COM13
31
61
COM14
32
62
COM15
33
63
COM16
34
64
O
LCD common signal output pins
SEG0
100
121
SEG1
101
122
SEG2
102
123
SEG3
103
124
SEG4
104
125
SEG5
105
126
SEG6
106
127
SEG7
107
128
SEG8
111
1
SEG9
112
2
SEG10
113
3
SEG11
114
4
SEG12
115
5
SEG13
116
6
SEG14
117
7
SEG15
118
8
LCD
SEG16
119
9
O
LCD segment signal output pins
FEDL63193-04
1Semiconductor
ML63193
14/37
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
SEG17
120
10
SEG18
121
11
SEG19
122
12
SEG20
123
13
SEG21
124
14
SEG22
125
15
SEG23
126
16
SEG24
127
17
SEG25
128
18
SEG26
129
19
SEG27
130
20
SEG28
131
21
SEG29
132
22
SEG30
133
23
SEG31
134
24
SEG32
135
25
SEG33
136
26
SEG34
137
27
SEG35
138
28
SEG36
139
29
SEG37
140
30
SEG38
141
31
SEG39
142
32
SEG40
3
33
SEG41
4
34
SEG42
5
35
SEG43
6
36
SEG44
7
37
SEG45
8
38
SEG46
9
39
SEG47
10
40
SEG48
11
41
LCD
SEG49
12
42
O
LCD segment signal output pins
FEDL63193-04
1Semiconductor
ML63193
15/37
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
SEG50
13
43
SEG51
14
44
SEG52
15
45
SEG53
16
46
SEG54
17
47
SEG55
18
48
SEG56
19
49
SEG57
20
50
SEG58
21
51
SEG59
22
52
SEG60
23
53
SEG61
24
54
SEG62
25
55
LCD
SEG63
26
56
O
LCD segment signal output pins
FEDL63193-04
1Semiconductor
ML63193
16/37
Table 2 shows the secondary functions of each pin of the ML63193.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin No.
Pad No.
Type
Description
PB.0/INT0
75
96
PB.1/INT0
76
97
PB.2/INT0
77
98
PB.3/INT0
78
99
I
External 0 interrupt input pins
The change of input signal level causes an interrupt
to occur.
The Port B Interrupt Enable register (PBIE) enables
or disables an interrupt for each bit.
PC.0/INT1
66
92
PC.1/INT1
67
93
PC.2/INT1
68
94
PC.3/INT1
69
95
I
External 1 interrupt input pins
The change of input signal level causes an interrupt
to occur.
The Port C Interrupt Enable register (PCIE) enables
or disables an interrupt for each bit.
PE.3/INT2
65
91
I
External 2 interrupt input pin
The change of input signal level causes an interrupt
to occur.
P0.0/INT5
87
108
P0.1/INT5
88
109
P0.2/INT5
89
110
External
Interrupt
P0.3/INT5
90
111
I
External 5 interrupt input pins
The change of input signal level causes an interrupt
to occur.
The Port 0 Interrupt Enable register (P0IE) enables
or disables an interrupt for each bit.
PB.0/
TM0CAP
75
96
I
Timer 0 capture input pin
Capture
PB.1/
TM1CAP
76
97
I
Timer 1 capture input pin
PB.0/
TM0OVF
75
96
O
Timer 0 overflow flag output pin
PB.1/
TM1OVF
76
97
O
Timer 1 overflow flag output pin
PB.2/T02CK
77
98
I
External clock input pin for timer 0 and timer 2.
Timer
PB.3/T13CK
78
99
I
External clock input pin for timer 1 and timer 3
FEDL63193-04
1Semiconductor
ML63193
17/37
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
Description
PC.0/RXD
66
92
I
Serial port receive data input pin
PC.1/TXC
67
93
I/O
Sync serial port clock input-output pin
Transmit clock output when this device is used as a
master processor.
Transmit clock input when this device is used as a
slave processor.
PC.2/RXC
68
94
I/O
Sync serial port clock input-output pin
Receive clock output when this device is used as a
master processor.
Receive clock input when this device is used as a
slave processor.
Serial Port
PC.3/TXD
69
95
O
Serial port transmit data output pin
PE.0/SIN
62
88
I
Shift register receive data input pin
PE.1/SOUT
63
89
O
Shift register transmit data output pin
Shift
Register
PE.2/SCLK
64
90
I/O
Shift register clock input-output pin.
Clock output when this device is used as a master
processor.
Clock input when this device is used as a slave
processor.
FEDL63193-04
1Semiconductor
ML63193
18/37
ABSOLUTE MAXIMUM RATINGS
(V
SS
= 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
V
DD1
Ta = 25C
0.3 to +1.6
V
Power supply voltage 2
V
DD2
Ta = 25C
0.3 to +2.9
V
Power supply voltage 3
V
DD3
Ta = 25
C
0.3 to +4.2
V
Power supply voltage 4
V
DD4
Ta = 25
C
0.3 to +5.5
V
Power supply voltage 5
V
DD5
Ta = 25
C
0.3 to +6.8
V
Power supply voltage 6
V
DD
Ta = 25
C
0.3 to +6.0
V
Power supply voltage 7
V
DDI
Ta = 25
C
0.3 to +6.0
V
Power supply voltage 8
V
DDH
Ta = 25
C
0.3 to +6.0
V
Input voltage 1
V
IN1
V
DD
input, Ta = 25
C
0.3 to V
DD
+ 0.3
V
Input voltage 2
V
IN2
V
DDI
input, Ta = 25
C
0.3 to V
DDI
+ 0.3
V
Output voltage 1
V
OUT1
V
DD1
output, Ta = 25
C
0.3 to V
DD1
+ 0.3
V
Output voltage 2
V
OUT2
V
DD2
output, Ta = 25
C
0.3 to V
DD2
+ 0.3
V
Output voltage 3
V
OUT3
V
DD3
output, Ta = 25
C
0.3 to V
DD3
+ 0.3
V
Output voltage 4
V
OUT4
V
DD4
output, Ta = 25
C
0.3 to V
DD4
+ 0.3
V
Output voltage 5
V
OUT5
V
DD5
output, Ta = 25
C
0.3 to V
DD5
+ 0.3
V
Output voltage 6
V
OUT6
V
DD
output, Ta = 25
C
0.3 to V
DD
+ 0.3
V
Output voltage 7
V
OUT7
V
DDI
output, Ta = 25
C
0.3 to V
DDI
+ 0.3
V
Output voltage 8
V
OUT8
V
DDH
output, Ta = 25
C
0.3 to V
DDH
+ 0.3
V
Storage temperature
T
STG
--
55 to +150
C
FEDL63193-04
1Semiconductor
ML63193
19/37
RECOMMENDED OPERATING CONDITIONS
When backup is used
(V
SS
= 0 V)
Parameter
Symbol
Condition
Rating
Unit
Operating Temperature
T
op
--
20 to +70
C
V
DD
--
0.9 to 2.7
V
Operating Voltage
V
DDI
--
0.9 to 5.5
V
Crystal Oscillation
Frequency
f
XT
C
G
= 5 to 25 pF
32.768 to 76.8
kHz
R
OSL
= 1.0 M
36
30%
R
OSL
= 1.1 M
33
30%
Low-speed RC Oscillation
Frequency
f
ROSL
R
OSL
= 1.2 M
30
30%
kHz
V
DD
= 0.9 to 1.2 V
Not applied
V
DD
= 1.2 to 2.7 V
300 k to 500 k
Ceramic Oscillation
Frequency
f
CM
V
DD
= 1.5 to 2.7 V
200 k to 1 M
Hz
V
DD
= 0.9 to 1.2 V
Not applied
R
OSH
= 400 k
200 k
30%
R
OSH
= 100 k
700 k
30%
High-speed RC Oscillation
Frequency
f
ROSH
V
DD
= 1.2 to 2.7 V
R
OSH
= 75 k
1 M
30%
Hz
When backup is not used
(V
SS
= 0 V)
Parameter
Symbol
Condition
Rating
Unit
Operating Temperature
T
op
--
20 to +70
C
V
DD
--
1.8 to 5.5
V
Operating Voltage
V
DDI
--
1.8 to 5.5
V
Crystal Oscillation
Frequency
f
XT
C
G
= 5 to 25 pF
32.768 to 76.8
kHz
R
OSL
= 1.0 M
36
30%
R
OSL
= 1.1 M
33
30%
Low-speed RC Oscillation
Frequency
f
ROSL
R
OSL
= 1.2 M
30
30%
kHz
Ceramic Oscillation
Frequency
f
CM
V
DD
= 1.8 to 5.5 V
200 k to 2 M
Hz
R
OSH
= 100 k
700 k
30%
R
OSH
= 75 k
1 M
30%
V
DD
= 1.8 to 3.6 V
R
OSH
= 51 k
1.35 M
30%
High-speed RC Oscillation
Frequency
f
ROSH
V
DD
= 1.8 to 3.5 V, R
OSH
= 30 k
2 M
30%
Hz
FEDL63193-04
1Semiconductor
ML63193
20/37
Typical characteristics of low-speed RC oscillation
When backup is used/backup is not used (V
DD
= V
DDI
= 1.5 V/V
DD
= V
DDI
= 3.0 V)
Typical characteristics of high-speed RC oscillation
When backup is used (V
DD
= V
DDI
= 1.5 V)
1000
100
10
100
1000
10000
f
RO
S
L
[
kH
z
]
R
OSL
[k
]
Reference data
10000
1000
100
10
100
1000
f
RO
S
H
[
kH
z
]
R
OSH
[k
]
Reference data
FEDL63193-04
1Semiconductor
ML63193
21/37
Typical characteristics of high-speed RC oscillation
When backup is not used (V
DD
= V
DDI
= 3.0 V)
10000
1000
100
10
100
1000
f
RO
S
H
[
kH
z
]
R
OSH
[k
]
Reference data
FEDL63193-04
1Semiconductor
ML63193
22/37
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(V
DD
= V
DDI
= 0.9 to 5.5 V, V
SS
= 0 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
V
DD2
Voltage
V
DD2
1/5 bias, 1/4 bias
(Ta = 25
C)
1.7
1.8
1.9
V
V
DD2
Voltage
Temperature
Deviation
V
DD2
--
--
4.0
--
mV/
C
V
DD1
Voltage
V
DD1
1/5 bias, 1/4 bias
Typ.0.1
1/2
V
DD2
Typ.+0.1
1/5 bias
Typ.0.3
2/3
V
DD2
Typ.+0.3
V
DD3
Voltage
V
DD3
1/4 bias
(connect V
DD3
and V
DD2
)
Typ.0.2
V
DD2
Typ.+0.2
1/5 bias
Typ.0.4
2
V
DD2
Typ.+0.4
V
DD4
Voltage
V
DD4
1/4 bias
Typ.0.3
3/2
V
DD2
Typ.+0.3
1/5 bias
Typ.0.5
5/2
V
DD2
Typ.+0.5
V
DD5
Voltage
V
DD5
1/4 bias
Typ.0.4
2
V
DD2
Typ.+0.4
High-speed clock oscillation
stopped
V
DD
= 1.5 V
2.8
--
3.0
V
DDH
Voltage
(Backup used)
V
DDH
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
V
DD
= 1.5 V
2.0
--
2.7
High-speed clock oscillation
stopped
1.0
1.5
2.0
V
DDL
Voltage
V
DDL
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
V
DD
= 1.2 to 5.5 V
1.2
--
5.5
V
1
Note:
1.
"
V
DD2
"
changes in the range from 1.8 to 2.4 V according to the valve of Display Contrast
register (DSPCNT)
FEDL63193-04
1Semiconductor
ML63193
23/37
DC Characteristics (2)
(V
DD
= V
DDI
= 0.9 to 5.5 V, V
SS
= 0 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
Crystal Oscillation
Start Voltage
V
STA
Oscillation start time:
within 5 seconds
1.2
--
--
Backup used
0.9
--
--
Crystal Oscillation
Hold Voltage
V
HOLD
Backup not used
1.7
--
--
V
Crystal Oscillation
Stop Detect Time
T
STOP
--
0.1
--
5.0
ms
External RC
Oscillator
Capacitance
C
G
--
5
--
25
Internal RC
Oscillator
Capacitance
C
D
--
20
25
30
External Ceramic
Oscillator
Capacitance
C
L0
, C
L1
CSA2.00 MG
(Murata MFG.make) used
V
DD
= 3.0 V
--
30
--
Internal RC
Oscillator
Capacitance
C
OS
--
8
12
16
pF
V
DD
= 1.5 V
0
--
0.4
POR Voltage
V
POR1
V
DD
= 3.0 V
0
--
0.7
V
DD
= 1.5 V
1.2
--
1.5
Non-POR Voltage
V
POR2
V
DD
= 3.0 V
2
--
3
LD1 = 1, LD0 = 1, Ta = 25
C
2.30
2.40
2.50
LD1 = 1, LD0 = 0, Ta = 25
C
1.70
1.80
1.90
LD1 = 0, LD0 = 1, Ta = 25
C
1.10
1.20
1.30
BLD Judgment
Voltage
V
BLDC
LD1 = 0, LD0 = 0, Ta = 25
C
0.95
1.05
1.15
V
V
BLDC
= 2.40 V (LD1 = 1, LD0 = 1)
--
3.5
--
V
BLDC
= 1.80 V (LD1 = 1, LD0 = 0)
--
2.3
--
V
BLDC
= 1.20 V (LD1 = 0, LD0 = 1)
--
1.6
--
BLD Judgment
Voltage
Temperature
Deviation
V
BLDC
V
BLDC
= 1.05 V (LD1 = 0, LD0 = 0)
--
1.2
--
mV/
C
1
Notes: 1.
"
T
STOP
"
indicates that if the crystal oscillator stops over the value of T
STOP
, the system reset
occurs.
2.
"
POR
"
denotes Power On Reset. (When not using RESET sampling circuit)
3.
"
V
POR1
"
indicates that POR occurs when V
DD
falls from V
DD
to V
POR1
and again rises up to V
DD
.
4.
"
V
POR2
"
indicates that POR dose not occur when V
DD
falls from V
DD
V
POR2
and again rises up to
V
DD
.
FEDL63193-04
1Semiconductor
ML63193
24/37
DC Characteristics (3)
When backup is used
(Low-speed clock = Crystal oscillation (32.768 kHz), V
DD
= V
DDI
= 1.5 V, V
SS
= 0 V,
Display contrast register (DSPCNT) = 0H, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
Ta = 20 to +50
C
--
5.6
6.5
Supply
Current 1
I
DD1
CPU is in HALT state.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
5.6
15.0
Ta = 20 to +50
C
--
4.5
5.0
Supply
Current 2
I
DD2
CPU is in HALT state.
LCD is in Power Down
mode.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
4.5
13.0
Ta = 20 to +50
C
--
23
26
Supply
Current 3
I
DD3
CPU is in operation at
low-speed oscillation.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
23
30
Supply
Current 4
I
DD4
CPU is in operation at high-speed oscillation.
(approx. 700 kHz RC oscillation,
R
OSH
= 100 k
)
--
1100 1500
Supply
Current 5
I
DD5
CPU is in operation at high-speed oscillation.
(1 MHz Ceramic oscillation)
--
950
1200
A
1
FEDL63193-04
1Semiconductor
ML63193
25/37
DC Characteristics (4)
When backup is not used
(Low-speed clock = Crystal oscillation (32.768 kHz), V
DD
= V
DDI
= 3.0 V, V
SS
= 0 V,
Display contrast register (DSPCNT) = 0H, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
Ta = 20 to +50
C
--
2.6
3.5
Supply
Current 1
I
DD1
CPU is in HALT state.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
2.6
7.0
Ta = 20 to +50
C
--
2.0
2.8
Supply
Current 2
I
DD2
CPU is in HALT state.
LCD is in Power Down
mode.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
2.0
6.0
Ta = 20 to +50
C
--
12
13
Supply
Current 3
I
DD3
CPU is in operation at
low-speed oscillation.
(High-speed clock
oscillation stopped)
Ta = 20 to +70
C
--
12
16
Supply
Current 4
I
DD4
CPU is in operation at high-speed oscillation.
(approx. 700 kHz RC oscillation,
R
OSH
= 100 k
)
--
1000
1200
Supply
Current 5
I
DD5
CPU is in operation at high-speed oscillation.
(2 MHz Ceramic oscillation)
--
1100
1300
A
1
FEDL63193-04
1Semiconductor
ML63193
26/37
DC Characteristics (5)
(V
DD
= V
DDI
= V
DDH
= 3.0 V, V
DD1
= 1.1 V, V
DD2
= 2.2 V, V
DD3
= 3.3 V, V
DD4
= 4.4 V,
V
DD5
= 5.5 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
V
DDI
= 1.5 V
2.5
1.4
0.4
V
DDI
= 3.0 V
6.0
3.5
1.0
I
OH1
V
OH1
= V
DDI
0.5 V
V
DDI
= 5.0 V
8.5
5.0
1.5
V
DDI
= 1.5 V
0.4
1.4
2.5
V
DDI
= 3.0 V
1.0
3.0
6.0
Output Current 1
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
I
OL1
V
OL1
= 0.5 V
V
DDI
= 5.0 V
1.5
3.7
8.5
V
DD
= 1.5 V
4.0
2.0
0.5
V
DD
= 3.0 V
11.0
6.0
2.0
I
OH2
V
OH2
= V
DD
0.7 V
V
DD
= V
DDH
= 5.0 V
14.0
9.0
4.0
V
DD
= 1.5 V
0.5
2.0
4.0
V
DD
= 3.0 V
2.0
5.5
11.0
Output Current 2
(MD, MDB)
I
OL2
V
OL2
= 0.7 V
V
DD
= V
DDH
= 5.0 V
4.0
7.0
14.0
mA
I
OH3
V
OH3
= V
DD5
0.2 V (V
DD5
level)
--
4
I
OHM3
V
OHM3
= V
DD4
+ 0.2 V (V
DD4
level)
4
--
--
I
OHM3S
V
OHM3S
= V
DD4
0.2 V (V
DD4
level)
--
--
4
I
OMH3
V
OMH3
= V
DD3
+ 0.2 V (V
DD3
level)
4
--
--
I
OMH3S
V
OMH3S
= V
DD3
0.2 V (V
DD3
level)
--
--
4
I
OML3
V
OML3
= V
DD2
+ 0.2 V (V
DD2
level)
4
--
--
I
OML3S
V
OML3S
= V
DD2
0.2 V (V
DD2
level)
--
--
4
I
OLM3
V
OLM3
= V
DD1
+ 0.2 V (V
DD1
level)
4
--
--
I
OLM3S
V
OLM3S
= V
DD1
0.2 V (V
DD1
level)
--
--
4
Output Current 3
(SEG0 to SEG63)
(COM1 to COM16)
I
OL3
V
OL3
= V
SS
+ 0.2 V (V
SS
level)
4
--
--
A
V
DD
= V
DDH
= 3.0 V
2.5
1.3
0.25
I
OH4R
V
OH4R
= V
DDH
0.5 V
(RC oscillation)
V
DD
= V
DDH
= 5.0 V
3.5
1.7
0.5
V
DD
= V
DDH
= 3.0 V
0.25
1.5
2.5
I
OL4R
V
OL4R
= 0.5 V
(RC oscillation)
V
DD
= V
DDH
= 5.0 V
0.5
1.8
3.5
mA
V
DD
= V
DDH
= 3.0 V
500
250
100
I
OH4C
V
OH4C
= V
DDH
0.5 V
(ceramic oscillation)
V
DD
= V
DDH
= 5.0 V
800
350
200
V
DD
= V
DDH
= 3.0 V
200
500
800
Output Current 4
(OSC1)
I
OL4C
V
OL4c
= 0.5 V
(ceramic oscillation)
V
DD
= V
DDH
= 5.0 V
400
700
1000
I
OOH
V
OH
= V
DDI
--
--
0.3
Output Leakage
Current
(P2.0 to P2.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
I
OOL
V
OL
= V
SS
0.3
--
--
A
2
FEDL63193-04
1Semiconductor
ML63193
27/37
DC Characteristics (6)
(V
DD
= V
DDI
= V
DDH
= 3.0 V, V
DD1
= 1.1 V, V
DD2
= 2.2 V, V
DD3
= 3.3 V, V
DD4
= 4.4 V,
V
DD5
= 5.5 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
V
DDI
= 1.5 V
2
20
45
V
DDI
= 3.0 V
30
120
260
I
IH1
V
IH1
= V
DDI
(when pulled down)
V
DDI
= 5.0 V
70
350
650
V
DDI
= 1.5 V
45
20
2
V
DDI
= 3.0 V
260
120
30
I
IL1
V
IL1
= V
SS
(when pulled up)
V
DDI
= 5.0 V
650
350
70
I
IH1Z
V
IH1
= V
DDI
(in a high impedance state)
0
--
1
Input Current 1
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
I
IL1Z
V
IL1
= V
SS
(in a high impedance state)
1
--
0
V
DD
= V
DDH
= 3.0 V
350
170
30
I
IL2
V
IL2
= V
SS
(when pulled up)
V
DD
= V
DDH
= 5.0 V
750
450
200
I
IH2R
V
IH2R
= V
DDH
(RC oscillation)
0
--
1
I
IL2R
V
IL2R
= V
SS
(RC oscillation)
1
--
0
V
DD
= V
DDH
= 3.0 V
0.5
1.8
4.0
I
IH2C
V
IH2C
= V
DDH
(ceramic oscillation)
V
DD
= V
DDH
= 5.0 V
3
6
10
V
DD
= V
DDH
= 3.0 V
4.0
1.8
0.5
Input Current 2
(OSC0)
I
IL2C
V
IL2C
= V
SS
(ceramic oscillation)
V
DD
= V
DDH
= 5.0 V
10
6
3
V
DD
= 1.5 V
10
180
350
V
DD
= 3.0 V
150
1100
2400
A
I
IH3
V
IH3
= V
DD
V
DD
= V
DDH
= 5.0 V
0.5
2.7
5.0
mA
Input Current 3
(RESET)
I
IL3
V
IL3
= V
SS
1
--
0
V
DD
= 1.5 V
50
750
1500
A
V
DD
= 3.0 V
0.5
3.0
5.5
I
IH4
V
IH4
= V
DD
V
DD
= V
DDH
= 5.0 V
2.0
6.5
11.0
mA
Input Current 4
(TST1, TST2)
I
IL4
V
IL4
= V
SS
1
--
0
A
3
FEDL63193-04
1Semiconductor
ML63193
28/37
DC Characteristics (7)
(V
DD
= V
DDI
= V
DDH
= 3.0 V, V
DD1
= 1.1 V, V
DD2
= 2.2 V, V
DD3
= 3.3 V, V
DD4
= 4.4 V,
V
DD5
= 5.5 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Meas-
uring
Circuit
V
DDI
= 1.5 V
1.2
--
1.5
V
DDI
= 3.0 V
2.4
--
3.0
V
IH1
V
DDI
= 5.0 V
4.0
--
5.0
V
DDI
= 1.5 V
0
--
0.3
V
DDI
= 3.0 V
0
--
0.6
Input Voltage 1
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
V
IL1
V
DDI
= 5.0 V
0
--
1
V
DD
= V
DDH
= 3.0 V
2.4
--
3.0
V
IH2
V
DD
= V
DDH
= 5.0 V
4.0
--
5.0
V
DD
= V
DDH
= 3.0 V
0
--
0.6
Input Voltage 2
(OSC0)
V
IL2
V
DD
= V
DDH
= 5.0 V
0
--
1
V
DD
= 1.5 V
1.35
--
1.5
V
DD
= 3.0 V
2.4
--
3.0
V
IH3
V
DD
= 5.0 V
4.0
--
5.0
V
DD
= 1.5 V
0
--
0.15
V
DD
= 3.0 V
0
--
0.6
Input Voltage 3
(RESET),
(TST1), (TST2)
V
IL3
V
DD
= 5.0 V
0
--
1
V
DDI
= 1.5 V
0.05
0.1
0.3
V
DDI
= 3.0 V
0.2
0.5
1.0
Hysteresis Width 1
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
V
T1
V
DDI
= 5.0 V
0.25
1.0
1.5
V
DD
= 1.5 V
0.05
0.1
0.3
V
DD
= 3.0 V
0.2
0.5
1.0
Hysteresis Width 2
(RESET),
(TST1), (TST2)
V
T2
V
DD
= 5.0 V
0.25
1.0
1.5
V
4
Input Pin
Capacitance
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
C
IN
--
--
--
5
pF
1
FEDL63193-04
1Semiconductor
ML63193
29/37
Measuring circuit 1
C
a
, C
b
, C
c
, C
d
, C
e
, C
l
, C
12
:
0.1
F
C
h
, C
b12
:
1
F
C
G
:
15 pF
C
L0
:
30 pF
C
L1
:
30 pF
Ceramic Resonator
:
CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
V
V
Ca
Cc
V
DD3
V
DD1
V
DDI
V
SS
XT0
XT1
*1 RC Oscillator
R
OSH
Ceramic Oscillator
C
L0
Cb12
CB1
CB2
OSC0
OSC1
A
V
DD
V
Cd
V
DD4
C
L1
Ceramic Resonator
*1
C12
C1
C2
V
Cb
V
DD2
Ce
V
DD5
V
V
Ch
V
DDH
Cl
V
DDL
V
*2
*2 RC Oscillator
R
OSL
Crystal Oscillator
C
G
Crystal
1
2
3
4
1
2
1
2
3
4
3
4
FEDL63193-04
1Semiconductor
ML63193
30/37
Measuring circuit 2
Measuring circuit 3
Measuring circuit 4
V
IH
INPUT
*3
V
IL
A
*4
*3 Input logic circuit to determine the specified measuring conditions.
*4 Measured at the specified output pins.
V
DD4
V
DD3
V
DD1
V
SS
V
DD
V
DD2
V
DD5
V
DDH
V
DDL
V
DDI
OUTPUT
V
DD3
V
DD2
A
*5
V
DDI
V
SS
V
DD
V
DD1
V
DD4
V
DDH
V
DD5
V
DDL
INPUT
OUTPUT
V
IH
*5
V
IL
*5 Measured at the specified input pins.
Waveform
Monitoring
V
DD3
V
DD2
V
DDI
V
DD
V
DD1
V
DD4
V
DDH
V
DD5
V
SS
V
DDL
INPUT
OUTPUT
FEDL63193-04
1Semiconductor
ML63193
31/37
AC Characteristics (Serial Interface, Serial Port)
(1) Synchronous Communication
(V
DD
= 0.9 to 5.5 V, V
DDH
= 1.8 to 5.5 V, V
SS
= 0 V, V
DDI
= 5.0 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
t
f
--
--
--
1.0
TXC/RXC Input Rise Time
t
r
--
--
--
1.0
TXC/RXC Input "L" Level Pulse Width
t
CWL
--
0.8
--
--
TXC/RXC Input "H" Level Pulse Width
t
CWH
--
0.8
--
--
TXC/RXC Input Cycle Time
t
CYC
--
2.0
--
--
TXC/RXC Output Cycle Time
t
CYC (O)
CPU is in operating at
32.768 kHz
--
30.5
--
TXD Output Delay Time
t
DDR
Output load capacitance
10 pF
--
--
0.4
RXD Input Setup Time
t
DS
--
0.5
--
--
RXD Input Hold Time
t
DH
--
0.8
--
--
s
Synchronous communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
t
r
t
f
t
CWH
t
CWL
t
DDR
t
DDR
t
CYC
t
DS
t
DS
t
DH
V
DDI
V
SS
V
DDI
V
SS
V
DDI
V
SS
TXC (PC.1)/
RXC (PC.2)
TXD (PC.3)
RXD (PC.0)
FEDL63193-04
1Semiconductor
ML63193
32/37
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transmit Baud Rate
T
BRT
T
BRT
= 1/f
BRT
T
CR
= 1/f
OSC
T
BRT
T
CR
T
BRT
T
BRT
+ T
CR
Receive Baud Rate
R
BRT
R
BRT
= 1/f
BRT
R
BRT
0.97
R
BRT
R
BRT
1.03
s
f
BRT
: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
T
BRT
V
DDI
V
SS
TXD (PC.3)
R
BRT
V
DDI
V
SS
RXD (PC.0)
FEDL63193-04
1Semiconductor
ML63193
33/37
AC Characteristics (Serial Interface, Shift Register)
(V
DD
= 0.9 to 5.5 V, V
DDH
= 1.8 to 5.5 V, V
DDI
= 5.0 V, V
SS
= 0 V, Ta = 20 to +70
C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SCLK Input Fall Time
t
f
--
--
--
1.0
SCLK Input Rise Time
t
r
--
--
--
1.0
SCLK Input "L" Level Pulse Width
t
CWL
--
0.8
--
--
SCLK Input "H" Level Pulse Width
t
CWH
--
0.8
--
--
SCLK Input Cycle Time
t
CYC
1.8
--
--
t
CYC1(O)
CPU is in operating at
32.768 kHz
--
30.5
--
SCLK Output Cycle Time
t
CYC2(O)
CPU is in operating at 2 MHz
V
DD
= V
DDH
= 1.8 to 3.5 V
--
0.5
--
SOUT Output Delay Time
t
DDR
C
L
= 10 pF
--
--
0.4
SIN Input Setup Time
t
DS
--
0.5
--
--
SIN Input Hold Time
t
DH
--
0.8
--
--
s
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
t
r
t
f
t
CWH
t
CWL
t
DDR
t
DDR
t
CYC
t
DS
t
DS
t
DH
V
DDI
V
SS
V
DDI
V
SS
V
DDI
V
SS
SCLK (PE.2)
SOUT (PE.1)
SIN (PE.0)
FEDL63193-04
1Semiconductor
ML63193
34/37
APPLICATION CIRCUITS
Note:
V
DDI
is the power supply pin for the input-output ports.
Be sure to connect the V
DDI
pin either to the positive power supply pin (V
DD
) of this device
or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
XT0
COM1-16
XT1
V
DDH
V
DD
CB1
CB2
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
MDB
V
SS
SEG0-63
OSC0
OSC1
R
OSH
C
b12
C
v
C
G
C
12
LCD
Crystal
32.768 kHz
C
h
1.5 V
C
e
C
d
C
c
C
b
C
a
Buzzer
Crystal oscillation is selected as low-speed
oscillation by mask option.
RC oscillation is selected as high-speed
oscillation by software.
Ports are powered from external memory
power source.
C
V
is an IC power supply bypass capacitor.
Values of C
a
, C
b
, C
c
, C
d
, C
e
, C
l
, C
b12
, C
12
,
C
h
, and C
G
, are for reference only.
V
DDL
C
l
Push SW
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
1.0
F
0.1
F
1.0
F
5 to
25 pF
ML63193
1.0
F
V
DDI
V
DD
PE.1
PE.0
PE.3
PE.2
PC.1
PC.0
PC.3
PC.2
PB.1
PB.0
PB.3
PB.2
PA.1
PA.0
PA.3
PA.2
P9.1
P9.0
P9.3
P9.2
P0.1
P0.0
P0.3
P0.2
FEDL63193-04
1Semiconductor
ML63193
35/37
Note:
V
DDI
is the power supply pin for the input-output ports.
Be sure to connect the V
DDI
pin either to the positive power supply pin (V
DD
) of this device
or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
XT0
COM1-16
XT1
V
DDH
V
DD
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
MDB
V
SS
SEG0-63
OSC0
OSC1
C
v
C
G
C
12
LCD
Crystal
32.768 kHz
V
DD
5.0 V
C
e
C
d
C
c
C
v
C
a
Buzzer
Crystal oscillation is selected as low-speed
oscillation by mask option.
Ceramic oscillation is selected as high-speed
oscillation by software.
Ports, external memory, and IC share their
power supply.
C
v
is an IC power supply bypass capacitor.
Values of C
a
, C
b
, C
c
, C
d
, C
e
, C
l
, C
12
, C
G
,
C
L0
, and C
L1
are for reference only.
C
L0
30 pF
C
L1
30 pF
Ceramic
Resonator
(Example: 1 MHz)
CB1
CB2
V
DDL
C
l
ML63193
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
Open
Push SW
5 to 25 pF
0.1
F
V
DDI
V
DD
PE.1
PE.0
PE.3
PE.2
PC.1
PC.0
PC.3
PC.2
PB.1
PB.0
PB.3
PB.2
PA.1
PA.0
PA.3
PA.2
P9.1
P9.0
P9.3
P9.2
P0.1
P0.0
P0.3
P0.2
FEDL63193-04
1Semiconductor
ML63193
36/37
PACKAGE DIMENSIONS
LQFP144-P-2020-0.50-K
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
5m)
Package weight (g)
1.37 TYP.
5
Rev. No./Last Revised
5/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
(Unit : mm)
FEDL63193-04
1Semiconductor
ML63193
37/37
NOTICE
1.
The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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