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Semiconductor
ML670100
OKI's High-Performance CMOS 32-Bit Single Chip Microcontroller
GENERAL DESCRIPTION
The ML670100 is a high-performance 32-bit microcontroller combining a RISC based, 32-bit CPU core -
the ARM7TDMI
TM
- with memory and such peripheral circuits as timers, serial ports, and analog-to-
digital converter. This combination of 32-bit data processing, built-in memory, and on-chip peripherals
make it ideal for controlling equipment requiring both high speed and high functionality. An external
memory controller supports direct connection to memory and peripheral devices for adding even more
functionality.
FEATURES
Operating Voltage
2.7 to 3.6V
Operating Frequency 25MHz maximum(3.0 to 3.6V)
On-chip memory
-ROM: 128 kilobytes
-RAM: 4 kilobytes
I/O Function
I/O ports: 8 bits x 9, I/O directions are specified at the bit level
Timer
-Flexible timer (16-bit multi-function timer with six channels)
Choice of operating modes: auto-reload timer, compare output, PWM
and capture
-Time base counter with WDT function
Serial Port
-One asynchronous serial port (UART) with baud rate generator
-Two clock synchronous serial port
A-to-D Converter
-8-bit resolution A-to-D converter with eight analog input ports
Interrupt
Controller
-Support for 28 interrupt sources: 9 external and 19 internal
-Choice of eight priority levels for each source
External Memory
Controller
-Direct connection to ROM, SRAM, DRAM and peripheral devices
-Support for four banks: two for ROM, SRAM and I/O devices plus two for
DRAM
-User-configurable bus width (8/16 bits) and wait control and other
parameters for accessing memory and external devices
Clock Generator
-Built-in crystal oscillation circuit and PLL
-Choice of divider ratio (1/1, 1/2, 1/4) for adjusting operating clock frequency
to match the load of processing
Package
144-pin LQFP ( LQFP144-P-2020-0.50-K)
ARM POWERED logo is the registered trademark of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
The Information contained herein can change without notice owing to product and/or technical i
mprovement.
The signal name of negative logic is being changed to nXXX from XXX in this data sheet.
Version 2
Aug., 1999
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2
BLOCK DIAGRAM
Asterisks indicate signals that aresecondary functions of I/O ports.
Brackets indicate bit ranges.
ARM7TDMI
4 kilobytes
of RAM
128 kilobytes
of ROM
Time Base
Generator
(TBG)
Flexible
Timer
Asynchronous
Serial Interface
(ASI)
Clock
Synchronous
Interface
(CSI0 and CSI1)
Interrupt
Controller
(INT)
Analog-to-digital
Converter
(ADC)
Internal
Bus
Controller
External Memory
Controller (XMC)
I/O Ports
TDI*
TDO*
nTRST*
TMS*
TCK*
DBGEN*
DBGRQ*
DBGACK*
XA23-16*
XA15-1
nLB/XA0
XD15-8*
XD7-0
nCS0
nRD
nWRE/nWRL
nXWAIT*
nCS1*
nHB/nWRH*
nRAS1*
nWH/nCASH*
nRAS0*
nCAS/nCASL*
nWL/nWE*
nBREQ*
nBACK*
nRST
nEA
DBSEL
TEST
VDD
GND
AVDD
AGND
TMIN/TMOUT[5:0]*
TMCLK[1:0]*
ASI_TXD*
ASI_RXD*
CSI1_TXD*
CSI1_RXD*
CSI1_SCLK*
CSI0_TXD*
CSI0_RXD*
CSI0_SCLK*
nEFIQ
nEIR[7:0]*
VREF
AI[7:0]
Clock
Control
OSC0
OSC1
CLKOUT
FSEL
PLLEN
VCOM
PIO8[7:0]
PIO7[7:0]
PIO6[7:0]
PIO5[7:0]
PIO4[7:0]
PIO3[7:0]
PIO2[7:0]
PIO1[7:0]
PIO0[7:0]
Core data bus (32b)
Peripheral data bus 16b)
Core address bus
Peripheral address bus
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PIN CONFIGURATION (TOP VIEW)
Top View
INDEX MARK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
AI[4]
AI[3]
AI[2]
AI[1]
AI[0]
VREF
AVDD
VDD
TEST
DBSEL
PIO6[0]
PIO6[1]
PIO6[2]
PIO6[3]
PIO6[4]
]
PIO6[5]
]
PIO6[6]
PIO6[7]
PIO7[0]
PIO7[1]
PIO7[2]
GND
VDD
PIO7[3]
PIO7[4]
PIO7[5]
PIO7[6]/
nBREQ
PIO8[0]/DBGACK
PIO8[1]/DBGRQ
PIO8[2]/DBGEN
PIO8[3]/TCK
PIO8[4]/
TMS
PIO8[5]/
nTRST
PIO8[6]/TDO
PIO8[7]/TDI
PIO7[7]/
nBACK
XD1
XD0
VDD
GND
nEA
nEFIQ
PIO0[7]/XA23
PIO0[6]/XA22
PIO0[5]/XA21
PIO0[4]/XA20
PIO0[2]/XA18
PIO0[3]/XA19
PIO0[1]/XA17
PIO0[0]/XA16
VDD
GND
XA15
XA14
XA13
XA12
XA11
XA10
XA9
XA8
VDD
XA7
GND
XA6
GND
XA5
XA4
XA3
XA2
XA0/nLB
XA1
VDD
XD2
XD3
XD4
XD5
XD6
XD7
GND
VDD
PIO1[0]/XD8
PIO1[1]/XD9
PIO1[2]/XD10
PIO1[3]/XD11
VDD
nRD
nWRE/
nWRL
PIO2[0]/
nWL/
nWE
PIO1[4]/XD12
GND
VDD
PIO3[0]/
nEIR[0]
PIO3[5]/nEIR[5]
PIO3[6]/nEIR[6]
PIO3[7]/nEIR[7]
GND
PIO4[0]/TMIN[0]/TMOUT[0]
PIO4[1]/TMIN[1]/TMOUT[1]
PIO4[2]/TMIN[2]/TMOUT[2]
PIO4[3]/TMIN[3]/TMOUT[3]
PIO4[4]/TMIN[4]/TMOUT[4]
PIO4[5]/TMIN[5]/TMOUT[5]
PIO4[6]/TMCLK[0]
PIO4[7]/TMCLK[1]
GND
VDD
PIO5[0]/CSI0_SCLK
OSC0
OSC1
VDD
CLKOUT
FSEL
VCOM
PLLEN
GND
nRST
AGND
AI[7]
AI[6]
AI[5]
PIO1[5]/XD13
PIO1[6]/XD14
PIO1[7]/XD15
PIO2[1]/
nCAS/
nCASL
PIO2[2]/nRAS0
PIO2[3]/
nWH/
nCASH
PIO2[4]/nRAS1
PIO2[5]/
nHB/
nWRH
PIO2[6]/nCS1
PIO2[7]/
nXWAIT
GND
PIO3[1]/
nEIR[1]
PIO3[2]/
nEIR[2]
PIO3[4]/
nEIR[4]
PIO3[3]/
nEIR[3]
PIO5[1]/CSI0_RXD
PIO5[2]/CSI0_TXD
PIO5[3]/CSI1_SCLK
PIO5[4]/CSI1_RXD
PIO5[5]/CSI1_TXD
PIO5[6]/ASI_RXD
PIO5[5]/ASI_TXD
GND
nCS0
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PIN DESCRIPTIONS
Type
Signal
Name
I/O Direction Description
Address
bus
XA23 -
XA16
Output
These are bits 23-16 of the external address bus. They represent
secondary functions for I/O port PIO0[7:0].
XA15 -
XA0
Output
These are bits 15 - 0 of the external address bus.
Data bus XD15 -
XD8
Bidirectional These are bits 15-8 of the external data bus. They represent
secondary functions for I/O port PIO1[7:0].
XD7- -XD0 Bidirectional These are bits 7-0 of the external data bus.
Bus
nCS0
Output
This output is the chip select signal for bank 0.
control
signals
nCS1
Output
This output is the chip select signal for bank 1. It represents a
secondary function for I/O port PIO2[6].
nRD
Output
This output is the read signal for SRAM banks (0 and 1).
nWRL
Output
This output is the Write Enable Low signal for SRAM banks (0
and 1).
nWRH
Output
This output is the Write Enable High signal for SRAM banks (0
and 1). It represents a secondary function for I/O port
PIO2[5].
nWRE
Output
This output is the Write Enable signal for SRAM banks (0 and
1).
nLB
Output
This output is the Low Byte Select signal for SRAM banks (0
and 1).
nHB
Output
This output is the High Byte Select signal for SRAM banks (0
and 1). It represents a secondary function for I/O port PIO2[5].
nRAS0
Output
This output is the Row Address Strobe signal for bank 2.
It represents a secondary function for I/O port PIO2[2].
nRAS1
Output
This output is the Row Address Strobe signal for banks 3.
It represents a secondary function for I/O port PIO2[4].
nCASL
Output
This output is the Column Address Strobe Low signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[1].
nCASH
Output
This output is the Column Address Strobe High signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[3].
nWE
Output
This output is the Write Enable signal for DRAM banks (2 and
3). It represents a secondary function for I/O port PIO2[0].
nCAS
Output
This output is the Column Address Strobe signal for DRAM
banks (2 and 3). It represents a secondary function for I/O port
PIO2[1].
nWH
Output
This output is the Write Enable High signal for DRAM banks
(2 and 3). It represents a secondary function for I/O port
PIO2[3].
nWL
Output
This output is the Write Enable Low signal for DRAM banks (2
and 3). It represents a secondary function for I/O port PIO2[0].
nXWAIT
Input
This input pin controls insertion of wait cycles. It represents a
secondary function for I/O port PIO2[7].
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PIN DESCRIPTIONS (Cont.)
Type
Signal Name I/O Direction Description
Bus
control
nBREQ
Input
This input is a bus request signal from an external device.
It represents a secondary function for I/O port PIO7[6].
signals nBACK
Output
This output is an acknowledgment signal to a bus request signal
from an external device. It represents a secondary function for
I/O port PIO7[7].
Interru-
pts
nEFIQ
Input
This input is an external fast interrupt request (FIQ). When
accepted, the request is processed as an FIQ exception.
nEIR[7:0]
Input
This inputs are external interrupt requests. They represent
secondary functions for I/O port PIO3[7:0].
Timers TMIN[5:0]
Input
These pins function as capture trigger input pins for Flexible
Timer channels 5-0 in capture mode. They represent secondary
functions for I/O port PIO4[5:0].
TMOUT[5:0] Output
These pins function as output pins for Flexible Timer channels
5-0 in compare output or PWM mode. They represent
secondary functions for I/O port PIO4[5:0].
TMCLK[1:0] Input
These pins function as Flexible Timer channels 1 and 0 clock
input pins. They represent secondary functions for I/O port
PIO4[7:6].
Serial
ports
ASI_TXD
Output
This output is the transmit data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[7].
ASI_RXD
Input
This input is the receive data for the Asynchronous Serial
Interface. It represents a secondary function for I/O port
PIO5[6].
CSI0_TXD
Output
This output is the transmit data for the Clock Synchronous
Serial Interface 0. It represents a secondary function for I/O
port PIO5[2].
CSI0_RXD
Input
This input is the receive data for the Clock Synchronous Serial
Interface 0. It represents a secondary function for I/O port
PIO5[1].
CSI0_SCLK
Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 0. It represents a secondary
function for I/O port PIO5[0].
CSI1_TXD
Output
This output is the transmit data for the Clock Synchronous
Serial Interface 1. It represents a secondary function for I/O
port PIO5[5].
CSI1_RXD
Input
This input is the receive data for the Clock Synchronous Serial
Interface 1. It represents a secondary function for I/O port
PIO5[4].
CSI1_SCLK
Bidirectional This pin accepts/provides clock signal for the Clock
Synchronous Serial Interface 1. It represents a secondary
function for I/O port PIO5[3].
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PIN DESCRIPTIONS (Cont.)
Type
Signal
Name
I/O Direction Description
Analog-
to-digital
VREF
Input
This input is the reference voltage for the analog-to-digital
converter channels 7-0. Connect it to VDD.
converter AI[7:0]
Input
These are analog signal input pins for analog-to-digital
converter channels 7-0.
Debugg-
ing
TDI
Input
This input is the serial data input for the debugging scan circuit.
It represents a secondary function for I/O port PIO8[7].
interface TDO
Output
This output is the serial data output for the debugging scan
circuit. It represents a secondary function for I/O port
PIO8[6].
nTRST
Input
"L" level input to this pin resets the debugging scan circuit.
It represents a secondary function for I/O port PIO8[5].
TMS
Input
This input selects the mode for the debugging scan circuit.
It represents a secondary function for I/O port PIO8[4].
TCK
Input
This input is the serial clock input for the debugging scan
circuit. It represents a secondary function for I/O port
PIO8[3].
DBGEN
Input
"H" level input to this pin enables the CPU's debugging
function. It represents a secondary function for I/O port
PIO8[2].
DBGRQ
Input
This input is a debugging request signal from an external
device. It represents a secondary function for I/O port
PIO8[1].
DBGACK
Output
This output is an acknowledgment signal to a debugging
request signal from an external device. It represents a secondary
function for I/O port PIO8[0].
I/O ports PIO8[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO7[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO6[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO5[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO4[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO3[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO2[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO1[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
PIO0[7:0]
Bidirectional These form an 8-bit I/O port. I/O directions are specified at the
bit level.
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PIN DESCRIPTIONS (Cont.)
Type
Signal
Name
I/O
Direction
Description
Clock
control
OSC0
Input
This pin is for connecting a crystal oscillator. If an external
clock is used, supply it to this pin.
OSC1
Output
This pin is for connecting a crystal oscillator. If an external
clock is used, leave this pin open.
CLKOUT
Output
This output is the internal system clock signal.
FSEL
Input
Connect this pin to VDD or ground to indicate the frequency
range for the basic clock.
PLLEN
Input
Connect this pin to VDD to enable the built-in phase-looked
loop. If the PLL is not used because an external clock with a
guaranteed duty is available, connect this pin to ground.
VCOM
Input
This input controls the oscillation frequency of the PLL's
voltage-controlled oscillator. Connect it to ground.
System
control
nRST
Input
"L" level input to this pin produces an external system reset for
this LSI. "H" level input then causes execution to resume from
address 0x000000.
DBSEL
Input
During a system reset of this LSI, this input specifies the width
of the external data bus for bank 0. Connect this pin to VDD for
a data bus width of 16bits and to ground for 8bits.
nEA
Input
During a system reset of this LSI, this input controls the use of
the internal ROM. Connect this pin to VDD to enable the ROM
and to ground to disable it.
TEST
Input
During a system reset of this LSI, this input controls the initial
pin functions for the I/O port 8 pins(PIO8[7:0]). Connect this
pin to VDD to initialize the port for its secondary function, the
debugging interface, and to ground for I/O.
Power
Supply
VDD
Input
These pins are this LSI's power supply pins. Connect them all to
VDD.
GND
Input
These pins are this LSI's ground pins. Connect them all to
ground.
AVDD
Input
This pin is the analog-to-digital converter's power supply.
Connect it to VDD.
AGND
Input
This pin is the analog-to-digital converter's ground pin.
Connect it to ground.
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OUTLINE of PERIPHERAL FUNCTIONS
I/O Ports
The I/O ports consist of nine 8-bit ports: PIOn(n=0 - 8). I/O directions are specified at the bit level. When
configured for input, the pins use high-impedance input.
Flexible Timer
The flexible timer consists of six 16-bit timer channels. Each channel offers independent choice of four
operating modes and of eight count clocks.
-Timer operating modes
- Auto-reload timer
- Compare output
- Pulse width modulation (PWM)
- Capture input
-Timer synchronization
- Timer channels can be started and stopped in union.
-External clocks
- Timer channels 0 and 1 accept external clock signals.
Time Base Generator
The time base generator consists of the time base counter, a frequency divider which derives the time base
signals for the on-chip peripherals from the system clock signals, and watchdog timer, which counts time
base clock cycles and produces a system reset signal when its internal counter overflows.
Asynchronous Serial Interface
The asynchronous serial interface is a serial port that frames each character of information with start and
stop elements. Parameters control transfer speed (using a dedicated baud rate generator), character length,
number of stop bits and use of parity.
-Built-in baud rate generator
-Character length: 7 or 8 bits
-Stop bits: 1 or 2
-Parity: none, odd, or even
-Error detection for receiving: parity, framing and overrun errors
-Full duplex operation
Clock Synchronous Serial Interface
The clock synchronous serial interface are two channels of serial ports that transmit 8-bit data
synchronized with internal or external clock signals.
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Analog-to-Digital Converter
The analog-to-digital converter is an 8-bit successive approximation analog-to-digital converter with
eight input channels and four result registers. It offers two operating mode: scan mode, which
sequentially converts the inputs from the selected set of four input channels, and select mode, which
converts the input from a single input channel.
-Resolution: 8 bits
-Eight analog input channels
-Four result registers for holding conversion results
-Operating modes
- Scan modes: Sequential conversion of the analog inputs from the upper or lower set of four
input channels
- Select mode: Conversion of the analog inputs from a single input channel
Interrupt Controller
The interrupt controller manages interrupt requests from 9 external sources and 19 internal ones and
passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. It
supports eight interrupt levels for each source for use in priority control.
-The interrupt controller supports 9 external interrupt sources connected to nEFIQ and nEIR[7:0] pins
and 19 internal interrupt sources, including the serial ports and the flexible timer channels.
-The interrupt controller simplifies interrupt priority control with a choice of eight interrupt levels for
each source.
-The interrupt controller assigns a unique interrupt number to each source to permit rapid branching
to the appropriate routine.
External Memory Controller
The external memory controller generates control signals for accessing external memory (ROM, SRAM,
DRAM, etc.), and other devices with address in the external memory space.
-Support for direct connection of ROM, SRAM and I/O devices
- Strobe signal outputs for a variety of memory and I/O devices
-Support for direct connection of DRAM
- Multiplexed row and column addresses
- Random access and high-speed paged modes
- Programmable wait cycle insertion
-Memory space divided into four banks
- Two banks for ROM, SRAM and I/O devices
- Two banks for DRAM
- Address space of 16 megabytes for each bank
- Separate data bus width (8 or 16 bits), wait cycle, and off time setting for each bank
-Single-stage store buffer permitting internal access during a wait cycle to external memory or device
-Arbitration of external bus requests from external devices
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Clock Controller
The clock controller controls the oscillator circuit based on a crystal oscillator and a built-in phase-locked
loop which together generate and control the system clock signal. It offers a choice of divider ratio (1/1,
1/2 and 1/4) for adjusting operating clock frequency to match the load of processing. It also controls the
transitions to and from a stand-by mode, HALT mode.
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CONFIGURATIONS of PINS and I/O PORTS
Input Pins (nRST, nEA, DBSEL, TEST, nEFIQ, FSEL, PLLEN, VCOM)
Output Pin (CLKOUT)
Tri-state output pins (XA23 - XA1, nLB/XA0, nCS0, nRD, nWRE/nWRL)
Bidirectional pins (XD7 - XD0)
VDD
GND
Input pins
(high impedance)
Bidirectional pins
(CMOS output when enabled)
Output enable
signal
Read signal
VDD
GND
Output pin
(CMOS output)
Output pins
(CMOS output when enabled)
Output enable
signal
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I/O port A (I/O ports without second functions)
PIO6[7:0], PIO7[5:0]
I/O port B (I/O ports with second functions of input)
PIO2[7], PIO3[7:0] , PIO4[7:6] , PIO5[6] , PIO5[4], PIO5[1] , PIO7[6] , PIO8[7] , PIO8[5:1]
PMm [n]
POm [n]
PIOm [n]
Peripheral bus
Read PIm [n]
PMm [n]
POm [n]
PIOm [n]
Peripheral bus
Read PIm [n]
PFSm [n]
Secondary function
input signal
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I/O port C (I/O ports with second functions of output)
PIO5[7], PIO5[5], PIO5[2], PIO7[7], PIO8[6], PIO8[0]
PMm [n]
POm [n]
PIOm [n]
Peripheral bus
Read PIm [n]
PFSm [n]
Secondary function
output signal
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I/O port D (I/O ports with second functions of tri-state output)
PIO0[7:0], PIO2[6:0]
PMm [n]
POm [n]
PIOm [n]
Peripheral bus
Read PIm [n]
PFSm [n]
Secondary function
output signal
Secondary function output
enable signal
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I/O port E (I/O ports with second functions of input and output)
PIO1[7:0], PIO4[5:0], PIO5[3], PIO5[0]
PMm [n]
POm [n]
PIOm [n]
Peripheral bus
Read PIm [n]
PFSm [n]
Secondary function
output signal
Secondary function output
enable signal
Secondary function
input signal
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ELECTRICAL CHARACTERISTICS
Absolute Maximum ratings
Item
Symbol
Condition
Rated Value
Unit
Power supply
V
DD
-0.3 to 4.6
V
Input voltage
V
IN
V
DD
=AV
DD
=V
REF
-0.3 to V
DD
+0.3
Analog input voltage
V
AI
GND=AGND=0V
-0.3 to AV
DD
+0.3
V
Output current
I
O
12
mA
Power dissipation
P
D
Ta=25V
850
mW
Storage temperature
T
STG
-
-55 to +150
C
Recommended Operating Conditions
(Condition: GND=AGND=0V)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Power supply
V
DD
-
2.7
3.3
3.6
Analog power supply
AV
DD
V
DD
=AV
DD
2.7
3.3
3.6
V
Analog reference
voltage
V
REF
-
AV
DD
-0.3
-
AV
DD
Analog input voltage
V
AI
-
AGND
-
V
REF
Operating Frequency 1
f
C1
V
DD
=3.0 to 3.6V, 1
4
-
25
Operating Frequency 2
f
C2
V
DD
=2.7 to 3.6V, 2
4
-
20
MHz
Ambient temperature
T
a
-
-40
25
+85
C
1
Basic clock frequency
from the oscillator
circuit or an external
clock signal
PLLEN Input
FSEL Input
Operating Frequency 1
f
C1
4 - 6.25MHz
"H" level
"H" level (Connect to V
DD
)
4 - 25MHz
8 - 12.5MHz
(Connect to V
DD
)
"L" level (Connect to GND)
4 - 25MHz
4 - 25MHz
(External clock only)
"L" level
(Connect to GND)
"H" level (Connect to V
DD
)
or
"L" level (Connect to GND)
4 - 25MHz
2
Basic clock frequency
from the oscillator
circuit or an external
clock signal
PLLEN Input
FSEL Input
Operating Frequency 2
f
C2
4 - 5MHz
"H" level
"H" level (Connect to V
DD
)
4 - 20MHz
8 - 10MHz
(Connect to V
DD
)
"L" level (Connect to GND)
4 - 20MHz
4 - 20MHz
(External clock only)
"L" level
(Connect to GND)
"H" level (Connect to V
DD
)
or
"L" level (Connect to GND)
4 - 20MHz
Semiconductor
ML670100
/ 27
17
DC Characteristics
(Condition: V
DD
=AV
DD
=V
REF
=2.7V to 3.6V, GND=AGND=0V, Ta=-40 to +85
C)
Item
Symbo
l
Condition
Min.
Typ.
Max.
Unit
High level input voltage 1
V
IH1
1
0.65x V
DD
-
V
DD
+0.3
High level input voltage 2
V
IH2
2
2
-
V
DD
+0.3
Low level input voltage 1
V
IL1
1
-0.3
-
0.3x V
DD
Low level input voltage 2
V
IL2
2
-0.3
-
0.8
High level output voltage
V
OH
I
OH
=-4mA
I
OH
=-100uA
2.2(
*
2)
V
DD
-0.2
-
-
-
-
Low level output voltage
V
OL
I
OL
= 4mA
-
-
0.4
V
Input leak current 1
|I
LI
|
V
I
=0/V
DD
,3
-
-
2.0(
*
3)
Input leak current 2
|I
L2
|
V
I
=0/V
DD
,4
-
-
10.0(
*
3)
Output leak current
|I
LO
|
V
O
=0/V
DD
-
-
2.0(
*
3)
A
Input capacity
C
I
-
-
6
-
Output capacity
C
O
-
-
9
-
Input/output capacity
C
IO
-
-
10
-
F
Power consumption
(in HALT mode)
I
DDH
-
30
50
Power consumption
I
DD
f
C
= 25MHz
No load
-
60
100
mA
1 Applied to PIO8 - PIO0, XD7 - XD0, nEFIQ
2 Applied to nRST, nEA, DBSEL, TEST, FSEL, PLLEN, VCOM
3 Applied to Input pins other than OSC0
4 Applied to OSC0
(
*
1): Typ. means that V
DD
=3.3V, Ta=25
C
(
*
2): 2.4V in case of that V
DD
=AV
DD
=V
REF
=3.0 to 3.6V
(
*
3): 20
A in case of that T
a
is equal or greater than 50
C
Semiconductor
ML670100
/ 27
18
AC Characteristics
(Condition: V
DD
=AV
DD
=V
REF
=2.7V to 3.6V, GND=AGND=0V,Ta=-40 to +85
C)
Clock timing
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Clock frequency
f
C
4
-
25
MHz
Clock cycle time
t
C
40
-
250
Clock high level pulse width
t
CH
16
-
-
Clock low level pulse width
t
CL
16
-
-
ns
External clock frequency
f
EXC
4
-
25
MHz
External clock cycle time
t
EXC
40
-
250
External clock high level pulse width
t
EXCH
16
-
-
External clock low level pulse width
t
EXCL
V
DD
=3.0 to 3.6V
16
-
-
ns
Clock frequency
f
C
4
-
20
MHz
Clock cycle time
t
C
50
-
250
Clock high level pulse width
t
CH
20
-
-
Clock low level pulse width
t
CL
20
-
-
ns
External clock frequency
f
EXC
4
-
20
MHz
External clock cycle time
t
EXC
50
-
250
External clock high level pulse width
t
EXCH
20
-
-
External clock low level pulse width
t
EXCL
V
DD
=2.7 to 3.6V
20
-
-
Clock rise time
t
R
-
-
-
5
Clock fall time
t
F
-
-
-
5
External clock rise time
t
EXR
-
-
-
5
External clock fall time
t
EXF
-
-
-
5
ns
Semiconductor
ML670100
/ 27
19
Control Signals Timing
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
nRST pulse width
(
*
1)
t
RSTW1
-
2t
C
-
-
ns
nRST pulse width
(
*
2)
t
RSTW2
Oscillation
stable time
-
-
-
nEFIQ pulse width
t
EFIQW
-
2t
C
-
-
nEIR pulse width
t
EIRW
-
2t
C
-
-
TMIN pulse width
t
TMINW
-
2t
C
-
-
TMCLK pulse width
t
TMCLKW
-
2t
C
-
-
ns
SCLKfrequency
f
SC
-
-
-
1/8f
C
MHz
SCLK high level pulse width
t
SCLKH
-
4t
C
-
-
SCLK low level pulse width
t
SCLKL
-
4t
C
-
-
TXD delay time
t
TXD
C
L
=50pF
-
-
1t
C
+22
RXD set-up time
t
RXS
-
0.5t
C
-
-
RXD hold time
t
RXH
-
1.5t
C
-
-
DBGRQ set-up time
t
RQS
-
1.0
-
-
DBGRQ hold time
t
RQH
-
2.6
-
-
DBGACK delay time
t
DBGD
C
L
=50pF
2.4
-
15.2
ns
(
*
1): Not applied to power-on.
(
*
2): Applied to power-on.
Semiconductor
ML670100
/ 27
20
External Bus Timing
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
XA[23:1],nLB/XA0 delay time
t
XAD
3
-
14
XD[15:0] output delay time
t
XDOD
5
-
20
XD[15:0] input set-up time
t
XDIS
11
-
-
XD[15:0] input hold time
t
XDIH
0
-
-
nXWAIT set-up time
t
XWAITS
3
-
-
nXWAIT hold time
t
XWAITH
0
-
-
nHB delay time
t
HBD
2
-
12
nCS[1:0] delay time
t
CSD
2
-
11
nWRE,nWRH,nWRL delay time
t
WRD
3
-
12
nRD delay time
t
RDD
4
-
11
nRAS[1:0] delay time
t
RASD
3
-
12
nCAS delay time
t
CASD
3
-
13
nWE,nWH,nWL delay time
t
WED
2
-
12
nBREQ set-up time
t
BREQS
5
-
-
nBREQ hold time
t
BREQH
3
-
-
nBACK delay time
t
BACKD
4
-
13
High-impedance delay time
t
XHD
C
L
=50pF
4
-
13
ns
Semiconductor
ML670100
/ 27
21
Clock Timing
Control Signals Timing
t
SCLKL
t
SCLKH
t
TXD
t
RXS
t
RXH
SCLK
TXD
RXD
t
C
t
CH
t
CL
t
R
t
F
t
EXC
t
EXCH
t
EXCL
t
EXR
t
EXF
CLKOUT
External
Clock
nEFIQ
nEIR
nRST
t
RSTW1,
t
RSTW2
t
EFIQW ,
t
EIRW
t
TMINW,
t
TMCLKW
TMIN
TMCK
Semiconductor
ML670100
/ 27
22
Control Signals Timing (Cont.)
t
DBGD
t
RQS
t
RQH
CLKOUT
DBGACK
DBGRQ
Semiconductor
ML670100
/ 27
23
External Bus Timing
Bank 0 and Bank 1 Write Cycle Timing
t
HBD
t
XAD
t
XAD
t
HBD
t
CSD
t
CSD
t
WRD
t
WRD
t
XDOD
t
XDOD
Write Data
CLKOUT
XA23-1
nLB/XA
nHB
nCS0
nCS1
nWRE
nWRL
nWRH
XD15-0
Semiconductor
ML670100
/ 27
24
Bank 0 and Bank 1 Read Cycle Timing
t
HBD
t
XAD
t
XAD
t
HBD
XD15-0
t
CSD
t
CSD
t
RDD
t
RDD
t
XDIS
t
XDIH
Read Data
CLKOUT
XA23-1
nLB/XA
nHB
nCS0
nCS1
nRD
Semiconductor
ML670100
/ 27
25
Bank 2 and Bank 3 Read/Write Cycle Timing
CAS before RAS (CBR) Refresh
t
XAD
t
RASD
t
RASD
t
CASD
t
CASD
t
XDIS
t
XDIH
t
XAD
t
XDOD
t
XDOD
t
WED
t
WED
CLKOUT
XA23-1
nLB/XA
nRAS0
nRAS1
nCAS
nCASL
nCASH
XD15-0
(Read cycle)
XD15-0
(Write cycle)
nWE, nWL
nWH
(Write cycle)
t
RASD
t
RASD
t
CASD
t
CASD
CLKOUT
nRAS
nCAS
Semiconductor
ML670100
/ 27
26
Self Refresh
nXWAIT Input Timing
External Bus Release Timing
t
XWAITS
t
XWAITH
CLKOUT
nXWAIT
CLKOUT
nRAS
nCAS
t
RASD
t
RASD
t
CASD
t
CASD
t
BREQS
t
BREQH
CLKOUT
nBREQ
CLKOUT
nBACK
t
BACKD
t
BACKD
t
XHD
t
XHD
XA
XD
Control
Signals
Semiconductor
ML670100
/ 27
27
A-to-D Converter Characteristics
(Condition: V
DD
=AV
DD
=V
REF
=2.7V to 3.6V, GND=AGND=0V,Ta=-40 to +85
C )
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Resolution
n
-
-
8
bit
Linearity error
E
L
Refer to the following
-3.0
-
+3.0
LSB
Differential
linearity error
E
D
recommended circuit.
Analog input source impedance
-1.0
-
+1.0
LSB
Zero scale error
E
ZS
R
I
is equal or less than 5K
-
-
+2.0
LSB
Full scale error
E
FS
-
-
-2.0
LSB
Conversion time
t
CONV
f
C
=25MHz
-
10.68
-
S/CH
Definitions of terms
Resolution
The minimum distinguishable analog value.
For 8 bits, 2
8
=256, i.e.(VREF-AGND)/256.
Linearity error
Variance between the ideal conversion characteristics as an 8-bit A-to-D
converter and actual conversion characteristics (does not include
quantatized error).
Differential
linearity error
Indicates the smoothness of the conversion. The width of analog input
voltage corresponding to the change by one bit of digital output is
1LSB=(VREF-AGND)/256 ideally. The variance between this ideal bit
size and bit size at arbitrary point in the conversion range.
Zero scale error
Variance between the ideal conversion characteristics at the switching
point of digital output "0x00" - "0x01" and actual conversion
characteristics.
Full scale error
Variance between the ideal conversion characteristics at the switching
point of digital output "0xFE" - "0xFF" and actual conversion
characteristics.
R
I
(Analog input source impedance) is equal or less than 5K
0.1
F
0.1
F
3.3V
Analog
input
0.1
F
0.1
F
47
F
+
R
I
+
-
ML670100
V
RE
F
V
DD
AI[7:0]
GND
AGND
AV
DD
47
F
+
3.3V
0V
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