FEDL7022-01-06

1Semiconductor

This version: May 2000
Previous version: Sep. 1999

ML7022-01

Single Rail Dual Channel PCM CODEC

1/20

GENERAL DESCRIPTION

The ML7022 is a two-channel single-rail CODEC CMOS IC for voice signals ranging from 300 to 3400Hz. This
device contains two-channel analog-to-digital (A/D) and digital-to-analog (D/A) converters on a single chip. The
ML7022 is designed especially for a single power supply and low power applications and achieves a reduced
footprint.
The ML7022 is best suited for line card applications with easy interface to subscriber line interface circuits
(SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external
components and optimizing board space.

FEATURES

Single 5 V Power Supply Operation

Using

ADC and DAC Technique

Low Power Consumption
2-Channel Operating Mode:

typical: 70 mW

max.: 90 mW

1-Channel Operating Mode:

typical: 40 mW

max.: 55 mW

Power Saving Mode: (CPD1 = CPD2 = "0")

typical: 9 mW

max.: 12.5 mW

Power Down Mode: (PDN = "0")

typical: 0.05 mW

max.: 0.25 mW

ITU-T Companding Law -

-law

Built-in Dual 3-bit Latches with CMOS Drive Capability

Serial PCM Interface

Master Clock: 4.096 MHz

Transmission Clocks:
256 to 4096 kbps

Adjustable Transmit Gain

Built-in Reference Voltage Supply

Analog Output can Directly Drive a 600

Line Transformer

Latched Content Echo-back Function

Package Type:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB)

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PIN DESCRIPTIONS

Symbol

Type

Description

Power Supply *

TEST1

Device Test Pin 1

TEST2

Device Test Pin 2

AIN1

Channel-1 Transmit Op-amp Input

GSX1

Channel-1 Transmit Op-amp Output

AOUT1

Channel-1 Receive Output

TEST3

Device Test Pin 3

Analog Ground

SGC

Signal Ground

AOUT2

Channel-2 Receive Output

GSX2

Channel-2 Transmit Op-amp Output

AIN2

Channel-2 Transmit Op-amp Input

TEST4

Device Test Pin 4

TEST5

Device Test Pin 5

Power Supply *

TEST6

Device Test Pin 6

C1B

C1B Bit Latched Output

C2B

C2B Bit Latched Output

C3B

C3B Bit Latched Output

MCK

Master Clock (4.096 MHz)

BCLK

Shift Clock for the DIN and DOUT

DIN

Data Input

DOUT

Data Output

Digital Ground

XSYNC

Transmit Synchronizing Signal

RSYNC

Receive Synchronizing Signal

C3A

C3A Bit Latched Output

C2A

C2A Bit Latched Output

C1A

C1A Bit Latched Output

PDN

Power Down Control

* V

of pin 1 and V

of pin 15 are connected internally, but these pins must be connected on the printed

circuit board.

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Power Supply Voltage

0.3 to +7.0

Analog Input Voltage

AIN

0.3 to V

+0.3

Digital Input Voltage

DIN

0.3 to V

+0.3

Storage Temperature

STG

55 to +150

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

Voltage must be fixed

4.75

5.0

5.25

Operating Temperature

+85

Analog Input Voltage

AIN

Gain = 1

3.4

High Level Input Voltage

2.2

Low Level Input Voltage

All Digital Input Pins

0.8

MCK Frequency

MCK

0.01%

4096

+0.01%

kHz

BCLK Frequency

BCLK

256

4096

kHz

Sync Pulse Frequency

SYNC

XSYNC, RSYNC

kHz

Clock Duty Ratio

CLK

MCK, BCLK

Digital Input Rise Time

Digital Input Fall Time

All Digital Input Pins

MCK to BCLK Phase
Difference

MCK, BCLK

BCLK to XSYNC

Transmit Sync Pulse Setting
Time

XSYNC to BCLK

BCLK to RSYNC

Receive Sync Pulse Setting
Time

RSYNC to BCLK

Sync Pulse Width

XSYNC, RSYNC

1 BCLK

100

DIN Set-up Time

DIN

DIN Hold Time

DIN

Pull-up Resistor, DOUT

0.5

DOUT

Digital Output Load

C1A, C2A, C3A,C1B, C2B, C3B

Bypass Capacitor for SGC

SG to AG

0.1

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ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

= 4.75 to 5.25 V, Ta = 40 to +85

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

DD1

2CH Operating Mode, No Signal

PDN = "1", CPD1 = CPD2 = "1"

14.0

18.0

DD2

1CH Operating Mode, No Signal

PDN = "1", CPD1 = "1", CPD2 =

"0" or PDN = "1", CPD1 = "0",

CPD2 = "1"

8.0

11.0

DD3

Power Saving Mode,

PDN = "1", CPD1 = CPD2 = "0"

1.8

2.5

Power Supply Current

DD4

Power Down Mode,

PDN = "0"

0.01

0.05

High Level Input Leakage
Current

All Digital Input Pins

= V

2.0

Low Level Input Leakage
Current

All Digital Input Pins

= 0 V

0.5

DOUT, Pull-up = 0.5 k

0.2

0.4

Digital Output Low Voltage

C1A, C2A, C3A, C1B, C2B, C3B

= 0.4 mA

0.2

0.4

C1A, C2A, C3A, C1B, C2B, C3B

= 0.4 mA

2.5

Digital Output High Voltage

C1A, C2A, C3A, C1B, C2B, C3B

= 50

0.5

Digital Output Leakage
Current

DOUT High Impedance State

Input Capacitance

Analog Interface Characteristics

= 4.75 to 5.25 V, Ta = 40 to +85

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

SGC Rise Time

SGC

SG to AG 0.1

Rise time to 90% of max. level

Transmit Analog Interface Characteristics

= 4.75 to 5.25 V, Ta = 40 to +85

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Input Resistance

INX

AIN1, AIN2

Output Load Resistance

LGX

Output Load Capacitance

LGX

Output Amplitude

OGX

GSX1, GSX2

with respect to SG

1.13

Offset Voltage

OSGX

Gain = 1

*1 0.27 dBm (600

) = 3.17 dBm0 (

-law) = 2.26 V

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Receive Analog Interface Characteristics

= 4.75 to 5.25 V, Ta = 40 to +85

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Output Load Resistance

LAO

AOUT1, AOUT2 (each)

with respect to SG

0.6

Output Load Capacitance

LAO

AOUT1, AOUT2

Output Amplitude

OAO

AOUT1, AOUT2, R

LAO

= 0.6 k

with respect to SG

1.7

Offset Voltage

OSAO

AOUT1, AOUT2

with respect to SG

100

AC Characteristics

= 4.75 to 5.25 V, Ta = 40 to +85

Condition

Parameter

Symbol

Freq.

(Hz)

Level

(dBm0)

Min.

Typ.

Max.

Unit

Loss T1

Loss T2

300

0.15

0.20

Loss T3

1020

Reference

Loss T4

3000

0.15

0.02

0.20

Loss T5

3300

0.15

0.1

0.80

Transmit
Frequency Response

Loss T6

3400

GSXn to DOUT

(Attenuation)

0.6

0.80

Loss R1

100

0.15

0.04

0.2

Loss R2

1020

Reference

Loss R3

3000

0.15

0.07

0.2

Loss R4

3300

0.15

0.2

0.8

Receive
Frequency Response

Loss R5

3400

DIN to AOUTn

(Attenuation)

0.6

0.8

SDT1

SDT2

SDT3

SDT4

Transmit
Signal to Distortion
Ratio

SDT5

1020

GSXn to DOUT

SDR1

SDR2

SDR3

SDR4

Receive
Signal to Distortion
Ratio

SDR5

1020

DIN to AOUTn

GTT1

0.2

0.02

0.2

GTT2

Reference

GTT3

0.2

0.06

0.2

GTT4

0.6

0.4

0.6

Transmit
Gain Tracking

GTT5

1020

GSXn to DOUT

1.2

0.4

1.2

GTR1

0.2

GTR2

Reference

GTR3

0.2

0.02

0.2

GTR4

0.6

0.1

0.6

Receive
Gain Tracking

GTR5

1020

DIN to AOUTn

1.2

0.2

1.2

NIDLE

AINn = SG *2

AINn to DOUT

Idle Channel Noise

NIDLE

DIN = 0 code *2

DIN to AOUTn

dBrnc0

*2 C-message Filter is used

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AC Characteristics (Continued)

= 4.75 to 5.25 V, Ta = 40 to +85

Condition

Parameter

Symbol

Freq.

(Hz)

Level

(dBm0)

Min.

Typ.

Max.

Unit

GSXn to DOUT

= 5 V,

Ta = 25

0.535

0.555

0.574

Absolute Level
(Initial Difference)

DIN to AOUTn

= 5 V,

Ta = 25

0.806

0.835

0.864

Vrms

0.3

Absolute level

(Deviation of

Temperature and
power)

1020

= 4.75 to 5.25 V

Ta = 40 to 85

0.3

Absolute Delay

1020

A to A Mode

BCLK = 2048 kHz

0.58

0.6

500

0.26

0.75

600

0.16

0.35

1000

0.02

0.125

2600

0.05

0.125

Transmit Group Delay

2800

0.07

0.75

500

0.00

0.75

600

0.00

0.35

1000

0.00

0.125

2600

0.09

0.125

Receive Group Delay

2800

0.12

0.75

Trans to Receive

Receive to Trans

Cross Talk
Attenuation

1020

Channel to Channel

Discrimination

DIS

4.6 to 72k

0 to 4 kHz

Out of Band Spurious

OBS

300 to

3.4k

4.6 kHz to 1000 kHz

37.5

SFD

Signal Frequency
Distortion

SFD

1020

0 to 4 kHz

dBm0

IMD

Intermoduration

Distortion

IMD

fa = 470
fb = 320

2 fa - fb

dBm0

PSR

0 to 4k

PSR

4 to 50k

PSR

0 to 4k

Power Supply Noise
Rejection Ratio

PSR

4 to 50k

100

mVrms

100

XD1

100

XD2

DOUT

Pull-up resister = 0.5 k

= 50 pF and 1 LSTTL

100

Digital Output
Delay Time

PDC

C1A, C2A, C3A, C1B, C2B, C3B

= 50 pF and 1 LSTTL

1000

DOUT Operation

Delay Time

DDO

Time of operation start after power on

AOUT Signal Output
Delay Time

DAO

Time of base band signal output start

after power on

*3 Minimum value of the group delay distortion
*4 The measurement under idle channel noise

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TIMING DIAGRAM

Figure 1 Transmit Side Timing Diagram

Figure 2 Receive Side Timing Diagram

Figure 3 Transmit Side Bit Configuration

Figure 4 Receive Side Bit Configuration

MCK

XD1

MSD

XD2

BCLK

XSYNC

DOUT

MSD

MCK

BCLK

RSYNC

DIN

3
A

EPD

2
A

1
A

3
B

EPD

2
B

1
B

CH1 PCM DATA ECHO bits

CH2 PCM DATA ECHO bits

BCLK

XSYNC

DOUT

C3A

C2A

C1A

C3B

C2B

C1B

CH1 PCM DATA

CH1 power down control bit

CH2 PCM DATA

Latch Data

CH2 power down control bit

Latch Data

BCLK

RSYNC

DIN

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MSD

CPD1

C3A

C2A

C1A

MSD

CPD2

C3B

C2B

C1B

MSD

CPD1

C3A

C2A

C1A

MSD

CPD2

C3B

C2B

C1B

CH1

I
N

T D

ontrol

DAT

CH2

I
N

T D

ontrol

DAT

CH1

I
N

T D

ontrol

DAT

CH2

I
N

T D

ontrol

DAT

MSD

EPD1

EC3A

EC2A

EC1A

MSD

EPD2

EC3B

EC2B

EC1B

MSD

EPD1

EC3A

EC2A

EC1A

MSD

EPD2

EC3B

EC2B

EC1B

CH1

OUT

ECHO

BIT

CH2

OUT

ECHO

BIT

CH2

OUT

ECHO

BIT

CH1

OUT

ECHO

BIT

PDC

BCLK

RSY

DIN

DOUT

A, C2

A, C3

B, C1

Figur

e
5

Contr

l Bit T

i
ming a

nd Ec

ho Ba

c
k
T

i
ming

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FUNCTIONAL DESCRIPTION

Pin Functional Description

AIN1, AIN2, GSX1, GSX2
AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp
and are used to adjust the level, as shown below.
If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down
mode, the GSX1 and GSX2 outputs are at AG voltage.
In the case of the analog input 2.26 Vpp at GSX pin with digital output +3.17 dBm0 (

-law).

AOUT1, AOUT2
AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2.
The output signal has an amplitude of 3.4Vpp above and below the signal ground voltage (SG).When the digital
signal of +3.17 dBm0 is input to DIN, it can drive a load of 600

or more.

During power saving or power down mode, these outputs are at a high impedance.

Power supply for +5 V.
Connect a bypass capacitor of 0.1

F with excellent high frequency characteristics between this pin and the AG

pin.
Although V

pin 1 and V

pin 15 are connected internally, these pins must be connected on the printed circuit

board.

CH1 Gain
Gain = R2/R1

R1: Variable
R2

20 k

1/ (2

3.14

R1)

CH2 Gain

Gain = R4/R3

R3: Variable
R4

20 k

1/ (2

3.14

R3)

CH1
Analog
Input

GSX1

AIN1

CH2
Analog
Input

GSX2

AIN2

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AG
Ground for the analog signal circuits.

DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed
circuit board to make a common analog ground.

SGC
Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1

F capacitor

with excellent high frequency characteristics between the AG pin and the SGC pin.
During power down mode, this outputs are at the voltage level of AG with about 50 k

impedance.

MCK
Master clock input.
The frequency must be 4.096 MHz.

BCLK
Shift clock signal input for the DIN and DOUT signals.
The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the
MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK.

RSYNC
Receive synchronizing signal input.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in
phase with the MCK (generated from the same clock source as MCK).

XSYNC
Transmit synchronizing signal input.
The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal.
This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase
with the MCK (generated from the same clock source as MCK).

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DIN
DIN is a data input pin.
The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The
analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2
pin.
The 28 bit signal structure is shown in Figure 4. It consists of voice band PCM signals (8 bits each), the general-
purpose latch signal (6 bits total), the power down control signal (1 bit per channel) and empty bits (4 bits). The
signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits.
The start of the PCM data (Channel 1's MSD) is identified at the rising edge of RSYNC.
The general purpose latch signal (C3A, C2A, C1A, C3B, C2B, C1B) are output from six latch output pins.
When the CPD1 (bit of DIN) = "0", Channel 1 block is in a power down state. When the CPD2 (bit of DIN) = "0",
Channel 2 block is in a power down state.

DOUT
DOUT is a data output pin.
The signal consist of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the echo bit (6
bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The output cording format
follows ITU-T recommendation on coding law.
The output signal is output from Channel 1's MSD bit in a sequential order, synchronizing with the rising edge of
the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing
between BCLK and XSYNC.
This pin is in a high impedance state during power down state.
A pull-up resistor must be connected to this pin because it is an open drain output.

Table 1 The Output Cording Format

PCMIN/PCMOUT

-law

INPUT/OUTPUT

Level

MSD

+ Full scale

Full scale

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C1A, C2A, C3A, C1B, C2B, C3B
General-purpose latched output signal.
C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing.
These outputs can drive a LSTTL/CMOS device without external resistor.

PDN
Power down control signal.
When PDN is at logic "0" level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all
internal latches are in initial state (logic "0" level).

TEST1, TEST2, TEST3, TEST4, TEST5, TEST6
These pins are used for device test.
These device test pin must be connected to the AG pin.

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Table 2 Condition of DOUT by the Power Control

PDN

CPD1 CPD2

CH1 PCM Data

CH2 PCM Data

CH1 Echo Bit

CH2 Echo Bit

0/1

11111111

Operate

11111111

Operate

Latched Data

Table 3 Condition of the Latched Output by the Power Control

PDN

CPD1 CPD2

LIN

C1A, C2A, C3A

C1B, C2B, C3B

0/1

Latched Data

0/1

Table 4 Condition of the Analog Output by the Power Control

PDN

CPD1 CPD2

GSX1

GSX2

AOUT1

AOUT2

SGC

0/1

High

Impedance

High

Impedance

High

Impedance

High

Impedance

High

Impedance

High

Impedance

High

Impedance

High

Impedance

Operate

High

Impedance

Operate

High

Impedance

Operate

High

Impedance

Operate

High

Impedance

Operate

*5 The voltage level of AG with about 50 k

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APPLICATION CIRCUITS

L7022

IN1

GSX

OUT

IN2

GSX

OUT

SGC

DOUT

DIN

MCK

BCLK

RSY

PDN

ltiplex

signal o

tpu

ltiplex

signal i

npu

ster

clo

ck &

i
t c

l
o
ck

inpu

ster

clo

ck &

i
t c

l
o
ck

inpu

r
d

t
r
o

0: pow

r dow

/1: o

era

t
ion

Latc

h out

put

hanne

l 1

anal

og i

nput

hanne

l 1

anal

og o

tput

hanne

l 2

anal

og i

nput

hanne

l 2

anal

og o

tput

0 V

+5 V

1 k

+5 V

0.1

F +

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RECOMMENDATIONS FOR ACTUAL DESIGN

To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics
for the power supply and keep them as close as possible to the device pins.

Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low
impedance.

Unless unavoidable, use short lead type socket.

When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as
power supply transformers surround the device.

Keep the voltage on the V

pin not lower than 0.3 V even instantaneously to avoid latch-up phenomenon when

turning the power on.

Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous
operation and the degradation of the characteristics of these device.

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PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).

SSOP30-P-56-0.65-K

Mirror finish

Package material

Epoxy resin

Lead frame material

42 alloy

Pin treatment

Solder plating (

5µm)

Package weight (g)

0.19 TYP.

Rev. No./Last Revised

5/Dec. 5, 1996

(Unit: mm)

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NOTICE

The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.

The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML7022-01MB