OKI Semiconductor
PEDL87V2104DIGEST-01
Issue Date: Jan. 20, 2003
ML87V2104
Preliminary
Video Signal Noise Reduction and Field Rate Conversion IC with a Built-in 4M Bit Field Memory
1/13
GENERAL DESCRIPTION
The ML87V2104 consists of a 3-port type (1 input port and 2 output ports) 4.4 Mbit (960
288 16bits) field
memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise.
Noise reduction auto mode can be set by detecting the noise in the vertical blanking period and by setting the noise
reduction setting value according to the detected noise state. Moreover, an internal memory controller controls
flicker-free conversion that doubles the vertical and horizontal direction frequencies.
FEATURES
Memory capacity :
4.4 Mbit (960
288 16 bits) 1 unit
Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656):
18/36 MHz (at 960 effective horizontal pixels)
Maximum output operating frequencies (normal/flicker-free):
18/36 MHz (at 960 effective horizontal pixels)
Power supply voltage :
3.3 V 0.3 V
Input pin:
TTL-5V tolerant (5 V withstand voltage)
Input/output pins:
Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage)
Output pin:
LVCMOS (3.3 V)
Input data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2): Input 16-bit mode
YCbCr (8 bits (YCbCr)) (4:2:2):
Input 8-bit mode
ITU-R656 (8 bits (YCbCr)):
Input ITU-R BT.656 mode
Output data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
Serial bus:
I
2
C-bus interface: (400 kHz, 100 kHz)
Memory controller functions:
Input:
Compliant to 525/60 Hz 2:1, 625/50 Hz 2:1
Output:
625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1
Sync generator functions:
Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1, 625/100 Hz 2:1, 525/120 Hz 2:1.
Field-recursive type noise reduction function:
Noise detection and noise subtraction type (with horizontal motion compensation)
Auto mode noise reduction (noise is detected during vertical blanking period)
Package:
100 pin QFP (QFP100-P-1420-0.65-BK4)
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
2/13
BLOCK DIAGRAM
3
port
s
Field
M
e
mory
4.4
M
b
its
(960
2
88
16
)
R_
Po
rt2
R_
Po
rt1
O
u
tput Sy
nc.
G
enerator
Me
m
o
r
y
C
ontrol
l
er
I
2
C-b
u
s
I/F
R
egist
er
OHS
ICL
K
IVS
OVS
OCL
K
SCL SD
A
x1
6
x1
6
SLA1 SLA2
C
ontrol Signa
l
YO
0
-
7
IHS
INT
RE
S
E
T
x1
6
DNR
IVS_dly
IH
S_dly
HREF
MODE
0
-
2
SSG
TE
S
T
1
-
5
CO0
-
7
YI
0
-
7
CI0
-
7
x1
6
Input
Proc
es
s
Bloc
k
+
3D
N
R
x1
6
W_
P
o
r
t
IF
CL
KO
MTE
S
T1
-
7
OE
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
3/13
PIN CONFIGURATION (TOP VIEW)
TEST1
TEST2
TEST3
TEST4
TEST5
96
95
94
93
92
91
89
88
87
86
85
84
83
82
81
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
90
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
ML87V2104
(QFP100-P-1420-0.65-BK4)
V
SS
V
DD
V
DD
V
DD
CO7
CO6
CO5
CO4
OCLK
V
SS
YO4
YO3
YO2
YO1
YO0
YO6
YO5
YO7
OE
V
DD
CI3
CI2
CI1
CI0
ICLK
V
SS
OV
S
OHS
V
DD
N.C.
V
SS
HREF
N.C.
N.C.
IH
S
IV
S
CO3
CO2
CO1
CO0
IN
T
CI7
CI6
CI5
CI4
YI3
YI2
YI1
YI0
YI7
YI6
YI5
YI4
V
DD
V
SS
N.C.
SSG
MOD
E
1
SLA1
SLA2
MOD
E
0
N.C.
MOD
E
2
V
DD
V
SS
SDA
SCL
RESET
V
DD
29
28
27
26
25
30
47
48
49
50
75
76
77
78
79
80
100
99
98
97
V
SS
N.C.
N.C.
V
SS
V
DD
CL
KO
V
SS
V
SS
DN
R
M
T
EST6
M
T
EST7
N.C.
N.C.
N.C.
N.C.
M
T
EST5
M
T
EST4
M
T
EST1
M
T
EST3
M
T
EST2
N.C.
N.C.
N.C.
N.C.
N.C.
V
DD
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
4/13
PIN DESCRIPTIONS
No.
Symbol
I/O
Pad Remarks
Pin Description
1 V
DD
--
Power supply 3.3 V
2 N.C. --
Unused
pin
3 N.C. --
Unused
pin
4 V
SS
--
Ground
5 SDA I/O
Schmitt(IN)/
OpenDrain(OUT)
I
2
C-bus data pin
6 SCL I Schmitt I
2
C-bus clock pin
7
SLA1
I
pull-down 50k
Slave address setting pin
8
SLA2
I
pull-down 50k
Slave address setting pin
9
YI7
I
Luminance signal input pin bit 7 (MSB)
10
YI6
I
Luminance signal input pin bit 6
11
YI5
I
Luminance signal input pin bit 5
12
YI4
I
Luminance signal input pin bit 4
13
YI3
I
Luminance signal input pin bit 3
14
YI2
I
Luminance signal input pin bit 2
15
YI1
I
Luminance signal input pin bit 1
16
YI0
I
Luminance signal input pin bit 0 (LSB)
17 V
DD
--
Power supply 3.3 V
18
ICLK
I
Input system clock pin
19 V
SS
--
Ground
20
CI7
I
Chrominance signal input pin bit 7 (MSB)
21
CI6
I
Chrominance signal input pin bit 6
22
CI5
I
Chrominance signal input pin bit 5
23
CI4
I
Chrominance signal input pin bit 4
24
CI3
I
Chrominance signal input pin bit 3
25
CI2
I
Chrominance signal input pin bit 2
26
CI1
I
Chrominance signal input pin bit 1
27
CI0
I
Chrominance signal input pin bit 0 (LSB)
28 N.C. --
Unused
pin
29 N.C. --
Unused
pin
30 V
DD
--
Power supply 3.3 V
31 V
SS
--
Ground
32 IVS I/O
Schmitt(IN)
pull-down 50k
Input vertical sync signal input/output pin
33 IHS I/O
Schmitt(IN)
pull-down 50k
Input horizontal sync signal input/output pin
34
MODE0
I
pull-down 50k
Mode setting pin bit 0
35
MODE1
I
pull-down 50k
Mode setting pin bit 1
36 N.C. --
Unused
pin
37
MODE2
I
pull-down 50k
Mode setting pin bit 2
38
CLKO
O
Clock output (I
2
C-bus control possible)
39 V
DD
--
Power supply 3.3 V
40 V
SS
--
Ground
41 N.C. --
Unused
pin
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
5/13
No.
Symbol
I/O
Pad Remarks
Pin Description
42 V
DD
--
Power supply 3.3 V
43 DNR I pull-down
50k
Noise reduction output mode setting pin
0: Normal operation
1: Direct noise reduction mode
44 N.C. --
Unused
pin
45
SSG
I
pull-down 50k
Internally generated sync signal mode setting pin
46 INT I
pull-down
50k
Output system sync signal input/output select setting pin
0: OVS, OHS input mode
1: OVS, OHS internally generated output mode
47 OHS I/O
Schmitt(IN)
pull-down 50k
Output system horizontal sync signal input/output pin
48 OVS I/O
Schmitt(IN)
pull-down 50k
Output system vertical sync signal input/output pin
49
HREF
O
Data output horizontal reference signal output pin
50 V
SS
--
Ground
51 V
DD
--
Power supply 3.3 V
52
CO0
O
Chrominance signal output pin bit 0 (LSB)
53
CO1
O
Chrominance signal output pin bit 1
54
CO2
O
Chrominance signal output pin bit 2
55
CO3
O
Chrominance signal output pin bit 3
56 V
SS
--
Ground
57
CO4
O
Chrominance signal output pin bit 4
58
CO5
O
Chrominance signal output pin bit 5
59
CO6
O
Chrominance signal output pin bit 6
60
CO7
O
Chrominance signal output pin bit 7(MSB)
61 V
DD
--
Ground
62
OCLK
I
Output system clock pin
63 V
SS
--
Ground
64
YO0
O
Luminance signal output pin bit 0 (LSB)
65
YO1
O
Luminance signal output pin bit 1
66
YO2
O
Luminance signal output pin bit 2
67
YO3
O
Luminance signal output pin bit 3
68
VDD
--
Power supply 3.3 V
69
YO4
O
Luminance signal output pin bit 4
70
YO5
O
Luminance signal output pin bit 5
71
YO6
O
Luminance signal output pin bit 6
72
YO7
O
Luminance signal output pin bit 7 (MSB)
73 V
SS
--
Ground
74 N.C. --
Unused
pin
75 N.C. --
Unused
pin
76 N.C. --
Unused
pin
77 N.C. --
Unused
pin
78 N.C. --
Unused
pin
79
RESET
I
System reset input pin (0 active)
0: System reset 1: Normal operation
Apply ICLK cycle one and more time during "0" level after VDD
voltage has reached the specified level in System reset operation.
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
6/13
No.
Symbol
I/O
Pad Remarks
Pin Description
80 V
DD
--
Power supply 3.3 V
81 V
SS
--
Ground
82
MTEST7
I
pull-down 50k
Memory test input pin bit 7 (1: test mode)
83
MTEST6
I
pull-down 50k
Memory test input pin bit 6 (1: test mode)
84 OE I
pull-down
50k
Output enable input pin (normally set to 1)
0: YO[7:0], CO[7:0] disable (Hi-z)
1: YO[7:0], CO[7:0] enable (drive)
Equivalent operation to setting fixed to 1 in RESET=0 or DNR=1
85 N.C. --
Unused
pin
86 N.C. --
Unused
pin
87 N.C. --
Unused
pin
88 N.C. --
Unused
pin
89
TEST5
I
pull-down 50k
Test input pin bit 5 (1: test mode)
90 V
DD
--
Power supply 3.3 V
91
TEST4
I
pull-down 50k
Test input pin bit 4 (1: test mode)
92
TEST3
I
pull-down 50k
Test input pin bit 3 (1: test mode)
93
TEST2
I
pull-down 50k
Test input pin bit 2 (1: test mode)
94
TEST1
I
pull-down 50k
Test input pin bit 1 (1: test mode)
95
MTEST5
I
pull-down 50k
Memory test input pin bit 5 (1: test mode)
96
MTEST4
I
pull-down 50k
Memory test input pin bit 4 (1: test mode)
97
MTEST3
I
pull-down 50k
Memory test input pin bit 3 (1: test mode)
98
MTEST2
I
pull-down 50k
Memory test input pin bit 2 (1: test mode)
99
MTEST1
I
pull-down 50k
Memory test input pin bit 1 (1: test mode)
100 V
SS
--
Ground
Notes: In 8-bit YcbCr and ITU-R BT. 656 mode, CI0-7 pin should be connected to the Vss level.
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
7/13
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol
Condition Rating Unit
Power supply voltage
V
DD
Ta = 25C
0.3 to 4.6
V
Input pin voltage
V
I
Ta = 25C
0.3 to 7.0
V
Output pin short-circuit current
I
OS
Ta = 25C
50
mA
Power dissipation
P
D
Ta = 25C
1
W
Operating temperature
T
opr
--
0 to 70
C
Storage temperature
T
stg
--
50 to 150
C
Recommended Operating Conditions
Parameter Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
V
DD
3.0 3.3 3.6
V
Power supply voltage
V
SS
0 0
0
V
Operating temperature
Ta
0
--
70
C
Pin Capacitance
(V
CC
= 3.3 V 0.3 V, f = 1 MHz, Ta = 25C)
Parameter Symbol
Min.
Max. Unit
Input capacitance
C
i
--
10 pF
Input/output capacitance
(IVS, IHS, OVS, OHS)
C
io1
--
10 pF
Input/output capacitance (SDA)
C
io2
--
10 pF
Output capacitance
C
o
--
10 pF
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
8/13
DC Characteristics
(Ta = 0 to 70C)
Parameter Symbol
Condition
Min.
Max.
Unit
H level input voltage
V
IH
-- 2.0
5.5
V
L level input voltage
V
IL
--
0.3
0.8
V
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, OVS, OHS)
V
t+
-- --
2.0
V
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, OVS, OHS)
V
t
-- 0.8
--
V
Hysteresis voltage width
V
h
--
0.1
--
V
H level input current (pull-down)
I
IH
50
k
Pull Down
20
200
A
Input leakage current
I
IL
TTL
10
10
A
H level output voltage (other than SDA)
V
OH
I
OH
= 4 mA
2.2
V
DD
V
L level output voltage (other than SDA)
V
OL
I
OL
= 4 mA
0
0.4
V
L level output voltage (N-Ch.OD)
(SDA)
V
OOL
I
OL
= 4 mA
0
0.4
V
Output leakage current
I
OL
0
V
out
V
DD
Output is disabled
10 10
A
Supply current (during operation)
I
DD1
ICLK: 36 MHz
OCLK: 36 MHz
Output open
-- 100 mA
Supply current (during standby)
I
DD2
Input pin = V
IL
--
10
mA
AC Characteristics
(Ta = 0 to 70C)
Parameter Symbol
Condition
Min.
Max.
Unit
ICLK clock cycle time
t
ICLK
Input 16-bit mode
54
--
Ns
ICLK clock cycle time
t
ICLK
Input 8-bit mode
27
--
Ns
ICLK clock duty ratio
dt
ICLK
-- 45
55
%
ICLK system input set-up time
t
IISU
-- 5
--
ns
ICLK system input hold time
t
IIH
-- 3
--
ns
ICLK system output delay time
t
IOD
C
L
= 20 pF
5
22
ns
OCLK clock cycle time
t
OCLK
-- 27
--
ns
OCLK clock duty ratio
dt
OCLK
-- 45
55
%
OCLK system input set-up time
t
OISU
-- 5
--
ns
OCLK system input hold time
t
OIH
-- 3
--
ns
OCLK system output delay time
t
OOD
C
L
= 20 pF
5
22
ns
C
L
= 20 pF (OCLK output)
5
22
C
L
= 20 pF (IICLK output)
6
25
CLKO delay time
t
CKD
C
L
= 20 pF (ICLK output)
6
22
ns
Data through time
t
DIDO
C
L
= 20 pF
3
20
ns
Notes: 1. Input signal reference levels for the parameter measurement are V
IH
= 3.0 V and V
IL
= 0 V.
Output reference levels are V
OH
= 1.5 V and V
OL
= 1.5 V.
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
9/13
Notes: 2. On power-up, the device is designed to begin proper operation after at least 100
s after V
CC
has
stabilized to a value within the range of recommended operating conditions. After this 100
s
stabilization interval, a minimum of 1-field dummy write operations and read operations must be
performed.
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
10/13
Application Example1
Mode setting: ALL Pin Open
Slave address: 1011100
Input format: 16bit YcbCr (Register setting: DISEL=0,R656=0)
NR-FIFO
ML87V2104
RGB CONVERTER
DEFLECTION
/
SCAN
CONVERTER
/
MPEG
ENCODER
DEGITAL
VIDEO
DECODER
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
OVS
OCLK
OHS
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
ICLK
I
2
C-bus
MATER
CONTROLLER
SDA
SCL
VDD
GND
VIDEO
IN
3.3V
HREF
CX
CLKO
OE
4,19,31,
40,50,56,
63,73,81,
100
62
15
16
13
14
11
12
9
10
5
6
1,17,30,
39,51,61
,
68,80,90
84
32
33
26
27
18
24
25
22
23
20
21
72
71
49
48
53
52
55
54
58
57
60
59
65
64
67
66
70
69
47
38
79
System
Reset
CLK
RESET
DATA
OUT
RESET
IVS
IHS
Application Example2
Mode setting: DNR=1(Direct Noise Reduction Mode), Others Pin:OPEN
Slave address: 1011100
Input format: ITU-R BT.656(Register setting: DISEL=0,R656=1)
Output format: ITU-R BT.656(Register setting: DOSEL=1)
NR-FIFO
ML87V2104
RGB CONVERTER
DEFLECTION
/
SCAN
CONVERTER
/
MPEG
ENCODER
DEGITAL
VIDEO
DECODER
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
OPEN
OPEN
ICLK
I
2
C-bus
MATER
CONTROLLER
SDA
SCL
VDD
GND
VIDEO
IN
3.3V
OE
4,19,31,
40,50,56,
63,73,81,
100
62
15
16
13
14
11
12
9
10
5
6
1,17,30,
39,51,61
,
68,80,90
84
32
33
26
27
18
24
25
22
23
20
21
72
71
49
48
53
52
55
54
58
57
60
59
65
64
67
66
70
69
47
38
79
System
Reset
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
CLK
RESET
DNR
43
OCLK
ITU-R BT.656
Format
ITU-R BT.656
Format
DATA
OUT
RESET
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
11/13
PACKAGE DIMENSIONS
(Unit: mm)
QFP100-P-1420-0.65-BK4
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
5m)
Package weight (g)
1.54 TYP.
5
Rev. No./Last Revised
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The QFP is a surface mount type package, which is very susceptible to heat in reflow mounting and
humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible
sales person on the product name, package name, pin number, package code and desired mounting
conditions (reflow method, temperature and times).
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
12/13
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
Description
PEDL87V2104DIGEST-01 Jan.20.
2003
Preliminary edition 1
PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
13/13
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
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