PEDL9041-03
1Semiconductor
This version: Mar. 2001
Previous version: Dec. 1999
ML9041-xxA/xxB
Preliminary
DOT MATRIX LCD CONTROLLER DRIVER
1/60
GENERAL DESCRIPTION
The ML9041 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
Easy interfacing with 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller/driver for a small (5
7 dots) or large (5
10 dots) font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Built-in character generation ROM capable of generating 160 small characters (5
7 dots) or 32 large
characters (5
10 dots)
Creation of character patterns by programming: up to 8 small character patterns (5
8 dots) or up to 4 large
character patterns (5
11 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties: 1/9 duty (1 line: 5
7 dots + cursor + arbitrator), 1/12 duty (1 line: 5
10 dots +
cursor + arbitrator), or 1/17 duty (2 lines: 5
7 dots + cursor + arbitrator)
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
Equipped with a 100-dot arbitrator
Display shifting on each line
Built-in contrast control circuit
Built-in voltage multiplier circuit
Chip (Gold Bump)
Product name: ML9041-xxA/xxB CVWA
xxA: With dummy bumps on both sides of the chip
xxB: Without dummy bumps on both sides of the chip
*xx indicates a code number.
*01A and 01B are general code numbers.
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
2/60
BLOCK DIAGRAM
V
DD
GN
D
OS
C
1
OS
C
R
OS
C
2
RS
1
RS
0
R/
W
E
C
S
P
/S
SH
T
SI
SO
DB
0
to
D
B
3
4
DB
4
to
D
B
7
4
T
1
T
2
T
3
V
1
V
2
V
3B
V
3
A
V
4
V
5
V
5I
N
Tim
i
n
g
ge
n
e
r
a
t
o
r
8
I/
O
bu
f
f
er
8
In
s
t
r
u
c
t
i
o
n
de
c
o
d
e
r
(I
D
)
Parallel-
serial
converter
7
8
8
8
Dat
a
re
gis
t
e
r
(DR)
5
CO
M
1
SEG
1
CO
M
17
Te
st
ci
rcu
i
t
LC
D
b
i
as
vo
l
t
a
g
e
di
v
i
d
i
n
g
ci
rcu
i
t
5
8
Bu
s
y
fl
a
g
(B
F
)
Ex
pa
n
s
i
o
n
in
st
ruc
t
io
n
re
gis
t
e
r
(E
R
)
Vol
t
a
g
e
m
u
ltip
li
e
r
ci
rc
u
i
t
Ad
dr
es
s
co
u
n
t
e
r
(ADC)
Ex
pa
n
s
i
o
n
in
st
ruc
t
io
n
de
c
o
d
e
r
(E
D)
Cha
r
ac
t
e
r
ge
n
e
r
a
t
o
r
RA
M
(CG R
A
M
)
8
8
Di
s
p
l
a
y
da
t
a
RA
M
(DD RA
M
)
A
r
bi
t
r
at
o
r
RA
M
(
AB RA
M
)
Cur
s
or
b
lin
k
co
n
t
ro
ll
e
r
5
5
CSR
17
-
b
it
sh
i
f
t
re
gis
t
e
r
Com
m
o
n
s
i
g
nal
dr
i
v
e
r
100-bit shift register
100-bit latch
Segment Signal - driver
SEG
10
0
SSR
BEB
V
CC
V
C
V
IN
Cha
r
ac
t
e
r
ge
n
e
r
a
t
o
r
RO
M
(CG R
O
M
)
In
s
t
r
u
c
t
i
o
n
re
gis
t
e
r
(I
R
)
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
3/60
I/O CIRCUITS
V
DD
P
N
Applied to pins SSR, CSR,
P
/S, and BEB
V
DD
P
N
Applied to pins T
1
, T
2
, and T
3
V
DD
P
N
V
DD
Applied to pins R/
W
, RS
1
, and RS
0
At serial I/F
At parallel I/F
At serial I/F
At parallel I/F
Applied to pin SI
Applied to pin E
Applied to pin
SHT
Applied to pin
CS
: 1 (
CS
= 0)
: 0 (
CS
= 1)
: 0
At serial I/F
At parallel I/F
: 1 (
CS
= 1)
: 0 (
CS
= 0)
: 1
: 0
: 1
At serial I/F
At parallel I/F
: 0
: 1
V
DD
P
V
DD
P
N
V
DD
P
N
Applied to pins DB
0
to DB
7
Output Enable signal
V
DD
P
P
V
DD
N
Applied to pin SO
Output Enable signal
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
4/60
PIN DESCRIPTIONS
Symbol
Description
R/
W
The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel I/F
Mode.
This pin should be open in the Serial l/F Mode.
RS
0
, RS
1
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
This pin should be open in the Serial I/F Mode.
E
The input pin for data input/output between the CPU and the ML9041 and for
activating instructions in the Parallel l/F Mode.
This pin should be open in the Serial l/F Mode.
DB
0
to DB
3
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9041 in the Parallel l/F Mode. The pins are not used for the 4-bit interface and
serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
DB
4
to DB
7
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9041 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
OSC
1
OSC
2
OSC
R
The clock oscillation pins required for LCD drive signals and the operation of the
ML9041 by instructions sent from the CPU.
To input external clock, the OSC
1
pin should be used. The OSC
R
and the OSC
2
pins
should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC
1
and OSC
2
pins. The OSC
R
pin should be open.
To start oscillation with an internal resistor, the OSC
2
and OSC
R
pins should be
short-circuited outside the ML9041. The OSC
1
pin should be open.
COM
1
to COM
17
The LCD common signal output pins.
For 1/9 duty, non-selectable voltage waveforms are output via COM
10
to COM
17
. For
1/12 duty, non-selectable voltage waveforms are output via COM
13
to COM
17
.
SEG
1
to SEG
100
The LCD segment signal output pins.
RS
1
RS
0
Name of register
H
H
Data register
H
L
Instruction register
L
L
Expansion Instruction register
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
5/60
Symbol
Description
CSR
The input pin to select the transfer direction of the common signal output data.
At 1/n duty, data is transferred from COM1 to COMn when "L" is applied to this pin and
transferred from COMn to COM1 when "H" is applied to this pin.
SSR
The input pin to select the transfer direction of the segment signal output data.
"L": Data transfer from SEG
1
to SEG
100
"H": Data transfer from SEG
100
to SEG
1
V
1
, V
2
, V
3A
, V
3B
, V
4
The pins to output bias voltages to the LCD.
For 1/4 bias : The V
2
and V
3B
pins are shorted.
For 1/5 bias : The V
3A
and V
3B
pins are shorted.
BEB
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage V
MUL
and the multiplied voltage
referenced to V
DD
is output to the V
5IN
pin. The voltage multiplier circuit can be used
only when generating a level lower than GND.
V
IN
The pin to input voltage to the voltage multiplier.
V
5
, V
5IN
The pins to supply the LCD drive voltage.
The LCD drive voltage is supplied to the V
5
pin when the voltage multiplier is not used
(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the
V
5IN
pin should be open.
The LCD drive voltage is supplied to the V
5IN
pin when the voltage multiplier is not used
(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V
5
pin
should be open.
When the voltage multiplier is used (BEB = 1), the V
5
pin should be open (the
multiplied voltage is output to the V
5IN
pin). In this case, the internal contrast adjusting
circuit must be used. Capacitors for the voltage multiplier should be connected
between the V
DD
pin and the V
5IN
pin.
V
C
The pin to connect the positive pin of the capacitor for the voltage multiplier.
V
CC
The pin to connect the negative pin of the capacitor used for the voltage multiplier.
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