OKI Semiconductor
FEDL9228-01
Issue Date: Oct. 20, 2004
ML9228
82-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, Keyscan
1/25
GENERAL DESCRIPTION
The ML9228 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs
of 82-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 246-segment VFD.
ML9228 features a digital dimming function, a 5
6 keyscan circuit.
FEATURES
Driver Supply voltage (V
DISP
)
: 8.0V to 18.5V
Logic Supply voltage (V
DD
)
: 3.3V10%, 5.0V10%
Duplex/Triplex selectable
Applicable VFD tube
: 2 Grids
82 Anodes VFD tube
: 3 Grids
82 Anodes VFD tube
82-segment driver outputs
: I
OH
= 6 mA at V
OH
= V
DISP
0.8 V (SEG1 to 82)
3-grid pre-driver outputs
: I
OL
= 10 mA at V
OL
= 2 V
Built-in digital dimming circuit (10-bit resolution)
Built-in 5
6 keyscan circuit
Built-in oscillation circuit (external R and C)
Built-in Power-On-Reset circuit
Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K) (ML9228 GA)
FEDL9228-01
OKI Semiconductor
ML9228
2/25
BLOCK DIAGRAM
Timing Generator
DUP/
TRI
OSC
Control
Out1-82
82 bit Shift Register
in1-10
Dimming Latch
Out1-10
10 bit Digital
Dimming
POR
CS
CLOCK
DATA I/O
Out1-3
3 bit Shift Register
POR
POR
POR
4H
Out1-82
Segment Latch
3
in1-82
0H
3H
POR
Out1-82
Segment Latch
2
in1-82
0H
2H
POR
Out1-82
Segment Latch
1
in1-82
0H
1H
POR
Mode Select
in1-3
POR
0H
7H
Power On
Reset
V
DD
L-GND
POR
Out1-82
246 to 82 Segment Control
in1-82
in1-82
in1-82
82 Segment Driver
D-GND
V
DISP
3 Grid pre Driver
GRID
2
GRID
3
GRID
1
SEG82
SEG1
5
6 Key Scan Interface
INT
OSCO
COL
1
COL
6
ROW1
ROW5
5H
6H
7H
BLANK
RESET
FEDL9228-01
OKI Semiconductor
ML9228
3/25
PIN CONFIGURATION (TOP VIEW)
NC: No connection
64-pin Plastic QFP
NC : No Connection
108
107
106
105
104
103
SEG
5
5
SEG
5
4
SEG
5
3
SEG
5
2
NC
NC
128
127
126
125
124
123
122
121
120
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
111
11
0
109
NC
NC
SEG
7
3
SEG
7
2
SEG
7
1
SEG
7
0
SEG
6
9
SEG
6
8
SEG
6
7
SEG
6
6
SEG
6
5
SEG
6
4
SEG
6
2
SEG
6
1
SEG
6
0
SEG
5
9
SEG
5
8
SEG
5
7
SEG
5
6
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
NC
SEG
1
2
59
60
61
62
SEG
1
6
63
64
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
SEG74
SEG75
SEG76
SEG78
SEG79
SEG80
SEG81
SEG82
V
DISP
D-GND
VDD
INT
ROW1
ROW2
ROW3
ROW4
ROW5
COL
1
COL
2
COL
3
COL
4
COL
5
COL
6
DUP/
TRI
SEG77
31
32
33
34
35
36
37
38
BLANK
RESET
L-GND
NC
OSC0
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SEG50
NC
NC
SEG51
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG19
72
71
70
69
68
67
66
65
SEG23
SEG22
SEG21
SEG20
SEG18
NC
NC
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
SEG
8
SEG
9
SEG
1
0
SEG
1
1
SEG
1
3
SEG
1
4
SEG
1
5
G
RI
D
3
SEG
6
3
CS
CLOCK
DATA I/O
V
DI
S
P
G
RI
D
1
NC
D-
G
N
D
SEG
1
7
NC
G
RI
D
2
NC
NC
NC
FEDL9228-01
OKI Semiconductor
ML9228
4/25
PIN DESCRIPTIONS
Pin Symbol
Type
Description
12,42 V
DISP
--
High Level Power supply pins
Pin12 and pin42 should be connected externally.
14 V
DD
--
Low Level Power supply pin
13,41 D-GND --
37 L-GND
--
D-GND is ground pins for the VFD driver circuit. L-GND is ground pin for
the logic circuit. Pin13,Pin37 and Pin41 should be connected externally.
3 to 11,
46 to 62,
67 to 100,
105 to 126
SEG1 to 82
O
Segment (anode) signal output pins for a VFD tube
These pins can be directly connected to the VFD tube. External circuit is
not required.
l
OH
6 mA, l
OL
500
43,44,45
GRID
1 to 3
O
Inverted Grid signal output pins
For pre-driver, the external circuit is required.
l
OH
6 mA, l
OL
10 mA
30 CS l
Chip Select input pin
Data input/output operation is valid when this pin is set at a High level.
31 CLOCK l
Serial clock input pin
Data is input and/or output through the DATA l/O pin at the rising edge of
the serial clock.
32 DATA
l/O
l/O
Serial data input/output pin
Data is input to/comes out from the shift register at the rising edge of the
serial clock.
15 INT
O
Interrupt signal output to microcontroller. When any key of key matrix is
pressed or released, key scanning is started. After the completion of the
one cycle, this pin goes to high level and keeps the high level until
keyscan stop mode is selected.
27 DUP/
TRl
l
Duplex/Triplex operation select input pin.
DUP/
TRl
= L(L-GND) : Triplex
DUP/
TRl
= H(VDD) : Duplex
21 to 26
COL
1 to 6
l
Return inputs from the key matrix
These pins are active low. When key matrix are in the inactive sate,
these pins are at high level through the internal pull-up resistors. All the
inputs do not have the chattering absorption function for the keyscans.
16 to 20
ROW1 to 5
O
Key switch scanning outputs
Normally low level is output through these pin. When any switch of key
matrix is depressed or released, key scanning is started and is continued
until keyscan stop mode is selected. When keyscan stop mode is
selected, all outputs of ROW1 to 5 go back to low level.
28
BLANK
I
Display off control input.
BLANK
= L(L-GND) : Display off(SEG1-82 = L)
BLANK
= H(VDD) : Display on
FEDL9228-01
OKI Semiconductor
ML9228
5/25
Pin Symbol
Type
Description
29
RESET
I
The contents of the shift registers and latches are set to "0".
The digital dimming duty cycle is set to "0".
All segment outputs are set to Low level.
Grid1 output is set to Low level. Grid2,3 outputs are set to High level.
All the ROW outputs are set to Low level.
INT output is set to Low level.
33 OSC0
l/O
RC oscillator connecting pins
Oscillation frequency changes with display
pipes to be used.
Please refer to the right figure.
1,2,35,36,
37,38,
40,63,64,
66,65,
101,102,
127,128
NC --
Open
pin
V
DD
OSC0
R
2
C
2
FEDL9228-01
OKI Semiconductor
ML9228
6/25
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Condition
Rating Unit
V
DISP
--
0.3 to +20
Supply Voltage
V
DD
--
0.3 to +6.5
Input Voltage
V
IN
--
0.3 to +6.0
V
Power Dissipation
P
D
Ta = 85 C
590
mW
Storage Temperature
T
STG
--
55 to +150
C
l
O1
SEG1 to 82
10.0 to +2.0
l
O3
GRID
1 to 3
7.0 to +20.0
Output Current
l
O4
ROW1 to 5, DATA I/O
2.0 to +2.0
mA
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol
Condition
Min.
Typ.
Max.
Unit
Driver Supply Voltage
V
DISP
-- 8.0
13.0
18.5
Unit Supply Voltage 5.0 V (Typ)
4.5
5.0
5.5
Logic Supply Voltage
V
DD
Unit Supply Voltage 3.3 V (Typ)
3.0
3.3
3.6
V
VDD = 5.0 V (Typ)
R
2
= 10 k
5%, C
2
= 27
pF
5%
2.6 3.3 4.0
MHz
VDD = 3.3 V (Typ)
Oscillation Frequency
f
OSC
R
2
= 8.2 k
5%, C
2
= 27
pF
5%
2.6 3.3 4.0
MHz
1/3
Duty 211 269 325
VDD=5.0 V (Typ)
R
2
= 10
k
5%
C
2
= 27
pF
5%
1/2
Duty 317 403 488
Hz
1/3
Duty 211 269 325
Frame Frequency
f
FR
VDD=3.3 V (Typ)
R
2
= 8.2
k
5%
C
2
= 27
pF
5%
1/2
Duty 317 403 488
Hz
Operating Temperature
T
OP
-- -40
--
+85
C
FEDL9228-01
OKI Semiconductor
ML9228
7/25
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 40 to +85C, V
DD
= 5.0 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Symbol
Applied
pin Condition
Min.
Max.
Unit
High Level Input Voltage
V
IH
*1)
--
0.7
V
DD
-- V
Low Level Input Voltage
V
IL
*1)
--
--
0.3
V
DD
V
l
IH1
*2)
V
IH
= V
DD
5.0
+5.0
High Level Input Current
l
IH2
*3)
V
IH
= V
DD
50
5.0
A
l
IL1
*2)
V
IL
= 0.0 V
5.0
+5.0
Low Level Input Current
l
IL2
*3)
V
IL
= 0.0 V
120
10
A
V
OH1
SEG1 to 82
l
OH1
= 6 mA
V
DISP
0.8 --
V
OH2
GRID
1 to 3
l
OH3
= 6 mA
V
DISP
0.8 --
l
OH4
= 120
A
V
DD
0.8 --
High Level Output Voltage
V
OH3
*4)
V
DISP
=
9.5V
Output Open
V
DD
0.2 --
V
V
OL1
SEG1 to 82
l
OL1
= 500
A -- 2.0
V
OL2
GRID
1 to 3
l
OL3
= 10 mA
--
2.0
Low Level Output Voltage
V
OL3
*5)
V
DISP
=
9.5V
l
OL4
= 120
A -- 0.8
V
I
DISP
V
DISP
R
2
= 10 k
5%,
C
2
= 27 pF 5%,
no load
-- 500
A
I
DD
V
DD
R
2
= 10 k
5%,
C
2
= 27 pF 5%
-- 5.0
mA
I
SLP1
V
DISP
Sleep
Mode --
5.0
A
Supply Current
I
SLP2
V
DD
Sleep
Mode
--
5.0
A
*1) CS, CLOCK, DATA I/O, DUP/
TRI
,
BLANK
,
RESET
,
COL
1 to 6
*2) CS, CLOCK, DATA I/O, DUP/
TRI
,
BLANK
,
RESET
*3)
COL
1 to 6
*4) DATA I/O, INT
*5) DATA I/O, INT, ROW1 to 5
FEDL9228-01
OKI Semiconductor
ML9228
8/25
DC Characteristics
(Ta = 40 to +85C, V
DD
= 3.3 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Symbol
Applied
pin Condition
Min.
Max.
Unit
High Level Input Voltage
V
IH
*1)
--
0.8
V
DD
-- V
Low Level Input Voltage
V
IL
*1)
--
--
0.2
V
DD
V
l
IH1
*2)
V
IH
= V
DD
5.0
+5.0
High Level Input Current
l
IH2
*3)
V
IH
= V
DD
-40
-5.0
A
l
IL1
*2)
V
IL
= 0.0 V
5.0
+5.0
Low Level Input Current
l
IL2
*3)
V
IL
= 0.0 V
-100
-5.0
A
V
OH1
SEG1 to 82
l
OH1
= 6 mA
V
DISP
0.8 --
V
OH3
GRID
1 to 3
l
OH3
= 6 mA
V
DISP
0.8 --
l
OH4
= 100
A
V
DD
0.4
--
High Level Output Voltage
V
OH3
*4)
V
DISP
=
9.5V
Output Open
V
DD
0.2
--
V
V
OL1
SEG1 to 82
l
OL1
= 500
A -- 2.0
V
OL2
GRID
1 to 3
l
OL3
= 10 mA
--
2.0
Low Level Output Voltage
V
OL3
*5)
V
DISP
=
9.5V
l
OL4
= 100
A -- 0.4
V
I
DISP
V
DISP
R
2
= 8.2 k
5%,
C
2
= 27 pF 5%,
no load
-- 500
A
I
DD
V
DD
R
2
= 8.2 k
5%,
C
2
= 27 pF 5%
-- 4.0
mA
I
SLP1
V
DISP
Sleep
Mode --
5.0
A
Supply Current
I
SLP2
V
DD
Sleep
Mode
--
5.0
A
*1) CS, CLOCK, DATA I/O, DUP/
TRI
,
BLANK
,
RESET
,
COL
1 to 6
*2) CS, CLOCK, DATA I/O, DUP/
TRI
,
BLANK
,
RESET
*3)
COL
1 to 6
*4) DATA I/O, INT
*5) DATA I/O, INT, ROW1 to 5
FEDL9228-01
OKI Semiconductor
ML9228
9/25
AC Characteristics
(Ta = 40 to +85C, V
DD
= 5.0 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Symbol
Condition
Min.
Max.
Unit
Clock Frequency
f
C
-- --
2.0
MHz
Clock Pulse Width
t
CW
-- 200
--
ns
Data Setup Time
t
DS
-- 200
--
ns
Data Hold Time
t
DH
-- 200
--
ns
CS Off Time
t
CSL
R
2
= 10 k
5%, C
2
= 27 pF 5%
20
--
s
CS Setup Time
(CS-Clock)
t
CSS
-- 200
--
ns
CS Hold Time
(Clock-CS)
t
CSH
-- 200
--
ns
DATA Output Delay Time
(Clock-DATA l/O)
t
PD
-- --
1.0
s
t
R
t
R
= 20 to 80%
--
2.0
s
Output Slew Rate Time
t
F
C
L
=100 pF
t
F
= 80 to 20%
--
2.0
s
V
DD
Rise Time
t
PRZ
Mounted in a unit
--
100
s
V
DD
Off Time
t
POF
Mounted in a unit, V
DD
= 0.0 V
5.0
--
ms
CS Wait Time
t
RSOFF
-- 400
--
s
(Ta = 40 to +85C, V
DD
= 3.3 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Symbol
Condition
Min.
Max.
Unit
Clock Frequency
f
C
-- --
1.0
MHz
Clock Pulse Width
t
CW
-- 400
--
ns
Data Setup Time
t
DS
-- 400
--
ns
Data Hold Time
t
DH
-- 400
--
ns
CS Off Time
t
CSL
R
2
= 8.2 k
5%, C
2
= 27 pF 5%
20
--
s
CS Setup Time
(CS-Clock)
t
CSS
-- 400
--
ns
CS Hold Time
(Clock-CS)
t
CSH
-- 400
--
ns
DATA Output Delay Time
(Clock-DATA l/O)
t
PD
-- --
1.0
s
t
R
t
R
= 20 to 80%
--
2.0
s
Output Slew Rate Time
t
F
C
L
=100 pF
t
F
= 80 to 20%
--
2.0
s
V
DD
Rise Time
t
PRZ
Mounted in a unit
--
100
s
V
DD
Off Time
t
POF
Mounted in a unit, V
DD
= 0.0 V
5.0
--
ms
CS Wait Time
t
RSOFF
-- 400
--
s
FEDL9228-01
OKI Semiconductor
ML9228
10/25
TIMING DIAGRAMS
V
DD
= 3.3 V
10%
V
DD
= 5.0 V
10%
V
IH
0.8
V
DD
0.7
V
DD
V
IL
0.2
V
DD
0.3
V
DD
Data Input Timing
Data Output Timing
Power-On Reset Timing
Driver Output Timing
t
POF
t
PRZ
V
DD
CS
t
RSOFF
0.8 V
DD
0.0 V
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CS
CLOCK
DATA I/O
(INPUT)
t
DS
t
DH
t
CSS
1/f
C
t
CW
t
CW
t
CSH
t
CSL
VALID
VALID VALID
VALID
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CS
CLOCK
DATA I/O
(OUTPUT)
t
PD
t
CSS
t
CSH
0.8 V
DISP
0.2 V
DISP
SEG1-82
t
R
t
F
V
IH
V
IL
BLANK
t
R
t
F
GRID
1-3
0.8 V
DISP
0.2 V
DISP
FEDL9228-01
OKI Semiconductor
ML9228
11/25
Keyscan Characteristics
(Ta = 40 to +85C, V
DD
= 5.0 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Condition
Min.
Typ.
Max.
Unit
Keyscan Cycle Time
R
2
= 10 k
5%, C
2
= 27 pF 5%
160
194
246
s
Keyscan Pulse Width
R
2
= 10 k
5%, C
2
= 27 pF 5%
32
39
49
s
(Ta = 40 to +85C, V
DD
= 3.3 V10%, V
DISP
= 8.0 to 18.5 V)
Parameter Condition
Min.
Typ.
Max.
Unit
Keyscan Cycle Time
R
2
= 8.2 k
5%, C
2
= 27 pF 5%
160
194
246
s
Keyscan Pulse Width
R
2
= 8.2 k
5%, C
2
= 27 pF 5%
32
39
49
s
Keyscan Timing
ROW1
ROW5
ROW2
ROW3
ROW4
Keyscan Cycle Time
Keyscan Pulse
Width
FEDL9228-01
OKI Semiconductor
ML9228
12/25
Output Timing (Duplex Operation)
*1 bit time = 4/f
OSC
Solid line: When dimming data is made into 1016/1024
Dotted line: When dimming data is made into 64/1024
Output Timing (Triplex Operation)
*1 bit time = 4/f
OSC
Solid line: When dimming data is made into 1016/1024
Dotted line: When dimming data is made into 64/1024
GRID
1
V
DISP
D-GND
GRID
2
V
DISP
D-GND
GRID
3
SEG1-82
V
DISP
D-GND
V
DISP
D-GND
1016 bit times
1016 bit times
1016 bit times
2048 bit times1 (display cycle)
8 bit times
8 bit times
8 bit times
64 bit times
64 bit times
64 bit times
GRID
1
V
DISP
D-GND
GRID
2
V
DISP
D-GND
GRID
3
SEG1-82
V
DISP
D-GND
V
DISP
D-GND
1016 bit times
1016 bit times
1016 bit times
3072 bit times (1 display cycle)
8 bit times
8 bit times
8 bit times
64 bit times
64 bit times
64 bit times
FEDL9228-01
OKI Semiconductor
ML9228
13/25
FUNCTIONAL DESCRIPTION
Power-on Reset
When power is turned on, ML9228 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
The contents of the shift registers and latches are set to "0".
The digital dimming duty cycle is set to "0".
All segment outputs are set to Low level.
Grid1 output is set to Low level. Grid2,3 outputs are set to High level.
All the ROW outputs are set to Low level.
INT output is set to Low level.
Reset
When power is turned on, ML9228 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
The contents of the shift registers and latches are set to "0".
The digital dimming duty cycle is set to "0".
All segment outputs are set to Low level.
Grid1 output is set to Low level. Grid2,3 outputs are set to High level.
All the ROW outputs are set to Low level.
INT output is set to Low level.
A command is received by the signal of Low(L-GND) level.
Blank
All segment outputs are set as a Low level.
A command is received by the signal of Low(L-GND) level.
Data Input and Output
Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High level.
The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is
automatically loaded to the latches when the CS pin is set at a Low level.
10-bit dimming data (D1 to D10) and 82-bit segment data (S1 to S82) are used for inputting of dimming data and
display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data
succeddingly.
The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock.
ML9228 outputs 30-bit key data (S11 to S56). To receive these data, the mode data (M0 to M2) must be sent first
and then CS must be set once to Low level and set again to High level.
Then inputting serial clocks, these data are output from the DATA I/O pin.
When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin.
To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is
stopped immediately.
CS
CLOCK
Keyscan
Stop
Command
DATA I/O
M0
M1 M2
M0
M1
M2
S44 S45 S51 S52
S53
S54
S55
S56
S11 S12 S13 S14 S15 S21 S22
Switch
Data
Output
Command
Switch Data
FEDL9228-01
OKI Semiconductor
ML9228
14/25
Mode Data
ML9228 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation
between function mode and mode data (M0 to M2) is as follows:
FUNCTION DATA
FUNCTION MODE
OPERATING MODE
M0 M1 M2
0
Segment Data for
GRID
1-3 Input
0
0
0
1
Segment Data for
GRID
1 Input
1
0
0
2
Segment Data for
GRID
2 Input
0
1
0
3
Segment Data for
GRID
3 Input
1
1
0
4
Digital Dimming Data Input
0
0
1
5
Keyscan Stop
1
0
1
6
Switch Data Output
0
1
1
7 Sleep
1
1
1
FEDL9228-01
OKI Semiconductor
ML9228
15/25
Segment Data Input [Function Mode: 0 to 3]
ML9228
receives the segment data when function mode 0 to 3 are selected.
The same segment data is transferred to the 3 segment data latch correspond to
GRID1
to
3 at the same time
when the function mode 0 is selected.
The segment data is transferred to only one segment data latch that is selected by mode data, when the function
mode is 1, 2 or 3 is selected.
Segment output (SEG1 to 82) becomes High level when the segment data (S1 to S82) is High level.
[Data Format]
Input Data
: 85 bits
Segment Data
: 82 bits
Mode
Data
: 3
bits
Bit
1 2 3 4 -----------
79
80
81
82
83 84 85
Input
Data S1
S2 S3 S4
-----------
S79 S80 S81 S82
M0 M1 M2
Segment Data (82 bits)
Mode Data
(3 bits)
[Bit correspondence between segment output and segment data]
SEG n
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
Segment data
S1 S2 S3 S4 S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
SEG
n
17 18 19 20 21
22
23
24
25
26
27
28
29 30 31 32
Segment data
S17 S18 S19 S20 S21
S22
S23
S24
S25
S26
S27
S28
S29 S30 S31 S32
SEG
n
33 34 35 36 37
38
39
40
41
42
43
44
45 46 47 48
Segment data
S33 S34 S35 S36 S37
S38
S39
S40
S41
S42
S43
S44
S45 S46 S47 S48
SEG
n
49 50 51 52 53
54
55
56
57
58
59
60
61 62 63 64
Segment data
S49 S50 S51 S52 S53
S54
S55
S56
S57
S58
S59
S60
S61 S62 S63 S64
SEG
n
65 66 67 68 69
70
71
72
73
74
75
76
77 78 79 80
Segment data
S65 S66 S67 S68 S69
S70
S71
S72
S73
S74
S75
S76
S77 S78 S79 S80
SEG n
81 82
Segment data
S81
S82
FEDL9228-01
OKI Semiconductor
ML9228
16/25
Digital Dimming Data Input [Function Mode: 4]
ML9228
receives the digital dimming data when function mode 4 is selected.
The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
The 10-bit digital dimming data is input from LSB.
[Data Format]
Input Data
: 13 bits
Digital Dimming Data
: 10 bits
Mode
Data
: 3
bits
Bit
1 2 3 4 5 6 7 8 9 10
11 12 13
Input
Data D1
D2 D3 D4
D5
D6
D7
D8
D9
D10
M0 M1 M2
LSB
MSB
Digital Dimming Data (10 bits)
Mode Data
(3 bits)
(LSB)
Dimming Data
(MSB)
D1
D2 D3 D4
D5
D6
D7
D8
D9
D10
Duty Cycle
0 0 0 0 0 0 0 0 0 0
0/1024
1 0 0 0 0 0 0 0 0 0
1/1024
1 1 1 0 1 1 1 1 1 1 1015/1024
0 0 0 1 1 1 1 1 1 1 1016/1024
1 0 0 1 1 1 1 1 1 1 1016/1024
1 1 1 1 1 1 1 1 1 1 1016/1024
Keyscan Stop [Function Mode: 5]
ML9228 stops a key scanning when function mode 5 are selected.
To select this mode, the only mode data (M0 to M2) is needed.
The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4
s to
3.6
s
[Input Data Format]
Input Data
: 3 bits
Mode Data
: 3 bits
Bit
83 84 85
Input
Data M0 M1 M2
Mode Data
(3 bits)
FEDL9228-01
OKI Semiconductor
ML9228
17/25
Switch Data Output [Function Mode: 6]
ML9228 output the switch data when function mode 6 is selected.
To select this mode, the only mode data (M0 to M2) is needed.
When ML9228 recieves this mode, the DATA I/O pin is changed to an output pin.
30-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock.
When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.
Contact Count bits are Q1 (LSB) to Q3 (MSB)
[Input Data Format]
Input Data
: 3 bits
Mode Data
: 3 bits
Bit
83 84 85
Input
Data M0 M1 M2
Mode
Data
(3 bits)
[Output Data Format]
Output Data
: 30 bits
5
6 push switch Data
: 30 bits
Bit
1 2 3
4
5
6
7
8
9
10
11 12
Output Data
S11 S12 S13
S14
S15
S16
S21
S22
S23
S24
S25 S26
Bit
13 14 15
16
17
18
19
20
21
22
23 24
Output Data
S31 S32 S33
S34
S35
S36
S41
S42
S43
S44
S45 S46
Bit
25 26 27
28
29
30
Output Data
S51
S52
S53
S54
S55
S56
Sij: i = ROW1 to 5, j =
COL
1 to 6
Sij = 1: Switch ON
Sij = 0: Switch OFF
[5
6Push Switch]
=
COL
1
COL
2
COL
3
COL
4
ROW1 ROW2
ROW3
ROW4
ROW5
COL
5
COL
6
FEDL9228-01
OKI Semiconductor
ML9228
18/25
P-in/S-out shift resistor
When the switch data output mode is selected and CS goes L, all the key data send to the shift resistor, and the
up/down counter is reset and the INT signal goes "L".
CS
Data I/O
CLOCK
When CS goes L, the up/down counter is reset and the INT goes "L".
INT
C1 C2 C3 C4 C5 C6
ROW1
ROW4
ROW5
C1 C2 C3 C4 C5 C6 C1 C2 C3 C4 C5 C6
FEDL9228-01
OKI Semiconductor
ML9228
19/25
Keyscan
Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by
scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The
INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level)
signal sent from the INT pin can be used as an interrupt signal.
[Keyscan Timing]
Note:
Keyscanning cannot be stopped by selecting the keyscan stop mode only once if:
- keyscanning is started after depression or release of any key is detected, and then
- a key is depressed or released again before the keyscan stop mode is selected.
To stop keyscanning, it is required to select the keyscan stop mode once again.
1 Cycle
INT
ROW 5
ROW
4
ROW 3
ROW 2
ROW 1
Depress/Release
Keyscan stop mode
is selected.
Depress Depress
Release
Keyscan Keyscan
INT
CS
MODE5
MODE5
MODE5
MODE5 : Keyscan stop
Keyscan
FEDL9228-01
OKI Semiconductor
ML9228
20/25
Sleep [Function Mode: 7]
ML9228
oscillation stops and segment display turns off when function mode 7 is selected.
key matrix is pushed, this mode will be canceled and it will usually become display mode.
[Input Data Format]
Input Data
: 3 bits
Mode Data
: 3 bits
Bit
83 84 85
Input
Data M0 M1 M2
Mode
Data
(3 bits)
Wake up
Wake up by key press from
COL6. Then, key scan is performed.
Wake up by CS assert(rising edge). Then, key scan does not carry out.
Oscillation restarts to accept normal operation.
Previous output for display data till updated by Each Mode.
If either of these keys is pushed, an oscillation will be started and it will usually return to operation.
COL
1
COL
2
COL
3
COL
4
ROW1
ROW2 ROW3
ROW4
ROW5
COL
5
COL
6
=
FEDL9228-01
OKI Semiconductor
ML9228
21/25
APPLICATION CIRCUITS
Circuit for the triplex VFD tube with 246 segments (3 Grid
82 Anode)
ML
9228
V
DI
SP
V
DD
L
-
G
ND
CL
O
C
K
DA
T
A
I/O
CS
GR
I
D
2
GR
I
D
1
GR
I
D
3
SEG
1
SEG
8
2
T
r
iplex
V
F
D
T
ube
S
80
S
81
S
82
S1
S2
S3
G1
G2
V
DI
SP
Ef
G
ND
G
ND
OS
C
0
V
DD
RO
W
1
to 5
C
OL
1 to 6
5
6
Ke
y
m
a
t
r
ix
B
LA
N
K
G3
DUP
/
TR
I
Microcontroller
R
ES
ET
V
DD
D-
G
ND
FEDL9228-01
OKI Semiconductor
ML9228
22/25
POWER SEQUENCE
If the power sequence (please see below) recommended by Oki is not followed,it is possible to damage internal
logic transistors.
Currently there is no definition for the time period between the point that V
DD
= 3.3V V
DISP
= 3.3V.
Oki recommends the following sequence.
18.0V
3.3 V
2.0
S
2.0
S
VDD
VDISP
FEDL9228-01
OKI Semiconductor
ML9228
23/25
PACKAGE DIMENSIONS
QFP128-P-1420-0.50-K
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
5m)
Package weight (g)
1.19 TYP.
5
Rev. No./Last Revised
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
(Unit: mm)
FEDL9228-01
OKI Semiconductor
ML9228
24/25
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
Description
FEDL9228-01 Oct. 20, 2004
Final edition 1
FEDL9228-01
OKI Semiconductor
ML9228
25/25
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
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