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Электронный компонент: MR53V8052J-XXRA

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Semiconductor
MR53V8052J
Preliminary
524,288-Word X 16-Bit or 1,048,576-Word X 8-Bit
8Word X 16-Bit or 16Word X 8-Bit/Page Mode MASK ROM
1/6
This version: Feb. 1999
Previous version: -------
DESCRIPTION
The MR53V8052J is a 8Mbit Read-Only Memory whose configuration can be electrically switched
between 524,288 word x 16bit and 1,048,576 word x 8bit. The MR53V8052J operates asynchronously,
external clocks are not required, making this device easy-to-use. The MR53V8052J is suitable as
large-capacity fixed memory for microcomputers and data terminals. It is manufactured using a CMOS
silicon gate technology and is offered in 42-pin DIP, 44-pin SOP or 44-pin TSOP packages.
FEATURES
524,288 word x 16bit / 1,048,576 word x 8bit electrically switchable configuration
8word x 16-Bit or 16word x 8-bit / Page read mode
Single +2.7V~3.6V power supply
Normal access time
100ns
Page access time
30ns
V
CC
power supply current 80mA
V
CC
standby current
10mA
Input / Output TTL compatible
Three-state output
Packages
42-pin plastic DIP
(DIP42-P-600-2.54)
MR53V8052J-XXRA
44-pin plastic SOP (SOP44-P-600-1.27-K)
MR53V8052J-XXMA
44-pin plastic TSOP (TSOPII44-P-400-0.80-K) MR53V8052J-XXTP
Semiconductor
MR53V8052J
2/6
PIN CONFIGURATION (TOP VIEW)
PIN NAMES
FUNCTIONS
D15/A-1
Data output / Address input
A0~A18
Address input
D0~D14
Data output
CE
Chip enable
OE
Output enable
BYTE
Mode switch
V
CC
Power supply voltage
V
SS
GND
NC
Non connection
1
A18
2
A17
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
CE
12
V
SS
13
OE
14
D0
15
D8
16
D1
17
D9
18
D2
19
D10
20
D3
21
D11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
V
CC
2
A18
3
A17
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
CE
13
V
SS
14
OE
15
D0
15
D8
17
D1
18
D9
19
D2
20
D10
21
D3
22
D11
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
V
CC
1
NC
44
NC
42-Pin DIP
44-Pin SOP
44-Pin TSOPII
Semiconductor
MR53V8052J
3/6
BLOCK DIAGRAM
FUNCTION TABLE
MODE
CE
OE
BYTE
D0~D7
D8~D14
A-1/D15
STAND BY
H
X
X
L
H
H
Hi-Z
OUTPUT DISABLE
L
H
L
L/H
READ(16-BIT)
L
L
H
D
OUT
READ(8-BIT)
L
L
L
D
OUT
Hi-Z
L/H
X8/X16 SWITCH
CE OE CONTROL
Address
Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Row
Decoder
Column
Decoder
Memory Cell
Matrix
524,288 x 16 or 1,048,676 x 8
Multiplexer
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
CE
OE
A-1
BYTE
Output Buffer
Semiconductor
MR53V8052J
4/6
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Value
Unit
Operating temperature under bias
T
OPR
-
0 ~ 70
`C
Storage temperature
T
STG
-
-55 ~ 125
`C
Input voltage
V
I
-0.5 ~ V
CC
+0.5
V
Output voltage
V
O
-0.5 ~ V
CC
+0.5
V
Power supply voltage
V
CC
Relative to V
SS
-0.5 ~ 5
V
Power dissipation per package
P
D
-
1.0
W
RECOMMENDED OPERATING CONDITIONS FOR READ
(Ta=0 ~ 70`C)
Parameter
Symbol
Condition
Min.
Typ.
Min.
Unit
V
CC
power supply voltage
V
CC
2.7
-
3.6
`C
Input "H" level
V
IH
2.2
-
V
CC
+0.5
`C
Input "L" level
V
IL
V
CC
=2.7V ~ 3.6V
-0.5
-
0.8
V
Voltage is relative to V
SS
PIN Capacitance
(Vcc=3.3V, Ta=25`C, f=1MHz)
Parameter
Symbol
Condition
Min.
Typ.
Min.
Unit
Input
C
IN
V
I
=0V
-
-
12
pF
Output
C
OUT
V
O
=0V
-
-
15
pF
Semiconductor
MR53V8052J
5/6
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Vcc=2.7V~3.6V, Ta=0~70`C)
Parameter
Symbol
Condition
Min.
Typ.
Min.
Unit
Input leakage current
C
IN
V
I
=0V~V
CC
-
-
10
mA
Output leakage current
C
OUT
V
O
=0V~V
CC
-
-
10
mA
I
CCSC
CE= V
CC
-
-
10
mA
V
CC
power supply current
(Standby)
I
CCST
CE= V
IH
-
-
1
mA
V
CC
power supply current
(Active)
I
CCA
CE= V
IL
, OE= V
IH
tc= 100ns
-
-
80
mA
Input "H" level
V
IH
-
2.0
-
V
CC
+0.5
V
Input "L" level
V
IL
-
-0.5
-
0.8
V
Output "H" level
V
OH
I
OH
=-200 mA
V
CC
-0.4
-
-
V
Output "L" level
V
OL
I
OL
=1mA
-
-
0.4
V
Voltage is relative to V
SS
AC Characteristics
(Vcc=2.7V~3.6V, Ta=0~70`C)
Parameter
Symbol
Condition
Min.
Min.
Unit
Address access cycle time
T
C
-
100
-
ns
Address access time
T
ACC
CE=OE= V
IL
-
100
ns
Page set up time
T
PSET
NOTE.1
100
-
ns
Page access cycle time
T
PC
-
30
-
ns
Page access time
T
PAC
-
-
30
ns
CE access time
T
CE
OE= V
IL
-
100
ns
OE access time
T
OE
CE= V
IL
-
30
ns
T
CHZ
OE= V
IL
0
30
ns
Output disable time
T
OHZ
CE= V
IL
0
25
ns
Output hold time
T
OH
CE=OE= V
IL
0
-
ns
NOTE.1 T
PSET
is defined as the end of either CE falling edge or address transition in random access
term until the first page address transition.
Measurement condition
Input signal level
0V/3V
Input timing reference level
0.8V/2.0V
Output load
100pF
Output timing reference level
0.8V/2.0V
Output
400W
1.7V
100pF
Semiconductor
MR53V8052J
6/6
TIMING CHART
NORMAL MODE READ CYCLE
PAGE MODE READ CYCLE
ADDRESS
CE
OE
DOUT
t
C
t
CE
t
OE
t
ACC
t
OHZ
t
CHZ
t
OH
Hi-Z
Hi-Z
Valid Data
A3-A18
CE
t
C
OE
t
PSET
t
PSET
t
PC
t
PC
t
CE
t
OE
t
ACC
t
PA
t
PA
t
OHZ
t
CHZ
t
OH
Hi-Z
DOUT
A0~A2
(x16mode)
A-1~A2
(x8mode)
Page 1
Semiconductor
NOTICE
The information contained herein can change without notice owing to product and/or technical im-
provements. Before using the product, please make sure that the information being referred to is up-to-
date.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program
designs.
When designing your product, please use our product below the specified maximum ratings and within
the specified operating ranges including, but not limited to, operating voltage, power dissipation, and
operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected opera-
tion resulting from misuse, neglect, improper installation, repair, alteration or accident, improper han-
dling, or unusual physical or electrical stress including, but not limited to, exposure to parameters be-
yond the specified maximum ratings or operation outside the specified operating range.
Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party's right which may result
from the use thereof.
The products listed in this document are intended for use in general electronics equipment for commer-
cial applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system orapplication that requires
special or enhanced quality and reliability characteristics nor in any system or application where the
failure of such system or application may result in the loss or damage of property, or death or injury to
humans. Such applications include, but are not limited to, traffic and automotive equipment, safety de-
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Certain products in this document may need government approval before they can be exported to par-
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products and will take appropriate and necessary steps at their own expense for these.
No part of the contents cotained herein may be reprinted or reproduced without our prior permission.
All brand, company and product names are the trademarks or registered trademarks of their respective
owners.
Copyright 1998 Oki Electric Industry Co., Ltd.
Marketing Communications Team (RB)
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