MS81V04160
Dual FIFO (262,214-word x 8-Bits) x 2
GENERAL DESCRIPTION
The MS81V04160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO
(First-In First-Out) memories which were designed for 256k x 8-bit high-speed
asynchronous read/write operation.
The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in
common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory
(MSM51V8222A), can be used as a x16 configuration FIFO.
The MS81V04160 is a field memory for wide or low end use in general commodity TVs and
VTRs exclusively and is not designed for high end use in professional graphics systems,
which require long term picture storage, data storage, medical use and other storage
systems.
The MS81V04160 provides independent control clocks to support asynchronous read and
write operations. Different clock rates are also supported, which allow alternate data rates
between write and read data streams.
The MS81V04160 provides high speed FIFO (First-in First-out) operation without external
refreshing: MS81V04160 refreshes its DRAM storage cells automatically, so that it appears
fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh
free serial access operation, so that serial read and/or write control clock can be halted
high or low for any duration as long as the power is on. Internal conflicts of memory access
and refreshing operations are prevented by special arbitration logic.
The MS81V04160's function is simple, and similar to a digital delay device whose delay-bit-
length is easily set by reset timing. The delay length and the number of read delay clocks
between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable
high speed first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MS81V04160 has a write mask function or input enable function (IE), and
read- data skipping function or output enable function (OE). The differences between write
enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE)
are that WE and RE can stop serial write/read address increments, but IE and OE cannot
stop the increment, when write/read clocking is continuously applied to MS81V04160. The
input enable (IE) function allows the user to write into selected locations of the memory
only, leaving the rest of the memory contents unchanged. This facilitates data processing to
display a "picture in picture" on a TV screen.
1
OKI Semiconductor
REVISION1 1999.4.15
2
MS81V04160
OKI Semiconductor
-25
-30
tAC
23ns
30ns
tSWC
tSRC
Icc1
80mA
80mA
Icc2
(MODE2 ="L")
Parameter
Symbol
MS81V04160-xxTB
Access Time
Read/Write
25ns
30ns
Cycle Time
Operation current
Standby current
3mA
3mA
FEATURES
512 Rows x 512 columns x 8 bits x2
Fast FIFO(First-In First-Out)Operation :25ns cycle time
Self refresh(No refresh control is required)
High speed asynchronous serial access
Read/Write Cycle Time 25ns/30ns
Access Time 22ns/25ns
Variable length delay bit (600 to 262215)
Write mask function (Output enable control)
Cascading capability by mode setting
Single power supply:3.3V
p
10%
Package:
100-Pin plastic TQFP(TQFP 100-P-1414-0.50-k)(Product:MS81V04160-xxTB)
xx indicates speed rank.
3
MS81V04160
OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
Note: The same power supply voltage must be provided to every Vcc pin,and
the same GND voltage level must be provided to every Vss pin.
Pin Name
Pin Name
SWCK
SRCK
WE1
WE2
RE1
RE2
IE1
IE2
OE1
OE2
RSTW1
RSTW2
RSTR1
RSTR2
DI 10-17
DI 20-27
DO 10-17
DO 20-27
MODE1,2,3
NC
Vcc
Vss
Port2 Data Input
Port2 Data Output
No Connection
Ground(0V)
Port2 Input Inable
Port2 Output Inable
Port2 Reset Write
Port2 Reset Read
Function
Serial Read Clock
Port2 Write Inable
Port2 Read Inable
Port1 Data Input
Port1 Data Output
Mode Input
Power Supply(3.3V)
Port1 Input Inable
Port1 Output Inable
Port1 Reset Write
Port1 Reset Read
Function
Serial Write Clock
Port1 Write Inable
Port1 Read Inable
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
100 PIN TQFP
TOP VIEW
Vcc
DO 20
DO 21
Vss
DO 22
DO 23
DO 24
DO 25
Vss
DO 26
DO 27
Vcc
SRCK
Vcc
DO 17
DO 16
Vss
DO 15
DO 14
DO 13
DO 12
Vss
DO 11
DO 10
Vcc
NC
DI 23
Vss
DI 24
DI 25
DI 26
DI 27
NC
Vss
Vss
Vcc
Vcc
SWCK
Vcc
Vcc
Vss
Vss
NC
DI 17
DI 16
DI 15
DI 14
Vss
DI 13
NC
NC
Vss
Vss
NC
OE
2
RE
2
RS
T
R
2
Vcc
NC
MOD
E
1
NC
Vss
NC
Vcc
NC
Vss
Vcc
Vss
WE2
IE
2
RS
T
W
2
DI 2
0
DI 2
1
DI 2
2
NC
NC
Vss
Vss
NC
OE
1
RE
1
RS
T
R
1
Vcc
MOD
E
3
MOD
E
2
NC
Vss
NC
Vcc
NC
Vss
Vcc
Vss
WE1
IE
1
RS
T
W
1
DI 1
0
DI 1
1
DI 1
2
NC
4
MS81V04160
OKI Semiconductor
BLOCK DIAGRAM
-
25
6k (
G
8)
Me
mor
y
Ar
r
a
y
51
2 W
o
r
d
S
e
ri
al
R
e
a
d
R
e
gi
s
t
er
(
G
8)
R
ead
L
i
ne
B
u
f
f
e
r
L
o
w
-
Ha
lf (
G
8)
R
ead
L
i
ne
B
u
f
f
e
r
Hi
g
h
-
H
a
l
f
(
G
8)
W
r
i
t
e Li
ne B
u
ff
er
L
o
w
-
Ha
lf (
G
8)
W
r
i
t
e Li
ne
B
u
f
f
e
r
Hi
g
h
-
H
a
l
f
(
G
8)
51
2 W
o
r
d
S
e
ri
al
W
r
i
t
e R
e
g
i
st
er
(
G
8)
25
6 (
G
8)
25
6 (
G
8)
25
6 (
G
8)
25
6 (
G
8)
Se
r
i
a
l
R
ead
C
ont
r
o
l
l
er
RE
2
RS
T
R
2
SR
CK
WE2
RS
T
W
2
SWC
K
71
W
o
r
d
S
ub-
R
egi
st
er
(
G
8)
Da
t
a
-
I
n
B
u
ff
e
r
(
G
8)
Da
t
a
-
O
u
t
B
u
ff
e
r
(
G
8)
DO
(
G
8)
DI (
G
8)
Read
/W
r
i
te
an
d R
e
fr
esh
C
ont
r
o
l
l
er
IE
2
71
W
o
r
d
S
ub-
R
egi
st
er
(
G
8)
C
ont
r
o
l
l
er
Se
r
i
a
l
Wr
it
e
Decod
e
r
OE
2
Cl
o
c
k
O
sci
l
l
at
or
VB
B
G
ene
r
a
to
r
M
O
D
E
1,
2,
3
-
25
6k (
G
8)
Me
mor
y
Ar
r
a
y
51
2 W
o
r
d
S
e
ri
al
R
e
a
d
R
e
gi
s
t
er
(
G
8)
R
ead
L
i
ne
B
u
f
f
e
r
L
o
w
-
Ha
lf (
G
8)
R
ead
L
i
ne
B
u
f
f
e
r
Hi
g
h
-
H
a
l
f
(
G
8)
W
r
i
t
e Li
ne B
u
ff
er
L
o
w
-
Ha
lf (
G
8)
W
r
i
t
e Li
ne
B
u
f
f
e
r
Hi
g
h
-
H
a
l
f
(
G
8)
51
2 W
o
r
d
S
e
ri
al
W
r
i
t
e R
e
g
i
st
er
(
G
8)
25
6 (
G
8)
25
6 (
G
8)
25
6 (
G
8)
25
6 (
G
8)
Se
r
i
a
l
R
ead
C
ont
r
o
l
l
er
RE
1
RS
T
R
1
SR
CK
WE1
R
S
T
W1
SWC
K
71
W
o
r
d
S
ub-
R
egi
st
er
(
G
8)
Da
t
a
-
I
n
B
u
ff
e
r
(
G
8)
Da
t
a
-
O
u
t
B
u
ff
e
r
(
G
8)
DO
(
G
8)
DI (
G
8)
Read
/W
r
i
te
an
d R
e
fr
esh
C
ont
r
o
l
l
er
IE
1
71
W
o
r
d
S
ub-
R
egi
st
er
(
G
8)
Decod
e
r
OE
1
Se
r
i
a
l
Wr
it
e
C
ont
r
o
l
l
er
5
MS81V04160
OKI Semiconductor
Data Inputs: (DIN 10 - 17)
These pins are used for serial data inputs.
Write Reset: RSTW1
The first positive transition of SWCK after RSTW becomes high resets the write address
pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK.
Because the write reset function is solely controlled by the SWCK rising edge after the high
level of RSTW, the states of WE1 and IE1 are ignored in the write reset cycle. Before
RSTW1 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Write Enable: WE1
WE1 is used for data write enable/disable control. WE1 high level enables the input, and
WE1 lowlevel disables the input and holds the internal write address pointer. There are no
WE1 disabletime (low) and WE1 enable time (high) restrictions, because the MS8104160
is in fully static operation as long as the power is on. Note that WE1 setup and hold times
are referenced to the rising edge of SWCK.
Input Enable: IE1
IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The
internal write address pointer is always incremented by cycling SWCK regardless of the
IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK.
Data Out: (DOUT 0 - 11)
These pins are used for serial data outputs.
Read Reset: RSTR1
The first positive transition of SRCK after RSTR1 becomes high resets the read address
pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK.
Because the read reset function is solely controlled by the SRCK rising edge after the high
level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before RSTR
may be brought high again for a further reset operation, it must be low for at least *two
SRCK cycles.
Read Enable: RE1
The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When
RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is
low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1
hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock.
Output Enable: OE1
OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal
read address pointer is always incremented by cycling SRCK regardless of the OE1 level.
Note that OE1 setup and hold times are referenced to the rising edge of SRCK.
PIN DESCRIPTION
6
MS81V04160
OKI Semiconductor
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE1, 2 is high, and also increments the
internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to
the rising edge of SWCK.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when
RE1, 2 is highduring a read operation. The SRCK input increments the internal read
address pointer when RE1,2 is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required).
Data out is the same polarity as data in. The output becomes valid after the access time
interval tAC that begins with the rising edge of SRCK. *There are no output valid time
restriction on MS8104160.
Data Input: (DIN 20-27)
These pins are used for serial data inputs.
Write Reset: RSTW2
The first positive transition of SWCK after RSTW becomes high resets the write address
pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK.
Because the write reset function is solely controlled by the SWCK rising edge after the high
level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before
RSTW2 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Write Enable: WE2
WE is used for data write enable/disable control. WE2 high level enables the input, and
WE2 lowlevel disables the input and holds the internal write address pointer. There are no
WE2 disabletime (low) and WE2 enable time (high) restrictions, because the MS8104160
is in fully static operation as long as the power is on. Note that WE2 setup and hold times
are referenced to the rising edge of SWCK.
Input Enable: IE2
IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The
internal write address pointer is always incremented by cycling SWCK regardless of the
IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK.
Data Out :
DOUT 20 27
These pins are used for serial data outputs.
Read Reset: RSTR2
The first positive transition of SRCK after RSTR2 becomes high resets the read address
pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK.
Because the read reset function is solely controlled by the SRCK rising edge after the high
level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before
RSTR2 may be brought high again for a further reset operation, it must be low for at least
*two SRCK cycles.
7
MS81V04160
OKI Semiconductor
Output Enable: OE2
OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal
read address pointer is always incremented by cycling SRCK regardless of the OE2 level.
Note that OE2 setup and hold times are referenced to the rising edge of SRCK.
Mode Setting: MODE1
The Cascade/Non cascade select pin. Setting the MODE1 pin to the Vcc level configures
this memory device as cascade type and setting the pin to the Vss level configures this
memory device as non cascade. During memory operation, the pin must be permanentry
connected to Vcc or Vss. If a MODE1 level is changed during memory operation, memory
data is not guaranteed.
Note: Cascade/Non cascade
When MODE1 is set to the Vss level, memory accessing starts in the cycle in which the
control signals are input (Non cascade type).
When MODE1 is set to the Vcc level, memory accessing starts in the cycle subsequent to
the cycle in which the control signals are input (Cascade type). This type is used for
consecutive memory accessing.
MODE2 Setting: MODE2
MODE2 selects whether the control input signals are enabled at a high level or a low level.
Setting MODE2 to the Vcc level enables the control input signals at a low level and setting
MODE2 to the Vss level enables the control input signals at a high level.
MODE Setting: MODE3
The boost control pin for data-out Buffer. For the MS8104160, the MODE3 pin should be
permanentry Connected to the Vss level.
8
MS81V04160
OKI Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Rating
Input Output Voltage
V
T
-1.0 to 4.6
Output Current
I
OS
50
Power Dissipation
P
D
1
Operating Temperature
T
opr
Storage Temperature
T
stg
-55 to 150
Parameter
at Ta = 25
o
C, V
SS
Ta = 25
o
C
Ta =25
o
C
0 to 70
Unit
mA
W
o
C
o
C
V
Parameter Symbol Min. Typ. Max. Unit
Power Supply Voltage V
CC
3.0 3.3 3.6 V
Power Supply Voltage V
SS
0 0 0 V
Input High Voltage V
IH
2.4 V
CC
V
CC
+ 0.3 V
Input Low Voltage V
IL
-0.3 0
0.8 V
Recommended Operating Conditions
Parameter Symbol Condition Min. Max. Unit
Input LeadKage Current I
LI
0 < V
I
< V
CC
, Other Pins Tested at V=0V
-10 10 uA
Output LeadKage Current I
LO
0 < V
O
< V
CC
-10 10 uA
Output "H" Level Voltage V
OH
I
OH
= -1 mA 2.4 - V
Output " L" Level Voltage V
OL
I
OL
= 2 mA - 0.4 V
Operating Current I
CC1
Minimum Cycle Time, Output Open
- 80 mA
I
CC2A
MODE2="L"
- 3
I
CC2B
MODE2="H"
- 10
DC Characteristics
Capacitance
Parameter Symbol Max. Unit
Input Capacitance (D
IN
,SWCK,SRCK,RSTW,RSTR,WE,RE,IE,OE) C
I
7 pF
Outnput Capacitance (D
OUT
) C
O
7 pF
(Ta = 25
o
C , f = 1 MHz)
Standby Current
Input Pin = V
IH
/ V
IL
mA
9
MS81V04160
OKI Semiconductor
AC Characteristics
( Vcc
= 3.0 - 3.6V,Ta = 0 to 70
o
C )
Parameter
Symbol
Unit
Min.
Max.
Access Time from SRCK
t
AC
30
ns
DOUT Hold Time from SRCK
t
DDCK
-
ns
DOUT Enable Time from SRCK
t
DECK
30
ns
SWCK "H" Pulse Width
t
WSWH
20
ns
SWCK "L" Pulse Width
t
WSWL
20
ns
Input Time Data Setup
t
DS
ns
Input Data Hold Time
t
DH
ns
WE Enable Setup Time
t
WENS
ns
WE Enable Hold Time
t
WENH
ns
WE Disable Setup Time
t
WDSS
ns
WE Disable Hold Time
t
WDSH
ns
IE Enable Setup Time
t
IENS
ns
IE Enable Hold Time
t
IENH
ns
IE Disable Setup Time
t
IDSS
ns
IE Disable Hold Time
t
IDSH
ns
WE "H" Pulse Width
t
WWEH
ns
WE "L" Pulse Width
t
WWEL
ns
IE "H" Pulse Width
t
WIEH
ns
IE "L" Pulse Width
t
WIEL
ns
RSTW Setup Time
t
RSTWS
ns
RSTW Hold Time
t
RSTWH
ns
SRCK "H" Pulse Width
t
WSRH
ns
SRCK "L" Pulse Width
t
WSRL
ns
RE Enable Setup Time
t
RENS
ns
RE Enable Hold Time
t
RENH
ns
RE Disable Setup Time
t
RDSS
ns
RE Disable Hold Time
t
RDSH
ns
OE Enable Setup Time
t
OENS
ns
OE Enable Hold Time
t
OENH
ns
OE Disable Setup Time
t
ODSS
ns
OE Disable Hold Time
t
ODSH
ns
RE "H" Pulse Width
t
WREH
ns
RE "L" Pulse Width
t
WREL
ns
OE "H" Pulse Width
t
WOEH
ns
OE "L" Pulse Width
t
WOEL
ns
RSTR Setup Time
t
RSTRS
ns
RSTR Hold Time
t
RSTRH
ns
SWCK Cycle Time
t
SWC
ns
SRCK Cycle Time
t
SRC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Transition Time (Rise and Fall)
t
T
-
23
6
-
6
23
15
-
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
-
6
6
30
ns
Min.
Max.
MS81V04160-25
MS81V04160-30
3
5
5
5
5
5 (7)
5
5
5
5
5
5
5
3
15
15
3
5
3
5
3
5
3
5
5
5
5
5
3
10
25
25
3
5
5
5
5
5
5
5
5
3
10
20
20
3
5
3
5
3
5
3
5
3
30
30
3
5 (7)
5 (7)
5 (7)
10
10
10
10
10
10
10
10
10
10
10
MS81V04160
OKI Semiconductor
Notes: 1. Input signal reference levels for the parameter measurement are V
IH
= 3.0 V and
V
IL
= 0 V. The transition time t
T
is defined to be a transition time that signal transfers
between V
IH
= 3.0 V and V
IL
= 0 V.
2. AC measurements assume t
T
= 3 ns.
3. Read address must have more than a 600 address delay than write address in
every cycle when asynchronous read/write is performed.
4. Read must have more than a 600 address delay than write in order to read the data
written in a current series of write cycles which has been started at last write reset
cycle: this is called "new data read". When read has less than a 70 address delay
than write, the read data are the data written in a previous series of write cycles
which had been written before at last write reset cycle: this is called "old data read".
5. When the read address delay is between more than 71 and less than 599 or more
than 262,214, read data will be undetermined. However, normal write is achieved in
this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output
reference levels are V
OH
= 1.5 V and V
OL
= 1.5 V.
7. ( ): MODE2=Vcc
11
MS81V04160
OKI Semiconductor
Write Operation Cycle (MODE2=Vss)
The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,
WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding
WE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be
preformed for internal circuit initialization before Write operation.
Each write operation, which begins after RSTW1, must contain at least 80 active write
cycles, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM
array, which at that time is stored in the serial data registers attached to the DRAM array, an
RSTW1 operation is required after the last SWCK cycle.
Note that every write timing of MS8104160 is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Setting MODE1 to the Vss level starts write data accessing in the cycle in which RSTW1,
WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the
cycle in which RSTW1, WE1, and IE1 control signals are input.
These operation are the same for Port1 and Port2.
OPERATION MODE
WE1,2
IE1,2
H
H
H
L
L
X
Data input
Internal Write address pointer
Incremented
Halted
X indicates "don't care"
Not input
Input
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and
Data input.
Write Operation Cycle (MODE2=Vcc)
The write Operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,
WE2, and IE1, IE2. Port1 write operation is accomplished by cycling SWCK and holding
both WE1 and IE1 low after the write address pointer reset operation or RSTW1. RSTW1
must be performed for internal circuit initialization before write operation.
Each write operation, which begins after RSTW1, must contain at least 80 active write
cycle, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM
array, which at that time is stored in the serial data registers attached to the DRAM array,
an RSTW1 operation is required after the last SWCK cycle.
Note that every write timing of MS8104160 is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Setting MODE1 to the Vss level starts write data accessing in the cycle in which
RSTW1.WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle in which RSTW1,
WE1, and IE1 control signals are input.
Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the
cycle in which RSTW1, WE1, and IE1 control signals are input.
These operations are the same for port1 and Port2.
12
MS81V04160
OKI Semiconductor
Read Operation Cycle (MODE2=Vss)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1,
RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding
both RE1 and OE1 high after the read address pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 80 active read
cycles, i.e. SRCK cycles while RE1 and OE1 are high.
These operations are the same for Port1 and Port2.
RE1,2
OE1,2
H
H
H
L
L
H
L
L
Internal Write address pointer
Data output
Incremented
Output
Halted
High impedance
Output
High impedance
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data
output.
Read Operation Cycle (MODE2=Vcc)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1,
RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding
both RE1 and OE1 high after the read address pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 80 active read
cycles, i.e. SRCK cycles while RE1 and OE1 are low.
These operations are the same for Port1 and Port2.
RE1,2
OE1,2
L
L
L
H
H
L
H
H
Halted
Output
High impedance
Internal Write address pointer
Data output
Incremented
Output
High impedance
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data
output.
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data
input.
WE1,2
IE1,2
L
L
L
H
H
X
X indicates "don't care"
Internal Write address pointer
Data input
Incremented
Input
Not input
Halted
13
MS81V04160
OKI Semiconductor
Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and
reading out from memory. If reading from the first field starts with an RSTR1, 2 operation,
before the start of writing the second field (before the next RSTW1, 2 operation), then the
data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in
the second field of data for as many as 70 SWCK cycles. If the RSTR1, 2 operation for the
first field read-out occurs less than 70 SWCK cycles after the RSTW1, 2 operation for the
second field write-in, then the internal buffering of the device assures that the first field will
still be read out. The first field of data that is read out while the second field of data is
written is called "old data". In order to read out "new data", i.e., the second field written in,
the delay between an RSTW1, 2 operation and an RSTR1, 2 operation must be at least
600 SRCK cycles. If the delay between RSTW1, 2 and RSTR1, 2 operations is more than
71 but less than 600 cycles, then the data read out will be undetermined. It may be "old
data" or "new" data, or a combination of old and new data. Such a timing should be
avoided.
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 us after
Vcc has stabilized to a value within the range of recommended operating conditions. After
this 100 us stabilization interval, the following initialization sequence must be performed.
Because the read and write address pointers are undefined after power-up, a minimum of
80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be
performed, followed by an RSTW1, 2 operation and an RSTR1, 2 operation, to properly
initialize the write and the read address pointer. Dummy write cycles/RSTW1, 2 and
dummy read cycles/RSTR1, 2 may occur simultaneously.
If these dummy read and write operations start while Vcc and/or the substrate voltage has
not stabilized, it is necessary to perform an RSTR1, 2 operation plus a minimum of 80
SRCK cycles plus another RSTR1,2 operation, and an RSTW1,2 operation plus a
minimum of 80 SWCK cycles plus another RSTW1,2 operation to properly initialize read
and write address pointers.
14
MS81V04160
OKI Semiconductor
TIMING WAVEFORM
Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vss
n cycle
Disable cycle
n+1 cycle
tWENH
tWWEL
tWENS
Disable cycle
tWDSH
tWWEH
tWDSS
n-1
n
n+1
DI
10-17/20-27
SWCK
WE 1,2
IE 1,2
RSTW 1,2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vss
DI
10-17/20-27
n cycle
0 cycle
1 cycle
2 cycle
tDS
tDH
tRSTWS
tRSTWH
tWSWH
tWSWL
tSWC
n-1
n
0
1
2
SWCK
WE 1,2
IE 1,2
RSTW 1,2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
15
MS81V04160
OKI Semiconductor
Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vss
Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vcc
SWCK
IE 1,2
DI
10-17/20-27
WE 1,2
RSTW 1,2
n cycle
n+1 cycle
n+3 cycle
tIENH
tWIEL
tIENS
n+2 cycle
tIDSH
tWIEH
tIDSS
n-1
n
n+3
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
SWCK
RSTW 1,2
DI
10-27/20-27
WE 1,2
IE 1,2
n cycle
0 cycle
1 cycle
tDS
tDH
tRSTWS
tRSTWH
tWSWH tWSWL
tSWC
n-1
n
0
1
2
2 cycle
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
16
MS81V04160
OKI Semiconductor
Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vcc
Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vcc
SWCK
WE 1,2
DI
10-17/20-27
IE 1,2
RSTW1,2
tWENH
tWWEL
tWENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
tWDSH
tWWEH
tWDSS
V
IH
V
IL
n-1
n
n+1
n cycle
Disable cycle
n+1 cycle
Disable cycle
SWCK
IE 1,2
WE 1,2
RSTW 1,2
n cycle
n+1 cycle
n+3 cycle
tIENH
tWIEL
tIENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
n+2 cycle
tIDSH
tWIEH
tIDSS
DI
10-17/20-27
V
IH
V
IL
n-1
n
n+3
V
IL
17
MS81V04160
OKI Semiconductor
Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vss
Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vss
SWCK
RSTW 1,2
DI
10-17/20-27
WE 1,2
IE 1,2
n cycle
0 cycle
1 cycle
2 cycle
tDS
tDH
n
0
1
2
3
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
tRSTWS
tRSTWH
tWSWH tWSWL
tSWC
SWCK
WE 1,2
DI
10-17/20-27
IE 1,2
RSTW 1,2
n cycle
Disable cycle
n+1 cycle
tWENH
tWWEL
tWENS
Disable cycle
tWDSH
tWWEH
tWDSS
n
n+1
n
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
18
MS81V04160
OKI Semiconductor
Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vss
Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vcc
SWCK
IE 1,2
DI
10-17/20-27
WE 1,2
RSTW 1,2
n cycle
n+1 cycle
n+3 cycle
tIENH
tWIEL
tIENS
n+2 cycle
tIDSH
tWIEH
tIDSS
n
n
n+4
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
n+3
SWCK
RSTW 1,2
DI
10-27/20-27
WE 1,2
IE 1,2
n cycle
0 cycle
1 cycle
tDS
tDH
tRSTWS
tRSTWH
tWSWH tWSWL
tSWC
n-1
n
0
1
2
2 cycle
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
n-1 cycle
19
MS81V04160
OKI Semiconductor
Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vcc
Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vcc
SWCK
WE 1,2
DI
10-17/20-27
IE 1,2
RSTW1,2
tWENH
tWWEL
tWENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
tWDSH
tWWEH
tWDSS
V
IH
V
IL
n
n+1
n+2
n cycle
Disable cycle
n+1 cycle
Disable cycle
n+2 cycle
SWCK
IE 1,2
WE 1,2
RSTW 1,2
n cycle
n+1 cycle
n+3 cycle
tIENH
tWIEL
tIENS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
n+2 cycle
tIDSH
tWIEH
tIDSS
DI
10-17/20-27
V
IH
V
IL
n
n+3
n+4
V
IL
20
MS81V04160
OKI Semiconductor
Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vss
DO
10-17/20-27
SRCK
RSTR 1,2
RE 1,2
OE 1,2
n cycle
0 cycle
1 cycle
2 cycle
tAC
tRSTRS
tRSTRH
tWSRH tWSRL
tSRC
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
n-1
n
0
1
2
tDDCK
Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vss
SRCK
RE 1,2
DO
10-17/20-27
OE 1,2
RSTR 1,2
n cycle
Disable cycle
n+1 cycle
tRENH
tWREL
tRENS
V IH
V IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
Disable cycle
tRDSH
tWREH
tRDSS
n-1
n
n+1
21
MS81V04160
OKI Semiconductor
Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vss
SRCK
OE 1,2
DO
10-17/20-27
RE 1,2
RSTR 1,2
n cycle
n+1 cycle
n+3 cycle
tOENH
tWOEL
tOENS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
n+2 cycle
tODSH
tWOEH
tODSS
n-1
n
n+3
Hi-Z
tDECK
Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vcc
SRCK
RSTR 1,2
DO
10-17/20-27
RE 1,2
OE 1,2
n cycle
1 cycle
2 cycle
tAC
tRSTRS
tRSTRH
tWSRH
tWSRL
tSRC
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
n-1
n
1
2
0 cycle
0
tDECK
22
MS81V04160
OKI Semiconductor
Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vcc
RSTR 1,2
V
SRCK
RE 1,2
DO
10-17/20-27
OE 1,2
n cycle
Disable cycle
n+1 cycle
tRENH
tWREL
tRENS
Disable cycle
tRDSH
tWREH
tRDSS
n-1
n
n+1
tAC
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
IL
Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vcc
SRCK
tOENH
tODSH
tODSS
OE 1,2
DO
10-17/20-27
RE 1,2
RSTR 1,2
n cycle
n+1 cycle
n+3 cycle
tWOEL
tOENS
n+2 cycle
tWOEH
n-1
n
n+3
Hi-Z
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
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