Semiconductor

This version: Sep. 2000

MS81V06160

Preliminary

(401,408-word

16-bit) FIFO memory

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GENERAL DESCRIPTION

The MS81V06160 is a 6Mb FIFO (First-In First-Out) memory designed for 401,408-words

16-bit high-speed

asynchronous read/write operation.

The MS81V06160 is best suited for a field memory for digital TVs or LCD panels which require high-speed, large
memory , and is not designed for high end use in professional graphics systems, which require long term picture
storage and data storage.

The MS81V06160 is provided with independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write
operation is enabled after 1600 ns + 4 cycles from write reset. Thereafter, the high-speed read/write operation is
possible every cycle time.

Additionally, a write mask function by IE pin and a read-data skipping function by OE pin implement image data
processing easily.

The MS81V06160 provides high speed FIFO (First-in First-out) operation without external refreshing:
MS81V06160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.

The MS81V06160's function is simple, and similar to a digital delay device whose delay-bit- length is easily set by
reset timing. The delay length and the number of read delay clocks between write and read, is determined by
externally controlled write and read reset timings. The MS81V06160 uses a thin and small 70-pin plastic TSOP.

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FEATURES

401,408 words

16 bits

Fast FIFO (First-In First-Out) operation: 12 ns cycle time

Self refresh (No refresh control is required)

High speed asynchronous serial access
Read/Write Cycle Time

12 ns/15 ns

Access Time

9 ns/12 ns

Variable length delay bit (600 to 401,408)

Write mask function (Output enable control)

Cascading capability

Single power supply: 3.3 V ± 10%

Package:
70-pin plastic TSOP TYPE II (TSOP II 70-P-400-0.5-K) (Product name: MS81V06160-xxTA)

xx indicates speed rank.

MS81V06160-TA

Parameter

Symbol

Access Time

tAC

9 ns

12 ns

Read/Write
Cycle Time

tSWC

tSRC

12 ns

15 ns

Operation current

Icc1

210 mA

170 mA

Standby current

Icc2

6 mA

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PIN CONFIGURATION (TOP VIEW)

70-pin Plastic TSOP

SWCK

Serial Write Clock

SRCK

Serial Read Clock

Write Enable

Read Enable

Input Enable

Output Enable

RSTW

Reset Write

RSTR

Reset Read

DI0-15

Data Input

DO0-15

Data Output

Ground (0 V)

Power Supply (3.3 V)

No Connection

Note: The same power supply voltage must be provided to every V

pin, and the same GND voltage

level must be provided to every V

pin.

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DI4

DI5

DI6

DI7

RSTR

SRCK

DI15

DI14

DI13

DI12

DO15

DO14

DO13

DO12

DO11

DO10

DO9

DO8

DI11

DI10

DI9

DI8

RSTW

SWCK

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PIN DESCRIPTION

Data Inputs: (DI0-15)
These pins are used for serial data inputs.

Write Reset: RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK.

Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS8106160 is in fully static operation as long as the power is on. Note that WE setup and
hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 2.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.

Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 2.

Data Out: (DO0-15)
These pins are used for serial data outputs.

Read Reset: RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address pointers to zero.
RSTR setup and hold times are referenced to the rising edge of SRCK.

Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
The latency for the read operation control by RE is 2. After read reset, RE must remain low for more than 1600 ns
(tFRD). After read reset, the read data at address 0 is output after a time tRL from the cycle in which WE is brought
high.
After read reset, RE should be remained high for 2 cycles after driving RE high first.

Output Enable: OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced
to the rising edge of SRCK. The latency for the read operation control by OE is 2.

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Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.

Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS8106160.

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ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter

Symbol

Condition

Rating

Unit

Power Supply Voltage

Ta = 25°C

0.5 to +4.6

Input Output Voltage

Ta = 25°C, V

0.5 to +4.6

Output Current

Ta = 25°C

Power Dissipation

Ta = 25°C

Operating Temperature

opr

0 to 70

°C

Storage Temperature

stg

55 to +150

°C

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Power Supply voltage

3.0

3.3

3.6

Input High Voltage

2.0

+ 0.2

Input Low Voltage

0.3

0.8

DC Characteristics

Parameter

Symbol

Condition

Min.

Max.

Unit

Input Leakage Current

0 < V

< V

Other Pins Tested at V = 0 V

+10

Output Leakage Current

0 < V

< V

+10

Output "H" Level Voltage

= 2 mA

2.4

Output "L" Level Voltage

= 2 mA

0.4

210

Operating Current

CC1

Minimum Cycle Time

Output Open

170

Standby Current

CC2

Input Pin = V

Capacitance

= 3.3 V ± 0.3 V, Ta = 25°C, f = 1 MHz)

Parameter

Symbol

Max.

Unit

Input Capacitance

Output Capacitance

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AC Characteristics

= 3.3 V ± 10%, Ta = 0 to 70°C)

MS81V06160-12

MS81V06160-15

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Access Time from SRCK

OUT

Hold Time from SRCK

DDCK

OUT

Enable Time from SRCK

DECK

SWCK "H" Pulse Width

WSWH

SWCK "L" Pulse Width

WSWL

Input Data Setup Time

Input Data Hold Time

1.5

WE Enable Setup Time

WENS

WE Enable Hold Time

WENH

1.5

WE Disable Setup Time

WDSS

WE Disable Hold Time

WDSH

1.5

IE Enable Setup Time

IENS

IE Enable Hold Time

IENH

1.5

IE Disable Setup Time

IDSS

IE Disable Hold Time

IDSH

1.5

WE "H" Pulse Width

WWEH

WE "L" Pulse Width

WWEL

IE "H" Pulse Width

WIEH

IE "L" Pulse Width

WIEL

RSTW Setup Time

RSTWS

RSTW Hold Time

RSTWH

1.5

SRCK "H" Pulse Width

WSRH

SRCK "L" Pulse Width

WSRL

RE Enable Setup Time

RENS

RE Enable Hold Time

RENH

1.5

RE Disable Setup Time

RDSS

RE Disable Hold Time

RDSH

1.5

OE Enable Setup Time

OENS

OE Enable Hold Time

OENH

1.5

OE Disable Setup Time

ODSS

OE Disable Hold Time

ODSH

1.5

RE "H" Pulse Width

WREH

RE "L" Pulse Width

WREL

OE "H" Pulse Width

WOEH

OE "L" Pulse Width

WOEL

RSTR Setup Time

RSTRS

RSTR Hold Time

RSTRH

1.5

SWCK Cycle Time

SWC

SRCK Cycle Time

SRC

Transition Time (Rise and Fall)

WE "L" Period before W Reset

LWE

clk

RE "L" Period before R Reset

LRE

clk

RE Delay after Reset

FRD

1,600

WE Delay after Reset

FWD

1,600

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Parameter

Symbol

MS81V06160-12, MS81V06160-15

Unit

Write Latency

clk

Read Latency

clk

WE Write Control Latency

WEL

clk

IE Write Control Latency

IEL

clk

RE Read Control Latency

REL

clk

OE Read Control Latency

OEL

clk

AC Characteristic Measuring Conditions

Output Compare Level

1.4 V

Output Load

1 TTL + 30 pF

Input Signal Level

3.0 V/0.0 V

Input Signal Rise/Fall Time

1 ns

Input Signal Measuring Reference Level

1.4 V

Note: Input voltage levels for the AC characteristic measurement are V

= 3.0 V and V

= 0 V.

When transition time t

becomes 1 ns or more, the input signal reference levels for the parameter

measurement are V

(min.) and V

(max.).

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MS81V06160

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OPERATION MODE

Write Operation Cycle
The write operation is controlled by four control signals, SWCK, RSTW, WE, and IE. The write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
RSTW must be performed for internal circuit initialization before write operation. WE must be low before and
after the reset cycle (t

LWE

+ t

FWD

Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles
while WE and IE are high.

Settings of WE and IE to the operation mode of Write address pointer and Data input.

Internal Write address pointer

Data input (Latency 2)

Input

Incremented

Halted

Not input

X indicates "don't care"

Read Operation Cycle
The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is
accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or
RSTR.
Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles
while RE and OE are high. RE must be low before and after the reset cycle (t

LRE

+ t

FWD

Settings of RE and OE to the operation mode of read address pointer and Data output.

Internal Read address pointer

Data output (Latency 2)

Output

Incremented

High impedance

Output

Halted

High impedance

Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 200

s after Vcc has stabilized to a

value within the range of recommended operating conditions. After this 200

s stabilization interval, the following

initialization sequence must be performed. Because the read and write address pointers are undefined after
power-up, a minimum of 330 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be
performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read
address pointer.

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Old/New Data Access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 70 SWCK
cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that
the first field will still be read out. The first field of data that is read out while the second field of data is written is
called "old data". In order to read out "new data", i.e., the second field written in, read reset must be input after
write address 200 the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles.
If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out
will be undetermined. It may be "old data" or "new" data, or a combination of old and new data. Such a timing
should be avoided.
When the read address delay is between more than 71 and less than 599 or more than 401,408, read data will be
undetermined. However, normal write is achieved in this address codition.