¡ Semiconductor

MSC1162A

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¡ Semiconductor

MSC1162A

40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver

GENERAL DESCRIPTION

The MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum
fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch
circuit, and 40-output circuit on a single chip.

Display data is serially stored in the shift register at the rising edge of a clock pulse.

Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to
set the display blanking.

Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high,
which provides the easy testing of all lights after final assembly of a VFD tube panel.

The MSC1162A is compatible with the MSC1162.

FEATURES

· Logic Supply Voltage

) : 5V

· Driver Supply Voltage (V

): 65V

· Driver Output Current

OHVH1

(Only one driver output : "H") : 40mA

OHVH2

(All the driver outputs : "H")

: 2mA

OHVL

:1mA

· Directly connected to VFD tube without pull-down resistors
· Data Transfer Speed: 4MHz
· Package :

60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK)

E2C0034-27-Y5

This version: Nov. 1997

Previous version: Jul. 1996

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MSC1162A

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PIN CONFIGURATION (TOP VIEW)

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

HVO 1
HVO 2
HVO 3
HVO 4
HVO 5
HVO 6
HVO 7
HVO 8
HVO 9
HVO 10
HVO 11
HVO 12
HVO 13
HVO 14
HVO 15
HVO 16

HVO 40
HVO 39
HVO 38
HVO 37
HVO 36
HVO 35
HVO 34
HVO 33
HVO 32
HVO 31
HVO 30
HVO 29
HVO 28
HVO 27
HVO 26
HVO 25

17
18
19
20

44
43
42
41

HVO 17
HVO 18
HVO 19
HVO 20

HVO 24
HVO 23
HVO 22
HVO 21

21
22
23
24
25
26

40
39
38
37
36
35

GND 1
GND 2

GND 1
GND 2
NC
CHG
NC

27
28
29
30

34
33
32
31

R/L

DIN

CLK
NC
DOUT
V

NC : No-connection pin

60-Pin Plastic SSOP

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MSC1162A

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PIN DESCRIPTION

Symbol

Description

CLK

Shift register clock input pin.
Shift register reads data through DIN while the CLK pin is low state and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.

Type

Serial data input pin of the shift register.
Display data (positive logic) is input in through the DIN pin synchronization with clock.

DIN

Serial data output pin of the shift register.
Data is output through the DOUT pin in synchronization with the CLK signal.
When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.
When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin.

DOUT

Latch strobe input pin
When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS
goes from high to low, the parallel output data (PO1-40) of the shift register is held.

Clear input pin with a built-in pull-up resistor
The CL pin is normally being set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high
irrespective of the states of the latch outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and latch outputs.
This allows display blanking to be set.

Input for testing (with a pull-down resistor)
The CL pin is normally being set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low
irrespective of the states of the latch outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
latch outputs.
This provides the easy testing of all lights after final assembly.

CHG

High voltage driver outputs for driving VFD tube
The driver outputs are in phase with the corresponding latch outputs (O1 to O40).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.

VHO1-40

Power supply pin for driver circuits of VFD tube

VHV

Power supply pin for logic

VCC

GND pin for driver circuits of a VFD tube. (D-GND)
Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.

GND1

GND pin for the logic circuits. (L-GND)
Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.

GND2

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MSC1162A

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Applicable to logic supply pin

Logic Supply Voltage

0.3 to +6.5

Applicable to driver supply pin

Driver Supply Voltage

0.3 to +70

Applicable to all input pins

Input Voltage

0.3 to V

+0.3

Applicable to data output pin

Output Voltage

0.3 to V

+0.3

Driver Driving Frequency

DRV

0 to 15

kHz

Applicable to driver output pin

860

Power Dissipation

Ta £ 25°C

Package Thermal Resistance

j-a

145

°C/W

Ta > 25°C

Storage Temperature

STG

55 to +150

°C

*1, *2

Withstand Output Voltage

*1, *2

HVO

0.3 to V

+0.3

Applicable to driver output pin

Notes: *1 Maximum Supply Voltage with respect to L-GND and D-GND

*2 Permanent damage may be caused if the voltage is supplied over the rating value.
*3 Package Thermal Resistance (between junction and ambient)

The junction temperature (Tj) expressed by the equation indicated below should not
exceed 150

=P ¥ R

+Ta (P: Maximum power consumption)

¡ Semiconductor

MSC1162A

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RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Max.

Unit

Applicable to logic supply voltage pin

Logic Supply Voltage

5.5

Min.

4.5

3.6

Applicable to driver supply voltage pin

Driver Supply Voltage

1.1

High Level Input Voltage

Low Level Input Voltage

High Level Driver Output
Current

Only one output is high

OHVH1

OHVH2

CLK Frequency

CLK

MHz

CLK Pulse Width

(CLK)

Data Setup Time

SU(D-CLK)

Data Hold Time

(CLK-D)

CLK-LS tsu

(CLK-LS)

LS-CLK tsu

(LS-CLK)

LS-CHG tsu

(LS-CHG)

LS-CL

tsu

(LS-CL)

Pulse Width

(CHG)

(CL)

Operating Temperature

°C

Low Level Driver Output
Current

Applicable to all driver output pins

OHVL

Applicable to all input pins

All outputs are high

Applicable to driver

output pin

Data Pulse Width

(D)

140

Latch Probe Pulse Width

(LS)

Setup Time

See timing diagram

CHG

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MSC1162A

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ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

Symbol

Condition

Max.

Unit

All input: Low

Logic Supply Current

CC1

6.65

Typ.

4.3

All input: High,

Ta=25°C

CC2

Min.

No load

=5.5V

1.0

0.5

All input: Low

Driver Supply Current

HV1

1.0

All input: High

Ta=25°C

HV2

No load

=5.5V

3.8

2.45

=5.5V, V

=5.5V

Inputs excluding CHG

High Level Input Current

Ta=25°C

Input Capacitance

=4.5V

3.5

=5.5V

4.5

High Level Data Output
Voltage

ODH

=4.5V

1.1

=5.5V

1.1

Low Level Data Output
Voltage

ODL

=0.1mA

High Level Driver Output
Voltage

=40mA

OHVH1

Low Level Driver Output
Voltage

=1mA

OHVL

3.0

=4.5 to 5.5V, V

=10 to 65V, Ta=40 to +85°C)

=5.5V, V

=5.5V

CHG input

=5.5V, V

=0V

Inputs excluding CL

Low Level Input Current

=5.5V, V

=0V

CL input

=2mA

OHVH2

AC Characteristics

Parameter

Symbol

Condition

Max.

Unit

Typ.

Min.

CLK-DOUT Delay Time

300

Delay Time Low to High

DLH

1.0

0.3

=5V, V

=65V, Ta=25°C)

Transit Time Low to High

TLH

5.0

2.0

Delay Time High to Low

DHL

1.0

0.3

Transit Time High to Low

THL

5.0

2.0

¡ Semiconductor

MSC1162A

11/14

FUNCTIONAL DESCRIPTION

Function Table

Shift register

Input

Shift Register Parallel Out

Output

CLK

R/L

DIN

PO1

PO39

PO2

PO40

DOUT

Not changed

PO38n

PO1n

PO39n

PO40

PO38n

PO1n

PO39n

PO40

PO2n

PO40n

PO3n

PO1

PO2n

PO40n

PO3n

PO1

Not changed

X: Don't Care
PO1n to PO40n : PO1 to PO40 data just before CLOCK rises.

Latch

Input

Shift Register Parallel Out

Latch Output

POm

Not changed

X: Don't Care, m: 1 to 40

Driver output

Input

Driver Output

HVOm

X: Don't Care, m: 1 to 40

Latch Output

CHG

¡ Semiconductor

MSC1162A

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NOTES ON USE

1. Connect GND1 to GND2 externally to be an equal potential voltage.

2. The contents of the shift register are undefined when the power is applied.

Therefore, unnecessary driver outputs may be driven high just after power-on, and
the VFD tube may flicker.

To avoid this, follow the procedures:

1) Apply the driver power supply after applying the logic power supply, with the

CL pin remained low.

2) Start displaying by setting the CL pin high after in putting display data the shift

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MSC1162A

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(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SSOP60-P-700-0.65-BK

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
1.21 TYP.

Mirror finish

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