¡ Semiconductor

MSC1201-xx

1/20

¡ Semiconductor

MSC1201-xx

60-Bit VFD Tube Driver with Digital Dimming and PWM Conversion Function

GENERAL DESCRIPTION

The MSC1201-xx is a 1/2 duty vacuum fluorescent display tube driver implemented in Bi-CMOS
technology. This LSI consists of 64-bit shift registers, 64 latches, PWM conversion circuit, a digital
dimming circuit, 30-segment driver and 2-grid driver. As the MSC1201-xx has both a digital
dimming circuit and a PWM conversion circuit which converts PWM signal for lamp dimming
control to PWM signal for VFD tube dimming control, the dimming control can be realized
without any external circuit.

The interface with a MCU can be done only with 3 wires (CS, DATA and CLOCK signals). Also,
DATA and CLOCK signal lines can be shared with other peripherals because of chip select
function by CS signal.

For the general purpose code, the code number is -01. (Product name: MSC1201-01GS-2K)

For a custom code, the code number will be ordered at any time.

FEATURES

· Single supply voltage : V

= 8 V to 18 V (built-in 5 V logic regurator)

· Operating temperature range : Ta = 40

C to +85

· 30-segment driver outputs (I

= 6 mA at V

= V

0.8 V)

· 2-grid pre-driver outputs (I

= 30 mA at V

= V

0.8 V)

· Built-in digital dimming circuit (11-bit resolution)
· Built-in oscillation circuit (external R and C, f

OSC

= 2.0 MHz)

· Built-in Power-On-Reset circuit.
· Lamp PWM signal Æ Buil-in PWM conversion circuit for vacuum fluorescent display tube.
· Built-in RC Oscillation (external R and C)
· Correspondence between shift register and output segment is settable optionally using built

in mask programmable 30 ¥ 30 PLA.

· Package :

44-pin plastic QFP (QFP44P910-0.802K)(Product name: MSC1201-xxGS-2K)

xx indicates the code number

E2C0017-27-Y2

This version: Nov. 1997

Previous version: Jul. 1996

¡ Semiconductor

MSC1201-xx

2/20

BLOCK DIAGRAM

SEG1

GND

TEST1

OSC0

OSC1

PWMIN

DATA

CLOCK

5 V

POR

SEG30

GRID1

GRID2

DATA OUT

INH

S3 S4

D
CK

OSC

Timing Generator

Digital Dimming Circuit

Selector

64-Bit Shift Register

M3 M2 M1 M0

Latch

Multiplexer

¥ 30 PLA Matrix

30-Segment Driver

Control

Circuit

5 V Reg

POR Circuit

PWM Conversion Circuit

S2 S3 S4

Mode Selector

Test Mode

2-Grid Driver

D48-59

POR

¡ Semiconductor

MSC1201-xx

3/20

INPUT AND OUTPUT CONFIGURATION

· Schematic Diagrams of Logic Portion Input

Circuit 1

· Schematic Diagrams of Logic Portion Input

Circuit 1

· Schematic Diagrams of Logic Portion Output

Circuit

· Schematic Diagrams of Driver Output Circuit

GND

INPUT

(5V Reg.)

GND

(5V Reg.)

GND

INH

TEST1

GND

(5V Reg.)

GND

OUTPUT

(5V Reg.)

GND

OUTPUT

¡ Semiconductor

MSC1201-xx

4/20

PIN CONFIGURATION (TOP VIEW)

SEG11

DATAOUT

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

GRID2

GRID1

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

PWM IN

INH

DATA

CLOCK

GND

OSC0

OSC1

TEST1

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

44-Pin Plastic Package

¡ Semiconductor

MSC1201-xx

5/20

PIN DESCRIPTIONS

Power Supply

Dimming select input. When the high level is input, daylight-mode output duty cycle
is about 100% for each grid time for PWM conversion and digital dimming mode.
When the low level is input, the dark-mode output duty cycle is determined by the
duty cycle of the PWM signal input to PWM IN and the digital dimming output duty
cycle is determined by digital dimming data.

Serial clock input. Data that is input through "DATA" pin is input and output by
synchronization with the rising edge of the serial clock.

Chip select input. Only when the high level is input to this pin, interfacing with a MCU
is available through "CLOCK" and "DATA" pins.
Therefore, 2-signal lines of "CLOCK" and "DATA" can be shared with other peripherals.

CLOCK

INH

TEST1

Serial data output. Data is shifted out at the rising edge of the serial clock with the
delay of 64-bit time. This pin is used for cascading this LSI with other drivers such
as a LED driver.

PWM signal input.

Pin

Symbol

GND

Description

Segment output pin for VFD

Input which receives display data and digital dimming data from a MCU. Data is
shifted in at the rising edge of the shift clock.

OSC1

SEG1-30

I/O

Ground

GRID1, 2

Grid 1 and Grid 2 output pins for VFD

OSC0

RC oscillation pins. Connect a resistor between OSC1 and OSC0 pin and a capacitor
between OSC0 and GND pin.

DATA

Test signal input pin. As this pin is used for shipping test of the LSI, leave open in the
normal operation mode.

DATA

OUT

PWMIN

Blank Display input with a built-in pull-up resistor. When set to "L", all the drivers
output "L". When display duly is not controlled by this signal, leave this pin open.

1-9

24-44

10, 11

¡ Semiconductor

MSC1201-xx

6/20

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Supply Voltage

0.3 to +20

All inputs

Input Voltage

0.3 to +6

Storage Temperature Range

STG

65 to +150

°C

Ta = 85°C

Power Dissipation

0.4

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Max.

Unit

Supply Voltage

Typ.

All inputs except OSC0, VK

High Level Input Voltage (1)

IH1

5.5

Min.

3.8

High Level Input Voltage (2)

IH2

3.8

OSC0

High Level Input Voltage (3)

IH3

5.5

4.5

All inputs except OSC0

Low Level Input Voltage (1)

IL1

0.8

OSC0

Low Level Input Voltage (2)

IL2

0.5

Clock Frequency

250

kHz

R = 4.7k

W, C=22pF

OSC Frequency

OSC

MHz

OSC

= 2 MHz

Frame Frequency

224

Operating Temperature Range

°C

¡ Semiconductor

MSC1201-xx

7/20

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

Hight Level Input Voltage (1)

Symbol

Min.

Unit

IH1

IL1

3.8

Max.

5.5

0.8

5.5

Low Level Input Voltage (1)

Condition

IH1

= 5.0 V

3.8

4.5

-0.8

4.5

0.3

0.1

0.5

OSC

= 2 MHz, No load

Hight Level Input Voltage (2)

Hight Level Input Voltage (3)

Hight Level Input Current (1)

Low Level Input Voltage (2)

Hight Level Input Current (2)

Hight Level Input Current (3)

Low Level Input Current (1)

Low Level Input Current (2)

Low Level Input Current (3)

High Level Output Voltage (1)

Low Level Output Voltage (1)

High Level Output Voltage (3)

Low Level Output Voltage (2)

IH2

= 5.0 V

IH3

= 5.0 V

IL1

= 0.0 V

IL2

= 0.0 V

IL3

= 0.0 V

= 9.5 V

OH1

= 6 mA

= 9.5 V

OH3-1

= 200

= 9.5 V

OL1-1

= 500

= 9.5 V

OL2

= 200

Power Supply Current

IH2

IH3

IL2

IH1

IH2

IH3

IL1

IL2

IL3

OH1

OL1-2

OL2

0.6

320

0.8

(Ta = 40 to +85°C, V

= 8 to 18 V)

*10

High Level Output Voltage (2)

OH2

= 9.5 V

OH2

= 30 mA

-0.8

OH3-1

OH3-2

OL1-1

OL1-3

= 9.5 V

Output Open

= 9.5 V

OL1-2

= 200

= 9.5 V

OL1-3

= 2

Notes: *1 Applicable to all input pins (except VK, OSC0 pin)

*2 Applicable to OSC0 pin
*3 Applicable to CLOCK, DATA, CS, VK, and PWMIN pin
*4 Applicable to TEST1
*5 Applicable to INH pin
*6 Applicable to pins SEG1 to SEG30
*7 Applicable to GRID1 and GRID2
*8 Applicable to DATA OUT pin
*9 Applicable to VK pin

*10 Applicable to all input pins (except OSC0 pin)

¡ Semiconductor

MSC1201-xx

8/20

AC Characteristics

Parameter

Symbol

Condition

Max.

Unit

R = 4.7k

W, C = 22pF

Oscillation Frequency

OSC

2.8

MHz

Min.

1.2

(Ta = 40 to +85°C, V

= 8 to 18 V)

Clock Frequency

250

kHz

Clock Pulse Width

1.3

Data Set-up Time

Data Hold Time

200

CS Pulse Width

CSW

CS Off Time

CSL

CS Set-up Time
CS-Clock Time

CSS

CS Hold Time
Clock-CS Time

CSH

Data Output Delay
Clock-Data out Time

= 100pF

SEG & GRID Output Delay
from CS

ODS

= 100pF, t = 20% to 80% or

80% to 20%

Slew Rate (All Drivers)

Power-on CS Time

PCS

300

Frame Frequency

342

146

External input only

OSC0 Input Frequency

OSCI

2.5

MHz

1.5

When the Unit mounted

= 0 V

Power-off Hold Time

POF

When the Unit mounted

Power-on Rise Time

PRZ

100

PWM Conversion Characteristics

Parameter

PWM Input Frequency

Input Threshold Voltage

Symbol

Condition

Unit

PWM

PWM Input Duty Cycle

Min.

176

0.8

Typ.

256

2.5

Max.

336

3.8

100

(Ta = 40 to +85°C, V

= 8 to 18 V)

¡ Semiconductor

MSC1201-xx

10/20

TIMING DIAGRAM (Continued)

3.8V

0.8V

PCS

POF

PRZ

Fig. 3 Power-On Timing

PWMIN

PWM Frequency (f

PWM

)

Duty Cycle d

= A/(A+B)

Input
Threshold
Voltage

Fig. 5 PWM Input Waveform

SEG1-30
GRID1, 2

CSW

ODS

3.8V

ODS

0.8V

80%

20%

Fig. 4 SEG & GRID Driver Output Timing

¡ Semiconductor

MSC1201-xx

11/20

FUNCTIONAL DESCRIPTION

Power-On-Reset

The status of the internal circuit after power-on reset is as follows;
1) Shift registers and latches are reset.
2) PWM conversion mode is selected.

DATA Input

Data input is available only when the high level is applied to the "CS" pin. Input data is shifted
into shift registers through "Data" pin at the rising edge of the shift clock. The data is
automatically loaded to latches at the falling edge of "CS" signal. When M0 = "0", input data
should include display data (total of 64 bits data should be input.) and when M0 = "1", input data
should exclude display data (Total of 16-bit data shoul

d be input.)

[Data Format]

1) Display Data Input Mode

Input Data

: 64 bits

VF Display Data

: 60 bits

Mode Select Data

: 4 bits

2) Segment outputs/Shift Registers Bit Correspondence Table
The content of the table depends on a PLA code.
This table is modeled on the general purpose code of -01.
Segment output positions can be changed dependent on the PLA code, but the segment-bit
correspondence cannot be changed.

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

Bit

SEGn

GRID1

GRID2

D59

D58

D57

D48

D47

Display

Data

Mode

Data

Display

Data

Bit

First In

¡ Semiconductor

MSC1201-xx

12/20

3) Digital Dimming Data Input Mode

Input Data

: 16 bits

Digital Dimming Data

: 11 bits

Mode Select Data

: 4 bits

First in

Bit

MSB

DUTY CYCLE

0/2048

1/2048

2032/2048

(MSB)

INPUT DATA

(LSB)

Dimming Data

LSB

Mode Data

4) Function Mode

Function

Display Data Input

Digital Dimming Data Input

Digital Dimming Select & Display Data Input

Digital Dimming Select

PWM Conversion Select & Display Data Input

PWM Conversion Select

Mode

¡ Semiconductor

MSC1201-xx

13/20

PWM Conversion

In the PWM conversion mode, "lamp PWM", which is used for dimming control of back-light for
instrument clusters or other displays, is used to generate the PWM signal for VFD tube dimming
control. The lamp PWM input to "PWM IN" pin is converted to PWM signal for VFD tube with
a built-in PWM conversion look-up table (User-Programmable Mask ROM).
The duty

cycle of the lamp PWM is defined as follows:

PWMIN

PWM Input Frequency = 256 ± 80Hz
Duty Cycle = A / (A+B)

Note: The duty cycle of the lamp PWM signal is measured with a reference point of 2.5 V typ.

As the reference point of 2.5 V is the threshold voltage of "PWM IN" pin, it deviates to
some value between 0.8 V and 3.8 V due to process parameter deviation. Therefore, the
PWM conversion error increases as the rise/fall time of the lamp PWM increases.

GRID/SEG Driver Operation and Digital/Analog Dimming Operation

Figure 6 shows an output timing of the GRID and SEG Driver when the VK is "H" level.
Output timings of the GRID and SEG drivers are shown in figure 7 for the digital dimming mode
operation in figure 8 for the PWM conversion mode operation.

(1) GRID and SEG drivers output timings when VK = "H"

GRID1

GRID2

SEG1-30

1 Frame (4096-bit times)

16-bit times

2032-bit times

6-bit times

2038-bit times

10-bit times

Fig. 6 GRID and SEG Output Timing (VK = "H")

Note: One bit time = 2/f

OSC

= 1 ms typ.

¡ Semiconductor

MSC1201-xx

14/20

(2) GRID and SEG driver output timing when VK = "L" and in Digital Dimming Mode.

Fig. 8 GRID and SEG Driver Output Timing (PWM conversion mode)

Notes: · The above indicates the GRID and SEG Drivers Timing when the PWM conversion

mode at VK = "L" level is selected.

· One bit time = 4/f

OSC

= 2 ms typ.

GRID1

GRID2

SEG1-30

1 Frame (4096-bit times)

Max.
2032-bit times

6-bit times

16-bit times

Max.
2038-bit times

10-bit times

Fig. 7 GRID and SEG Output Timing (digital dimming mode)

Notes: · The above indicates the timing for the digital dimming mode with the duty cycle of

2032/2048 at V

PARK

= "L" level.

· The On-times for GRID and SEG are specified with the 11 bits of the digital dimming

data.

· One bit time = 2/f

OSC

= 1 ms typ.

(3) GRID and SEG driver output timings when VK = "L" and in PWM Conversion Mode

1 Frame (2048-bit times)

Max.
256-bit times

3-bit times

8-bit times

GRID1

GRID2

SEG1-30

Max.
259-bit times

¡ Semiconductor

MSC1201-xx

15/20

PWM Conversion Table

MSC1201-01

LAMP PWM

DUTY CYCLE

12.50%

100.00%

98.75%

97.50%

96.25%

95.00%

93.75%

92.50%

91.25%

90.00%

88.75%

87.50%

86.25%

85.00%

83.75%

82.50%

81.25%

80.00%

78.75%

77.50%

76.25%

75.00%

73.75%

72.50%

71.25%

70.00%

68.75%

STEP No.

VF PWM

DUTY CYCLE

LAMP PWM

DUTY CYCLE

VF PWM

DUTY CYCLE

67.50%

66.25%

65.00%

63.75%

62.50%

61.25%

60.00%

58.75%

57.50%

56.25%

55.00%

53.75%

52.50%

51.25%

50.00%

48.75%

47.50%

46.25%

45.00%

43.75%

42.50%

41.25%

40.00%

38.75%

37.50%

36.25%

35.00%

33.75%

32.50%

31.25%

30.00%

28.75%

27.50%

26.25%

25.00%

23.75%

22.50%

21.25%

20.00%

STEP No.

12.30%

12.11%

11.91%

11.72%

11.52%

11.33%

11.13%

10.94%

10.74%

10.55%

10.35%

10.16%

9.96%

9.77%

9.57%

9.38%

9.18%

8.98%

8.79%

8.59%

8.40%

8.20%

8.01%

7.81%

7.62%

7.42%

7.23%

7.03%

6.84%

6.64%

6.45%

6.25%

6.05%

5.86%

5.66%

5.47%

5.27%

5.08%

4.88%

4.69%

4.49%

4.30%

4.10%

3.91%

3.71%

3.52%

3.32%

3.13%

2.93%

2.73%

2.54%

2.34%

2.15%

1.95%

1.76%

1.56%

1.37%

1.17%

0.98%

0.78%

0.59%

0.39%

0.20%

0.10%

¡ Semiconductor

MSC1201-xx

16/20

PLA Code Table

MSC1201-01

SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
SEG 24
SEG 25
SEG 26
SEG 27
SEG 28
SEG 29
SEG 30

PIN 24
PIN 25
PIN 26
PIN 27
PIN 28
PIN 29
PIN 30
PIN 31
PIN 32
PIN 33
PIN 34
PIN 35
PIN 36
PIN 37
PIN 38
PIN 39
PIN 40
PIN 41
PIN 42
PIN 43
PIN 44
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9

BIT 1, 31

BIT 2, 32

BIT 3, 33

BIT 4, 34

BIT 5, 35

BIT 6, 36

BIT 7, 37

BIT 8, 38

BIT 9, 39

BIT10, 40

BIT11, 41

BIT12, 42

BIT13, 43

BIT14, 44

BIT15, 45

BIT16, 46

BIT17, 47

BIT18, 48

BIT19, 49

BIT20, 50

BIT21, 51

BIT22, 52

BIT23, 53

BIT24, 54

BIT25, 55

BIT26, 56

BIT27, 57

BIT28, 58

BIT29, 59

BIT30, 60

¡ Semiconductor

MSC1201-xx

17/20

Pin Name

Output

Pin Name

Output

SEG1

BIT 1,31

SEG16

BIT 16,46

SEG2

BIT 2,32

SEG17

BIT 17,47

SEG3

BIT 3,33

SEG18

BIT 18,48

SEG4

BIT 4,34

SEG19

BIT 19,49

SEG5

BIT 5,35

SEG20

BIT 20,50

SEG6

BIT 6,36

SEG21

BIT 21,51

SEG7

BIT 7,37

SEG22

BIT 22,52

SEG8

BIT 8,38

SEG23

BIT 23,53

SEG9

BIT 9,39

SEG24

BIT 24,54

SEG10

BIT 10,40

SEG25

BIT 25,55

SEG11

BIT 11,41

SEG26

BIT 26,56

SEG12

BIT 12,42

SEG27

BIT 27,57

SEG13

BIT 13,43

SEG28

BIT 28,58

SEG14

BIT 14,44

SEG29

BIT 29,59

SEG15

BIT 15,45

SEG30

BIT 30,60

¡ Semiconductor

MSC1201-xx

20/20

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

mm or more

0.41 TYP.

QFP44-P-910-0.80-2K

Mirror finish

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSC1201

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSC1201