Semiconductor
MSC1212-01
1/12
FEDL1212-01-03
Semiconductor
MSC1212-01
48-Bit Grid/Anode Driver
GENERAL DESCRIPTION
The MSC1212-01 is a driver IC for VFD implemented in BiCMOS technology.
The circuit consists of a 48-bit shift register and a 48-bit latch; they control display data, which
is output from the display drivers.
Since a 64-pin plastic QFP package is used, the display unit size can be reduced.
FEATURES
Logic supply voltage (V
CC
)
: 4.5 to 5.5 V
Driver supply voltage (V
DISP
)
: 8 to 18 V
Operating temperature range
: 40 to +105
C
Driver output current
: I
O2-1
= 6 mA (for only one driver on state)
I
O2-2
= 50 mA (total current for all drivers on
state)
I
O2-3
= 0.2 mA
Built-in 48-bit output Driver (with latch)
Built-in 48-bit shift register
Clock frequency
: 0.5 MHz
Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSC1212-01GS-BK)
FEDL1212-01-03
This version: Sep. 2001
Previous version: Nov. 1997
Semiconductor
MSC1212-01
2/12
FEDL1212-01-03
BLOCK DIAGRAM
V
DISP
V
CC
CL
CHG
LS
DIN
CLK
L-GND
D-GND
48-BIT
S/R
I1 O1
48-BIT
LATCH
HVO 1
HVO48
DOUT
V
CC
L
O48
I48
SO
PO48
PO1
C
SI
Semiconductor
MSC1212-01
3/12
FEDL1212-01-03
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
HVO 18
HVO 19
HVO 20
HVO 21
HVO 22
HVO 23
HVO 24
HVO 25
HVO 26
HVO 27
HVO 28
HVO 29
HVO 30
HVO 31
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HVO 32
HVO 33
HVO 34
HVO 35
HVO 36
HVO 37
HVO 38
HVO 39
HVO 40
HVO 41
HVO 42
HVO 43
HVO 44
HVO 45
HVO 46
HVO 47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HVO1
NC
V
DISP
D-GND
L-GND
DIN
CLK
LS
CL
CHG
V
CC
DOUT
D-GND
V
DISP
NC
HVO 48
HVO 17
HVO 16
HVO 15
HVO 14
HVO 13
HVO 12
HVO 11
HVO 10
HVO 9
HVO 8
HVO 7
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
NC: No-connection pin
64-Pin Plastic QFP
Semiconductor
MSC1212-01
4/12
FEDL1212-01-03
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input Circuit
Schematic Diagrams of Logic Portion Input
Circuit (Pull-down)
Schematic Diagrams of Driver Output Circuit
GND
V
CC
V
DISP
GND
INPUT
Schematic Diagrams of Logic Portion Input
Circuit (Pull-up)
GND
V
CC
V
DISP
GND
INPUT
GND
V
CC
V
DISP
GND
INPUT
Schematic Diagrams of Logic Portion Output
Circuit
GND
V
CC
GND
OUTPUT
V
CC
GND
V
DISP
GND
OUTPUT
V
DISP
Semiconductor
MSC1212-01
5/12
FEDL1212-01-03
PIN DESCRIPTION
Pin
1 to 17
32 to 48
50 to 63
19, 30
27
20, 29
21
22
23
24
25
26
Symbol
HVO1
to
HVO48
V
DISP
V
CC
D-GND
L-GND
DIN
CLK
LS
CL
CHG
Function
Driver Output
Driver Power Supply
Logic Power Supply
Driver GND
Logic GND
Data Input
Clock Input
Latch Strobe Input
Clear Input
Test Input
Description
Driver output pins, applicable to each bit of shift
register.
Power supply pins for driver circuit. Both Pin 19
and 30 should be connected externally.
Power supply pin for logic.
GND pins for the driver circuit.
Both Pin 20 and 29 should be connected externally.
GND pin for the logic circuit.
Input pin without pull-up or pull-down resistor.
Input pin of shift register. Display data input is
synchronized with clock signal. (positive logic)
Input pin without pull-up or pull-down resistor.
Data of shift register is shifted from one stage to
the next on application of each clock rising edge.
Input pin without pull-up or pull-down resistor.
When LS is at "H" level, the latch is shunted and the
shift register output becomes the lacth output.
When LS is at "L" level, the lacth holds the shift
register output just bafore LS goes to "L" level.
Clear input pin with pull-up resistor. Normally "L"
level. In this condition, driver output changes to "H"
or "L" according to latch output level. When CL is
"H", all driver output pins are fixed to "L".
Test input pin with pull-down resistor. Normally "L"
level, but here, if CL="H", then driver output changes
to "H" or "L" according to latch output level.
If CL = "L" when CHG is at "H" level, all driver output
is fixed to "H" for test.
28
DOUT
Data Output
Serial output pin of shift register.
Semiconductor
MSC1212-01
6/12
FEDL1212-01-03
ABSOLUTE MAXIMUM RATINGS
*1 Maximum supply voltage with respect to L-GND and D-GND
*2 Catastrophic breakdown may occur if the applied voltage is more than the rating.
*3 Thermal resistance of package (between junction and atmosphere)
The junction temperature (T
j
) given by the following formula should not exceed 150
C.
T
j
= P R
j-a
+ Ta (P is the maximum power dissipation)
Condition
V
CC
0.3 to +6.5
V
Parameter
Symbol
Rating
Unit
Logic Supply Voltage
V
DISP
0.3 to +20
V
Driver Supply Voltage
V
IN
0.3 to V
CC
+0.3
V
Applicable to all input pins
Input Voltage
V
O1
0.3 to V
CC
+0.3
V
Applicable to data output pin
Data Output Voltage
V
O2
0.3 to V
DISP
+0.3
V
Applicable to driver output pin
Driver Output Voltage
P
D
1.0
W
Ta 25
C
Power Dissipation
R
j-a
120
C/W
Thermal Resistance
T
STG
55 to +150
C
--
Storage Temperature
*1
*1, *2
*1
*1
*1
*3
--
--
--
Semiconductor
MSC1212-01
7/12
FEDL1212-01-03
RECOMMENDED OPERATING CONDITIONS
Condition
V
CC
V
DISP
V
IH
V
IL
I
O1
I
O2-1
I
O2-2
I
O2-3
f
CLK
t
DS
t
DH
t
WLS
t
WCHG
t
WCL
t
WCLK
t
DCLK-LS
t
DLS-CLK
t
DLS-CHG
t
DLS-CL
T
op
4.5
8
0.8 V
CC
--
0.1
--
--
--
--
400
300
125
10
10
500
525
0
0
0
40
V
V
V
V
mA
mA
mA
mA
MHz
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
C
Parameter
Symbol
Min.
Unit
5.5
18
--
0.2 V
CC
0.1
6
50
0.2
0.5
--
--
--
--
--
--
--
--
--
--
105
Max.
Logic Supply Voltage
Applicable to logic supply voltage pin
Driver Supply Voltage
Applicable to driver supply voltage pin
High Level Input Voltage
Applicable to all input pins
Applicable to all input pins
Logic Output Current
Applicable to DOUT pin
Driver High Level Output Current
Only one driver is ON state
Total current at all driver outputs
are ON state
Driver Low Level Output Current
Applicable to all driver output pins
CLK Frequency
See Timing Diagram
Data Setup Time
See Timing Diagram
Data Hold Time
See Timing Diagram
LS Pulse Width
See Timing Diagram
CHG Pulse Width
See Timing Diagram
CL Pulse Width
See Timing Diagram
CLK Pulse Width
See Timing Diagram
CLK-LS Delay Time
See Timing Diagram
LS-CLK Delay Time
See Timing Diagram
LS-CHG Delay Time
See Timing Diagram
LS-CL Delay Time
See Timing Diagram
Low Level Input Voltage
Operating Temperature
--
Semiconductor
MSC1212-01
8/12
FEDL1212-01-03
ELECTRICAL CHARACTERISTICS
DC Characteristics
*1 Pin D-GND and Pin L-GND are not connected internally.
Therefore, set the voltage between D-GND and L-GND at the same level by connecting both
pins externally.
AC Characteristics
Condition
t
PD
t
DLH
t
TLH
t
DHL
t
THL
1.6
2.0
5.0
2.0
5.0
Parameter
Symbol
Max.
ms
ms
ms
ms
ms
Unit
See Timing Diagram
See Timing Diagram
See Timing Diagram
See Timing Diagram
See Timing Diagram
CLK-Dout Delay Time
Delay Time Low High
Transit Time Low High
Delay Time High Low
Transit Time High Low
(V
CC
= 4.5 to 5.5 V, V
DISP
= 8 to 18 V, Ta = 40 to +105
C)
--
1.0
2.0
1.0
2.0
Typ.
0.3
--
--
--
--
Min.
Condition
I
CC1
4
6
5
--
--
2.1
2.6
--
600
1
100
1
--
--
--
--
0.1
Parameter
Symbol
Max.
mA
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
V
Unit
No Load
All input pins
All input pins
All input pins
V
I
= V
CC
V
I
= 0V
V
CC
V
OH1
=
1.0 V
V
OL1
=
1.0 V
Only one driver is ON state
V
DISP
V
OH2
= 1.0 V
V
OL2
=
1.0 V
Voltage difference between
D-GND and L-GND
*1
Logic Power Supply
Current
Driver Power Supply
Current
High Level Input
Threshold Voltage
Low Level Input
Threshold Voltage
Hysteresis Voltage
High Level Input
Current
Low Level Input
Current
High Level Data
Output Current
Low Level Data
Output Current
Driver High Level
Output Current
Driver Low Level
Output Current
Voltage Difference
Between GND Pins
(V
CC
= 4.5 to 5.5 V, V
DISP
= 8 to 18 V, Ta = 40 to +105
C)
2
4
--
2.75
3.25
1.75
2.25
1
--
--
--
--
--
--
--
--
0
Typ.
--
--
--
2.4
2.9
--
--
0.3
100
1
600
1
0.1
0.1
6
0.2
0.1
Min.
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 4.5 V
V
CC
= 5.5 V
CHG pin
Input pins except CHG pin
CL pin
Input pins except CL pin
f
CLK
= 0 Hz
f
CLK
= 0.5 MHz
No Load
mA
I
CC2
I
DISP
V
P
V
N
V
H
I
IH1
I
IH2
I
IL1
I
IL2
I
OH1
I
OL1
I
OH2
I
OL2
V
GND
Semiconductor
MSC1212-01
9/12
FEDL1212-01-03
TIMING DIAGRAM
CLK
DIN
DOUT
LS
CHG
CL
HVO (1, 2, 47, and 48)
HVO (Others)
t
WCLK
1/f
CLK
t
DS
t
DH
T1/2
T3/4
T47/48
T1/2
T3/4
t
PD
t
PD
t
DCLK-LS
t
DLS-CLK
t
WLS
t
DLS-CHG
t
WCHG
t
WCHG
t
DLS-CL
t
DLH
t
DLH
t
DHL
t
DHL
t
WCL
t
WCL
t
TLH
t
TLH
t
THL
t
THL
Semiconductor
MSC1212-01
10/12
FEDL1212-01-03
FUNCTIONAL DESCRIPTION
Function Table
L
: Low Level, H: High Level, X: Don't Care, NC: No Change
CLOCK
DIN
H
L
PO1
H
L
PO2
PO1k
PO1k
PO3
PO2k
PO2k
PO4
PO3k
PO3k
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
CL
H
L
L
L
L
CHG
X
H
L
L
L
LS
X
X
H
H
L
POn
X
X
H
L
X
HVOn
L
H
H
L
NC
PO46
PO45k
PO45k
PO47
PO46k
PO47k
PO48
PO47k
PO47k
DOUT
PO47k
PO47k
Semiconductor
MSC1212-01
11/12
FEDL1212-01-03
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
QFP64-P-1414-0.80-BK
Package material
Lead frame material
Pin treatment
Package weight (g)
Oki Electric Industry Co., Ltd.
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (5 mm)
0.87 TYP.
6/Feb. 23, 2001
Mirror finish
Semiconductor
MSC1212-01
12/12
FEDL1212-01-03
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
Printed in Japan
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