1
Semiconductor
MSC2313258A-xxBS2/DS2
53
Semiconductor
MSC2313258A-xxBS2/DS2
1,048,576-Word
32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The Oki MSC2313258A-xxBS2/DS2 is a fully decoded 1,048,576-word 32-bit CMOS dynamic
random access memory composed of two 16-Mb (1M 16) DRAMs in SOJ. The mounting of two
DRAMs together with decoupling capacitors on a 72-pin glass epoxy SIMM Package supports
any application where high density and large capacity of storage memory are required.
FEATURES
1,048,576-word 32-bit organization
72-pin SIMM
MSC2313258A-xxBS2
: Gold tab
MSC2313258A-xxDS2 : Solder tab
Single 5 V supply
10% tolerance
Input
: TTL compatible
Output : TTL compatible, 3-state, nonlatch
Refresh : 1024 cycles/16 ms
CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
Fast Page Mode with EDO capability
PRODUCT FAMILY
Family
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Operating (Max.) Standby (Max.)
t
RAC
MSC2313258A-70BS2/DS2
2200 mW
11 mW
t
AA
t
CAC
70 ns
35 ns
20 ns
130 ns
MSC2313258A-60BS2/DS2
2420 mW
60 ns
30 ns
15 ns
110 ns
MSC2313258A-xxBS2/DS2
Semiconductor
54
PIN CONFIGURATION
Typ.
10.16
Typ.
6.35
101.19 Typ.
3.38 Typ.
107.95 0.2
1.04 Typ.
95.25
2.03 Typ.
1.27
+0.1
0.08
5.28 Max.
3.18
f
1.27 0.2
72
1
* 1
6.35
R1.57
19.0 0.2
6.0 Min.
6.35 Typ.
*1 The common size difference of the board width 12.5 mm of its height is
specified as 0.2. The value above 12.5 mm is specified as 0.5.
(Unit : mm)
Pin No. Pin Name
Pin No. Pin Name
Pin No. Pin Name
1
V
SS
16
A4
31
A8
Pin No. Pin Name
46
NC
Pin No.
Pin Name
67
PD1
Pin No. Pin Name
61
DQ13
2
DQ0
17
A5
32
A9
47
WE
62
DQ30
3
DQ16
18
A6
33
NC
48
NC
63
DQ14
4
DQ1
19
NC
34
RAS2
49
DQ8
64
DQ31
5
DQ17
20
DQ4
35
NC
50
DQ24
65
DQ15
6
DQ2
21
DQ20
36
NC
51
DQ9
66
NC
7
DQ18
22
DQ5
37
NC
52
DQ25
67
PD1
8
DQ3
23
DQ21
38
NC
53
DQ10
68
PD2
9
DQ19
24
DQ6
39
V
SS
54
DQ26
69
PD3
10
V
CC
25
DQ22
40
CAS0
55
DQ11
70
PD4
11
NC
26
DQ7
41
CAS2
56
DQ27
71
NC
12
A0
27
DQ23
42
CAS3
57
DQ12
72
V
SS
13
A1
28
A7
43
CAS1
58
DQ28
14
A2
29
NC
44
RAS0
59
V
CC
15
A3
30
Vcc
45
NC
60
DQ29
68
PD2
69
PD3
70
PD4
-70BS2/DS2
V
SS
V
SS
V
SS
NC
-60BS2/DS2
V
SS
V
SS
NC
NC
MSC2313258A
MSC2313258A
Presence Detect Pins
MSC2313258A-xxBS2/DS2
1
Semiconductor
MSC2313258A-xxBS2/DS2
55
BLOCK DIAGRAM
A0 - A9
RAS0
CAS0
CAS1
WE
V
CC
V
SS
A0 - A9
RAS
LCAS
UCAS
WE
V
SS
V
CC
DQ1
DQ15
C4
C1
DQ0
DQ1
DQ2
DQ0
DQ2
OE
DQ15
DQ17
DQ31
DQ16
DQ18
RAS2
CAS2
CAS3
A0 - A9
RAS
LCAS
UCAS
WE
V
SS
V
CC
DQ0
DQ1
DQ2
OE
DQ15
MSC2313258A-xxBS2/DS2
Semiconductor
56
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Unit
Power Supply Voltage
V
CC
Input High Voltage
Typ.
Min.
Max.
4.5
5.0
5.5
V
(Ta = 0C to 70C)
V
SS
0
0
0
V
V
IH
2.4
--
6.5
V
V
IL
1.0
--
0.8
V
Input Low Voltage
Capacitance
Parameter
Symbol
Unit
C
IN1
pF
Input Capacitance (A0 - A9)
Typ.
Max.
--
16
(Ta = 25C, f = 1 MHz)
C
IN2
pF
Input Capacitance (WE)
--
20
C
IN3
pF
Input Capacitance (RAS0, RAS2)
--
13
C
IN4
pF
Input Capacitance (CAS0 - CAS3)
--
13
C
DQ
pF
I/O Capacitance (DQ0 - DQ31)
--
13
Note :
Capacitance measured with Boonton Meter.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
, V
OUT
1.0 to 7.0
V
Voltage V
CC
Supply Relative to V
SS
V
CC
1.0 to 7.0
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
2.6
W
Operating Temperature
T
opr
0 to 70
C
Storage Temperature
T
stg
40 to 125
C
1
Semiconductor
MSC2313258A-xxBS2/DS2
57
DC Characteristics
All other pins not
Parameter
MSC2313258A
Unit
Condition
Input Leakage Current
Note
I
LI
A
1, 2
(V
CC
= 5 V 10%, Ta = 0C to 70C)
Symbol
0 V V
I
6.5 V;
under test = 0 V
D
OUT
disable
0 V V
O
5.5 V
I
OH
= 5.0 mA
I
OL
= 4.2 mA
RAS, CAS cycling,
t
RC
= Min.
RAS, CAS = V
IH
RAS, CAS
V
CC
0.2 V
RAS cycling,
CAS = V
IH
,
t
RC
= Min.
RAS cycling,
CAS before RAS,
t
RC
= Min.
RAS = V
IL
,
CAS cycling,
t
HPC
= Min.
Output Leakage Current
Output High Voltage
Output Low Voltage
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Supply Current
(RAS-only Refresh)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
I
LO
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC6
I
CC7
A
V
V
mA
mA
mA
mA
mA
mA
Min.
20
10
2.4
0
--
--
--
--
--
--
Max.
20
10
V
CC
0.4
400
4
2
400
400
400
1
1
1, 2
1, 2
1, 3
-70BS2/DS2
Min.
20
10
2.4
0
--
--
--
--
--
--
Max.
20
10
V
CC
0.4
440
4
2
440
440
440
MSC2313258A
-60BS2/DS2
Notes:
1. I
CC
Max. is specified as I
CC
for output open condition.
2. Address can be changed once or less while RAS=V
IL
.
3. Address can be changed once or less while CAS=V
IH
.
MSC2313258A-xxBS2/DS2
Semiconductor
58
AC Characteristics (1/2)
Parameter
Symbol
Unit
Random Read or Write Cycle Time
Note
(V
CC
= 5 V 10%, Ta = 0C to 70C) Note 1,2,3
t
RC
ns
MSC2313258A
Fast Page Mode Cycle Time
t
HPC
ns
Access Time from RAS
t
RAC
ns
Access Time from CAS
t
CAC
ns
Access Time from Column Address
t
AA
ns
Access Time from CAS Precharge
t
CPA
ns
Output Low Impedance Time from CAS
t
CLZ
ns
CAS to Data Output Buffer Turn-off Delay Time
t
CEZ
ns
Transition Time
t
T
ns
Refresh Period
t
REF
ms
RAS Precharge Time
t
RP
ns
RAS Pulse Width
t
RAS
ns
RAS Pulse Width (Fast Page Mode)
t
RASP
ns
RAS Hold Time
t
RSH
ns
CAS Precharge Time
t
CP
ns
CAS Pulse Width
t
CAS
ns
RAS Low to CAS High Delay Time
t
CSH
ns
CAS High to RAS Low Delay Time
t
CRP
ns
RAS to CAS Delay Time
t
RCD
ns
RAS to Column Address Delay Time
t
RAD
ns
Row Address Set-up Time
t
ASR
ns
Row Address Hold Time
t
RAH
ns
Column Address Set-up Time
t
ASC
ns
Column Address Hold Time
t
CAH
ns
Column Address Hold Time from RAS
t
AR
ns
Column Address to RAS Lead Time
t
RAL
ns
4, 5, 6
4, 5
4, 6
4
7, 8
3
5
6
-70BS2/DS2
MSC2313258A
-60BS2/DS2
4
RAS Hold Time from CAS Precharge
t
RHCP
ns
Min.
130
30
--
--
--
--
0
0
3
--
50
70
70
20
10
10
45
5
20
15
0
10
0
15
50
35
40
Max.
--
--
70
20
35
40
--
15
50
16
--
10k
100k
--
--
10k
--
--
50
35
--
--
--
--
--
--
--
Min.
110
25
--
--
--
--
0
0
3
--
40
60
60
15
10
10
40
5
20
15
0
10
0
10
45
30
35
Max.
--
--
60
15
30
35
--
15
50
16
--
10k
100k
--
--
10k
--
--
45
30
--
--
--
--
--
--
--
Output Hold Time from CAS Low
t
DOH
ns
5
--
5
--
RAS to Data Output Buffer Turn-off Delay Time
t
REZ
ns
7, 8
0
15
0
15
WE to Data Output Buffer Turn-off Delay Time
t
WEZ
ns
7
0
15
0
15
RAS to Second CAS Delay Time
t
RSCD
ns
70
--
60
--
1
Semiconductor
MSC2313258A-xxBS2/DS2
59
AC Characteristics (2/2)
Parameter
Symbol
Unit
Read Command Hold Time
Note
(V
CC
= 5 V 10%, Ta = 0C to 70C) Note 1,2,3
t
RRH
ns
MSC2313258A
Read Command Hold Time referenced to RAS
t
WCS
ns
Write Command Set-up Time
t
WCH
ns
Write Command Hold Time
t
WCR
ns
Write Command Hold Time from RAS
t
WP
ns
Write Command Pulse Width
t
RWL
ns
Write Command to RAS Lead Time
t
CWL
ns
Write Command to CAS Lead Time
t
DS
ns
Data-in Set-up Time
t
DH
ns
Data-in Hold Time
t
DHR
ns
Data-in Hold Time from RAS
t
RPC
ns
CAS Active Delay Time from RAS Precharge
t
CSR
ns
RAS to CAS Set-up Time (CAS before RAS)
t
CHR
ns
RAS to CAS Hold Time (CAS before RAS)
ns
-70BS2/DS2
Read Command Set-up Time
t
RCH
ns
Min.
0
0
0
15
50
15
20
20
0
15
50
5
5
15
0
Max.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
t
RCS
9
9
MSC2313258A
-60BS2/DS2
Min.
0
0
0
10
45
10
15
15
0
15
45
5
5
10
0
Max.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
t
WPE
Write Command Pulse Width (Output Disable)
ns
10
--
5
--
MSC2313258A-xxBS2/DS2
Semiconductor
60
See ADDENDUM H for AC Timing Waveforms
Notes:
1. A start-up delay of 200
s is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.) and t
WEZ
(Max.) define the time at which the output achieves
the open circuit condition and are not referenced to output voltage levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
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