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Электронный компонент: MSC23140D-70BS10

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Semiconductor
MSC23140D-xxBS10/DS10
1,048,576-word x 40-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
This version: Feb. 23. 1999
DESCRIPTION
The MSC23140D-xxBS10/DS10 is a fully decoded, 1,048,576-word x 40-bit CMOS dynamic random access
memory module composed of ten 4Mb DRAMs in SOJ packages mounted with ten decoupling capacitors on a 72-
pin glass epoxy single-inline package. This module supports any application where high density and large capacity
of storage memory are required.
FEATURES
1,048,576-word x 40-bit organization
72-pin socket insertable module
MSC23140D-xxBS10 : Gold tab
MSC23140D-xxDS10 : Solder tab
Single +5V supply 10% tolerance
Input
: TTL compatible
Output
: TTL compatible, 3-state
Refresh
: 1024cycles/16ms
/CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
Fast page mode capability
Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Family
t
RAC
t
AA
t
CAC
t
OEA
Cycle
Time
(Min.)
Operating(Max.)
Standby(Max.)
MSC23140D-60BS10/DS10
60ns
30ns
15ns
15ns
110ns
4950mW
MSC23140D-70BS10/DS10
70ns
35ns
20ns
20ns
130ns
4400mW
55mW
Semiconductor
MSC23140D
MODULE OUTLINE
1
72
R1.57
6.35
1.04Typ.
1.270.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
3.18
25.40.2
101.19Typ.
107.950.2
*1
3.38Typ.
3.5Min.
5.28Max.
+0.1
-0.08
1.27
(Unit : mm)
MSC23140D-xxBS10/DS10
*1
The common size difference of the board width 12.5mm of its height is specified as 0.2.
The value above 12.5mm is specified as 0.5.
Semiconductor
MSC23140D
PIN CONFIGURATION
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
V
SS
19
/OE
37
DQ19
55
DQ28
2
DQ0
20
DQ8
38
DQ20
56
DQ29
3
DQ1
21
DQ9
39
V
SS
57
DQ30
4
DQ2
22
DQ10
40
/CAS0
58
DQ31
5
DQ3
23
DQ11
41
NC
59
V
CC
6
DQ4
24
DQ12
42
NC
60
DQ32
7
DQ5
25
DQ13
43
NC
61
DQ33
8
DQ6
26
DQ14
44
/RAS0
62
DQ34
9
DQ7
27
DQ15
45
NC
63
DQ35
10
V
CC
28
A7
46
DQ21
64
DQ36
11
NC
29
DQ16
47
/WE
65
DQ37
12
A0
30
V
CC
48
V
SS
66
DQ38
13
A1
31
A8
49
DQ22
67
PD1
14
A2
32
A9
50
DQ23
68
PD2
15
A3
33
NC
51
DQ24
69
PD3
16
A4
34
NC
52
DQ25
70
PD4
17
A5
35
DQ17
53
DQ26
71
DQ39
18
A6
36
DQ18
54
DQ27
72
V
SS
Presence Detect Pins
Pin No.
Pin Name
MSC23140D
-60BS10/DS10
MSC23140D
-70BS10/DS10
67
PD1
V
SS
V
SS
68
PD2
V
SS
V
SS
69
PD3
NC
V
SS
70
PD4
NC
NC
Semiconductor
MSC23140D
BLOCK DIAGRAM
/WE
/CAS0
/RAS0
A0-A9
DQ0
A0-A9
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ1
DQ2
DQ3
DQ8
A0-A9
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ9
V
CC
V
SS
C1-C10
A0-A9
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ4
DQ5
DQ6
DQ7
A0-A9
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ12
DQ13
DQ14
DQ15
A0-A9
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ16
DQ17
DQ18
DQ19
DQ20
A0-A9
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ21
DQ22
DQ23
V
CC
V
SS
V
CC
V
SS
DQ24
A0-A9
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ25
DQ26
DQ27
V
CC
V
SS
DQ28
A0-A9
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ29
DQ32
A0-A9
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ33
DQ34
DQ35
V
CC
V
SS
DQ36
A0-A9
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ37
DQ38
DQ39
V
CC
V
SS
/OE
DQ
DQ
DQ10
DQ11
DQ
DQ30
DQ
DQ31
Semiconductor
MSC23140D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
( Ta = 25C )
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
, V
OUT
-1.0 to +7.0
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-1.0 to +7.0
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
10
W
Operating Temperature
T
OPR
0 to +70
C
Storage Temperature
T
STG
-40 to +125
C
Recommended Operating Conditions
( Ta = 0C to +70C )
Parameter
Symbol
Min.
Typ.
Max.
Unit
V
CC
4.5
5.0
5.5
V
Power Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.4
-
6.5
V
Input Low Voltage
V
IL
-1.0
-
0.8
V
Capacitance
( V
CC
= 5V 10%, Ta = 25C, f = 1 MHz )
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A9)
C
IN1
-
70
pF
Input Capacitance (/RAS0, /CAS0, /WE, /OE)
C
IN2
-
80
pF
I/O Capacitance (DQ0 - DQ39)
C
DQ
-
13
pF
Note:
Capacitance measured with Boonton Meter.
Semiconductor
MSC23140D
DC Characteristics
(V
CC
= 5V 10%, Ta = 0C to +70C )
MSC23140D
-60BS10/DS10
MSC23140D
-70BS10/DS10
Parameter
Symbo
l
Condition
Min.
Max.
Min.
Max.
Unit
Note
Input Leakage Current
I
LI
0V
V
IN
6.5V:
All other pins not
under test = 0V
-100
100
-100
100
A
Output Leakage Current
I
LO
Data out is disable
0V
V
OUT
5.5V
-10
10
-10
10
A
Output High Voltage
V
OH
I
OH
= -5.0mA
2.4
V
CC
2.4
V
CC
V
Output Low Voltage
V
OL
I
OL
= 4.2mA
0
0.4
0
0.4
V
Average Power Supply Current
(Operating)
I
CC1
/RAS cycling,
/CAS cycling,
t
RC
= min.
-
900
-
800
mA
1, 2
TTL
-
20
-
20
mA
1
Power Supply Current
(Standby)
I
CC2
/RAS = V
IH
/CAS = V
IH
MOS
-
10
-
10
mA
1
Average Power Supply Current
(/RAS only refresh)
I
CC3
/RAS cycling,
/CAS = V
IH
,
t
RC
= min.
-
900
-
800
mA
1, 2
Average Power Supply Current
(/CAS before /RAS refresh)
I
CC6
t
RC
= min.
-
900
-
800
mA
1, 2
Average Power Supply Current
(Fast Page Mode)
I
CC7
/RAS = V
IL
,
/CAS cycling,
t
PC
= min.
-
700
-
600
mA
1, 3
Notes: 1. I
CC
is dependent on output loading and cycles rates. Specified values are obtained with the output open.
2. Address can be changed once or less while /RAS = V
IL
.
3. Address can be changed once or less while /CAS = V
IH
.
Semiconductor
MSC23140D
AC Characteristics (1/2)
(V
CC
= 5V 10%, Ta = 0C to +70C ) Note: 1, 2, 3, 11, 12
MSC23140D
-60BS10/DS10
MSC23140D
-70BS10/DS10
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Note
Random Read or Write Cycle Time
t
RC
110
-
130
-
ns
Read Modify Write Cycle Time
t
RW C
150
-
180
-
ns
Fast Page Mode Cycle Time
t
PC
40
-
45
-
ns
Fast Page Mode Read Modify Write Cycle Time
t
PRW C
80
-
95
-
ns
Access Time from /RAS
t
RAC
-
60
-
70
ns
4, 5, 6
Access Time from /CAS
t
CAC
-
15
-
20
ns
4, 5
Access Time from Column Address
t
AA
-
30
-
35
ns
4, 6
Access Time from /CAS Precharge
t
CPA
-
35
-
40
ns
4
Access Time from /OE
t
OEA
-
15
-
20
ns
4
Output Low Impedance Time from /CAS
t
CLZ
0
-
0
-
ns
4
/CAS to Data Output Buffer Turn-off Delay Time
t
OFF
0
15
0
20
ns
7
/OE to Data Output Buffer Turn-off Delay Time
t
OEZ
0
15
0
20
ns
7
Transition Time
t
T
3
50
3
50
ns
3
Refresh Period
t
REF
-
16
-
16
ms
/RAS Precharge Time
t
RP
40
-
50
-
ns
/RAS Pulse Width
t
RAS
60
10K
70
10K
ns
/RAS Pulse Width (Fast Page Mode)
t
RASP
60
100K
70
100K
ns
/RAS Hold Time
t
RSH
15
-
20
-
ns
/RAS Hold Time referenced to /OE
t
ROH
15
-
20
-
ns
/CAS Precharge Time (Fast Page Mode)
t
CP
10
-
10
-
ns
/CAS Pulse Width
t
CAS
15
10K
20
10K
ns
/CAS Hold Time
t
CSH
60
-
70
-
ns
/CAS to /RAS Precharge Time
t
CRP
5
-
5
-
ns
/RAS Hold Time from /CAS Precharge
t
RHCP
35
-
40
-
ns
/RAS to /CAS Delay Time
t
RCD
20
45
20
50
ns
5
/RAS to Column Address Delay Time
t
RAD
15
30
15
35
ns
6
Row Address Set-up Time
t
ASR
0
-
0
-
ns
Row Address Hold Time
t
RAH
10
-
10
-
ns
Column Address Set-up Time
t
ASC
0
-
0
-
ns
Column Address Hold Time
t
CAH
15
-
15
-
ns
Column Address Hold Time from /RAS
t
AR
50
-
55
-
ns
Column Address to /RAS Lead Time
t
RAL
30
-
35
-
ns
Semiconductor
MSC23140D
AC Characteristics (2/2)
(V
CC
= 5V 10%, Ta = 0C to +70C ) Note: 1, 2, 3, 11, 12
MSC23140D
-60BS10/DS10
MSC23140D
-70BS10/DS10
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Note
Read Command Set-up Time
t
RCS
0
-
0
-
ns
Read Command Hold Time
t
RCH
0
-
0
-
ns
8
Read Command Hold Time referenced to /RAS
t
RRH
0
-
0
-
ns
8
Write Command Set-up Time
t
W CS
0
-
0
-
ns
9
Write Command Hold Time
t
W CH
10
-
10
-
ns
Write Command Hold Time from /RAS
t
W CR
45
-
50
-
ns
Write Command Pulse Width
t
W P
10
-
10
-
ns
/OE Command Hold Time
t
OEH
15
-
20
-
ns
Write Command to /RAS Lead Time
t
RW L
15
-
20
-
ns
Write Command to /CAS Lead time
t
CW L
15
-
20
-
ns
Data-in Set-up Time
t
DS
0
-
0
-
ns
10
Data-in Hold Time
t
DH
15
-
15
-
ns
10
Data-in Hold Time from /RAS
t
DHR
50
-
55
-
ns
/OE to Data-in Delay Time
t
OED
15
-
20
-
ns
/CAS to /WE Delay Time
t
CW D
35
-
45
-
ns
9
Column Address to /WE Delay Time
t
AW D
50
-
60
-
ns
9
/RAS to /WE Delay Time
t
RW D
80
-
95
-
ns
9
/CAS Precharge /WE Delay Time
t
CPW D
55
-
65
-
ns
9
/CAS Active Delay Time from /RAS Precharge
t
RPC
10
-
10
-
ns
/RAS to /CAS Set-up Time
(/CAS before /RAS)
t
CSR
5
-
5
-
ns
/RAS to /CAS Hold Time
(/CAS before /RAS)
t
CHR
10
-
10
-
ns
/WE to /RAS Precharge Time
(/CAS before /RAS)
t
W RP
10
-
10
-
ns
/WE Hold Time from /RAS
(/CAS before /RAS)
t
W RH
10
-
10
-
ns
/RAS to /WE Set-up Time
(Test Mode)
t
W TS
10
-
10
-
ns
/RAS to /WE Hold Time
(Test Mode)
t
W TH
10
-
10
-
ns
Semiconductor
MSC23140D
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assumes t
T
= 5ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition time (t
T
) are
measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, then
the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, then
the access time is controlled by t
AA
.
7. t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieves the open circuit condition and are
not referenced to output voltage levels.
8. t
RCH
or t
RRH
must be satisfied for a read cycle.
9. t
W CS
, t
CW D
, t
RW D
and t
CPW D
are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If t
W CS
t
W CS
(Min.), the cycle is an early write cycle and the data out will
remain open circuit (high impedance) throughout the entire cycle. If t
CW D
t
CW D
(Min.), t
RW D
t
RW D
(Min.),
t
AW D
t
AW D
(Min.) and t
CPW D
t
CPW D
(Min.), the cycle is a read modify write cycle and data out will contain
data read from the selected cell; if neither or the above sets of conditions is satisfied, the conditions of
the data out (at access time) is indeterminate.
10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge
in an /OE control write cycle or a read modify write cycle.
11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin
will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by a /RAS only
refresh or /CAS before /RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.