FEDD5117400F-01
1Semiconductor
This version: June. 2000
Previous version :
MSM5117400F
4,194,304-Word
4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
1/15
DESCRIPTION
The MSM5117400F is a 4,194,304-word
4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM5117400F achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal
CMOS process. The MSM5117400F is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP.
FEATURES
4,194,304-word
4-bit configuration
Single 5V power supply,
10% tolerance
Input
: TTL compatible, low input capacitance
Output : TTL compatible, 3-state
Refresh : 2048 cycles/32ms
Fast page mode, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Packages
26/24-pin 300mil plastic SOJ
(
SOJ26/24-P-300-1.27
)
(Product : MSM5117400F-xxSJ)
26/24-pin 300mil plastic TSOP
(
TSOPII26/24-P-300-0.80-K
)
(Product : MSM5117400F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Family
t
RAC
t
AA
t
CAC
t
OEA
Cycle Time
(Min.)
Operating
(Max.)
Standby
(Max.)
50ns
25ns
13ns
13ns
90ns
550mW
60ns
30ns
15ns
15ns
110ns
495mW
MSM5117400F
70ns
35ns
20ns
20ns
130ns
440mW
5.5mW
FEDD5117400F-01
1Semiconductor
MSM5117400F
2/15
PIN CONFIGURATION (TOP VIEW)
Pin Name
Function
A0A10
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1DQ4
Data Input/Data Output
OE
Output Enable
WE
Write Enable
V
CC
Power Supply (5V)
V
SS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every V
CC
pin, and the same GND voltage level must
be provided to every V
SS
pin.
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
DQ1
DQ2
V
CC
V
CC
V
SS
V
SS
A9
A8
A7
A6
A0
A1
A2
A3
WE
RAS
NC
A10
A5
A4
OE
DQ4
DQ3
CAS
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
DQ1
DQ2
V
CC
V
CC
V
SS
V
SS
DQ4
DQ3
A9
A8
A7
A6
A0
A1
A2
A3
WE
RAS
NC
A10
A5
A4
CAS
OE
26/24-Pin Plastic
SOJ
26/24-Pin Plastic TSOP
(K Type)
FEDD5117400F-01
1Semiconductor
MSM5117400F
3/15
BLOCK DIAGRAM
4
4
4
4
4
4
11
11
11
11
Timing
Generator
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Refresh
Control Clock
Column Decoders
Sense Amplifiers
Memory
Cells
Word
Drivers
Row
Deco-
ders
I/O
Selector
Input
Buffers
Output
Buffers
DQ1
-
DQ
4
OE
WE
RAS
CAS
V
CC
V
SS
On Chip
V
BB
Generator
Timing
Generator
4
Write
Clock
Generator
A0
-
A10
FEDD5117400F-01
1Semiconductor
MSM5117400F
4/15
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage V
CC
Supply relative to V
SS
V
T
0.5 to V
CC
+0.5
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D*
1
W
Operating Temperature
T
opr
0 to 70
C
Storage Temperature
T
stg
55 to 150
C
*: Ta = 25
C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
V
CC
4.5
5.0
5.5
V
Power Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.4
V
CC
+ 0.5
*1
V
Input Low Voltage
V
IL
-
0.5
*2
0.8
V
Notes: *1. The input voltage is V
CC
+ 1.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which V
CC
is applied).
*2. The input voltage is V
SS
-
1.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which V
SS
is applied).
PIN CAPACITANCE
(Vcc = 5V
10%, Ta = 25C, f = 1 MHz)
Parameter
Symbol
Min.
Typ.
Min.
Unit
Input Capacitance (A0 A10)
C
IN1
--
--
5
pF
Input Capacitance
(
RAS
,
CAS
,
WE
,
OE
)
C
IN2
--
--
7
pF
Output Capacitance (DQ1 DQ4)
C
I/O
--
--
7
pF
FEDD5117400F-01
1Semiconductor
MSM5117400F
5/15
DC CHARACTERISTICS
(V
CC
= 5V
10%, Ta = 0 to 70C)
MSM5117400
F-50
MSM5117400
F-60
MSM5117400
F-70
Parameter
Symbol
Condition
Min.
Max.
Min.
Max.
Min.
Max.
Unit Note
Output High Voltage V
OH
I
OH
=
-
5.0mA
2.4
V
CC
2.4
V
CC
2.4
V
CC
V
Output Low Voltage
V
OL
I
OL
= 4.2mA
0
0.4
0
0.4
0
0.4
V
Input Leakage
Current
I
LI
0V
V
I
6.5V;
All other pins not
under test = 0V
-
10
10
-
10
10
-
10
10
A
Output Leakage
Current
I
LO
DQ disable
0V
V
O
V
CC
-
10
10
-
10
10
-
10
10
A
Average Power
Supply Current
(Operating)
I
CC1
RAS
,
CAS
cycling,
t
RC
= Min.
100
90
80
mA
1,2
RAS
,
CAS
= V
IH
2
2
2
Power Supply
Current
(Standby)
I
CC2
RAS
,
CAS
V
CC
-
0.2V
1
1
1
mA
1
Average Power
Supply Current
(
RAS
-only Refresh)
I
CC3
RAS
cycling,
CAS
= V
IH
,
t
RC
= Min.
100
90
80
mA
1,2
Power Supply
Current
(Standby)
I
CC5
RAS
= V
IH
,
CAS
= V
IL
,
DQ = enable
5
5
5
mA
1
Average Power
Supply Current
(
CAS
before
RAS
Refresh)
I
CC6
RAS
= cycling,
CAS
before
RAS
100
90
80
mA
1,2
Average Power
Supply Current
(Fast Page Mode)
I
CC7
RAS
= V
IL
,
CAS
cycling,
t
PC
= Min.
80
70
60
mA
1,3
Notes: 1. I
CC
Max. is specified as I
CC
for output open condition.
2. The address can be changed once or less while
RAS = V
IL
.
3. The address can be changed once or less while
CAS = V
IH
.
FEDD5117400F-01
1Semiconductor
MSM5117400F
6/15
AC CHARACTERISTICS (1/2)
(V
CC
= 5V
10%, Ta = 0 to 70C) Note1,2,3,11,12
MSM5117400
F-50
MSM5117400
F-60
MSM5117400
F-70
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit Note
Random Read or Write Cycle Time
t
RC
90
110
130
ns
Read Modify Write Cycle Time
t
RWC
131
155
185
ns
Fast Page Mode Cycle Time
t
PC
35
40
45
ns
Fast Page Mode Read Modify Write
Cycle Time
t
PRWC
76
85
100
ns
Access Time from
RAS
t
RAC
50
60
70
ns 4, 5, 6
Access Time from
CAS
t
CAC
13
15
20
ns
4, 5
Access Time from Column Address
t
AA
25
30
35
ns
4, 6
Access Time from
CAS
Precharge
t
CPA
30
35
40
ns
4
Access Time from
OE
t
OEA
13
15
20
ns
4
Output Low Impedance Time from
CAS
t
CLZ
0
0
0
ns
4
CAS
to Data Output Buffer Turn-
off Delay Time
t
OFF
0
13
0
15
0
20
ns
7
OE
to Data Output Buffer Turn-off
Delay Time
t
OEZ
0
13
0
15
0
20
ns
7
Transition Time
t
T
3
50
3
50
3
50
ns
3
Refresh Period
t
REF
32
32
32
ms
RAS
Precharge Time
t
RP
30
40
50
ns
RAS
Pulse Width
t
RAS
50
10,000
60
10,000
70
10,000
ns
RAS
Pulse Width (Fast Page Mode) t
RASP
50
100,000
60
100,000
70
100,000 ns
RAS
Hold Time
t
RSH
13
15
20
ns
RAS
Hold Time referenced to
OE
t
ROH
13
15
20
ns
CAS
Precharge Time
(Fast Page Mode)
t
CP
7
10
10
ns
CAS
Pulse Width
t
CAS
13
10,000
15
10,000
20
10,000
ns
CAS
Hold Time
t
CSH
50
60
70
ns
CAS
to
RAS
Precharge Time
t
CRP
5
5
5
ns
RAS
Hold Time from
CAS
Precharge t
RHCP
30
35
40
ns
RAS
to
CAS
Delay Time
t
RCD
17
37
20
45
20
50
ns
5
RAS
to Column Address Delay Time t
RAD
12
25
15
30
15
35
ns
6
Row Address Set-up Time
t
ASR
0
0
0
ns
FEDD5117400F-01
1Semiconductor
MSM5117400F
7/15
AC CHARACTERISTICS (2/2)
(V
CC
= 5V
10%, Ta = 0 to 70C) Note1,2,3,11,12
MSM5117400
F-50
MSM5117400
F-60
MSM5117400
F-70
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit Note
Row Address Hold Time
t
RAH
7
10
10
ns
Column Address Set-up Time
t
ASC
0
0
0
ns
Column Address Hold Time
t
CAH
7
10
15
ns
Column Address to
RAS
Lead Time
t
RAL
25
30
35
ns
Read Command Set-up Time
t
RCS
0
0
0
ns
Read Command Hold Time
t
RCH
0
0
0
ns
8
Read Command Hold Time
referenced to
RAS
t
RRH
0
0
0
ns
8
Write Command Set-up Time
t
WCS
0
0
0
ns
9
Write Command Hold Time
t
WCH
7
10
15
ns
Write Command Pulse Width
t
WP
7
10
10
ns
OE
Command Hold Time
t
OEH
13
15
20
ns
Write Command to
RAS
Lead Time
t
RWL
13
15
20
ns
Write Command to
CAS
Lead Time
t
CWL
13
15
20
ns
Data-in Set-up Time
t
DS
0
0
0
ns
10
Data-in Hold Time
t
DH
7
10
15
ns
10
OE
to Data-in Delay Time
t
OED
13
15
20
ns
CAS
to
WE
Delay Time
t
CWD
36
40
50
ns
9
Column Address to
WE
Delay Time
t
AWD
48
55
65
ns
9
RAS
to
WE
Delay Time
t
RWD
73
85
100
ns
9
CAS
Precharge
WE
Delay Time
t
CPWD
53
60
70
ns
9
CAS
Active Delay Time from
RAS
Precharge
t
RPC
5
5
5
ns
RAS
to
CAS
Set-up Time
(
CAS
before
RAS
)
t
CSR
10
5
5
ns
RAS
to
CAS
Hold Time
(
CAS
before
RAS
)
t
CHR
10
10
10
ns
WE
to
RAS
Precharge Time
(
CAS
before
RAS
)
t
WRP
10
10
10
ns
WE
Hold Time from
RAS
(
CAS
before
RAS
)
t
WRH
10
10
10
ns
RAS
to
WE
Set-up Time (Test Mode) t
WTS
10
10
10
ns
RAS
to
WE
Hold Time (Test Mode)
t
WTH
10
10
10
ns
FEDD5117400F-01
1Semiconductor
MSM5117400F
8/15
Notes: 1. A start-up delay of 200
s is required after power-up, followed by a minimum of eight initialization
cycles (
RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume t
T
= 5ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition times (t
T
)
are measured between V
IH
and V
IL
.
4. -50 is measured with a load circuit equivalent to 2TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 2TTL load and 100pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit,
then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit,
then the access time is controlled by t
AA
.
7. t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieved the open circuit condition and
are not referenced to output voltage levels.
8. t
RCH
or t
RRH
must be satisfied for a read cycle.
9. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If t
WCS
t
WCS
(Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If t
CWD
t
CWD
(Min.), t
RWD
t
RWD
(Min.), t
AWD
t
AWD
(Min.) and t
CPWD
t
CPWD
(Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
10. These parameters are referenced to the
CAS, leading edges in an early write cycle, and to the WE
leading edge in an
OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a
WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test CA0, CA1 and CA10 are not
used and each DQ pin now access 8-bit locations. Since all 4 DQ pins are used, a total 32 data bits can
be written in parallel into the memory array. In a read cycle, if 8 data bits are equal, the DQ pin will
indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode
is cleared and the memory device returned to its normal operating state by performing a
RAS-only
refresh cycle or a
CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
FEDD5117400F-01
1Semiconductor
MSM5117400F
9/15
TIMING CHART
Read Cycle
Write Cycle (Early Write)
t
OFF
t
CLZ
t
CAC
t
OEA
t
ASC
t
RRH
t
RAH
t
ASR
t
RAD
t
RAL
t
CRP
t
CAH
t
CRP
t
RCD
t
RC
t
RAS
t
RP
t
CSH
t
RSH
t
CAS
t
RAC
t
AA
t
RCS
t
ROH
t
RCH
t
OEZ
Row
Column
Valid Data-out
Open
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
"H" or "L"
t
CRP
t
RP
t
RWL
Valid Data-in
t
DH
t
DS
t
WCS
t
WCH
t
CWL
t
ASR
t
RAH
t
ASC
t
RC
t
RAS
Row
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
Column
t
CAH
t
RAD
t
RAL
t
WP
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
IH
V
IL
"H" or "L"
Open
FEDD5117400F-01
1Semiconductor
MSM5117400F
10/15
Read Modify Write Cycle
t
RSH
t
CAS
t
RWC
t
CWL
t
RWL
t
CRP
t
RP
t
OED
t
CWD
t
AWD
t
OEH
t
WP
t
OEZ
t
CAC
t
DH
t
DS
Valid
Data-out
Valid
Data-in
t
AA
t
RWD
Row
Colum
t
RAC
t
OEA
t
RCS
t
CAH
t
ASC
t
ASR
t
RAH
t
RAD
t
CRP
t
RCD
t
CSH
t
RAS
t
CLZ
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
I/OH
V
I/OL
"H" or "L"
FEDD5117400F-01
1Semiconductor
MSM5117400F
11/15
Fast Page Mode Write Cycle
Fast Page Mode Write Cycle (Early Write)
t
CLZ
t
OEA
t
RCS
t
OEZ
t
CAC
t
RRH
t
RCH
t
RCS
t
CPA
t
RCH
t
AA
t
OEA
t
OFF
t
OEZ
t
CLZ
t
OFF
t
CAH
t
CAS
t
RAL
t
ASC
t
RSH
t
CP
t
CAH
t
RP
t
RHCP
Column
t
CRP
t
PC
t
OFF
t
CAC
t
CSH
t
CAC
t
OEZ
t
RAC
t
OEA
t
RCH
t
CPA
t
AA
t
AA
t
CAH
t
ASC
t
RAH
t
RAD
t
RCS
t
ASR
t
ASC
t
CP
t
CAS
t
RASP
t
CAS
t
RCD
t
CRP
t
CLZ
Valid
Data-out
Row
Column
Column
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
"H" or "L"
Valid
Data-out
Valid
Data-out
t
WP
t
CWL
t
WCH
t
ASC
t
CP
t
PC
t
RASP
Column
t
RAL
t
CRP
t
ASC
t
CAH
t
CAH
t
CAS
t
RSH
t
CP
t
CAS
t
RP
t
RHPC
Column
t
WP
t
WCH
t
DH
t
DS
t
DH
t
DS
Valid *
Data-in
t
WCS
t
WCS
Valid *
Data-in
t
CWL
t
CSH
t
RAD
t
ASR
t
ASC
t
RAH
t
RCD
t
CRP
t
CAS
t
CAH
Row
Column
t
WP
t
RWL
t
WCH
t
CWL
t
DH
t
DS
t
WCS
Valid *
Data-in
"H" or "L"
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
DQ
V
IH
V
IL
Note:
OE
= "H" or "L"
FEDD5117400F-01
1Semiconductor
MSM5117400F
12/15
Fast Page Mode Read Modify Write Cycle
RAS-only Refresh Cycle
t
DS
t
AA
t
DH
t
ROH
t
OEA
t
WP
t
CPA
t
DS
t
OEZ
t
CPWD
t
WP
t
CWD
t
AWD
t
DH
t
AWD
t
AA
t
RAC
t
RCS
t
RCS
t
AA
t
CPA
t
OEA
t
PWD
t
CWD
t
ASC
t
RAH
t
ASR
t
RAD
t
CSH
t
CAS
t
RASP
t
CWL
t
RCD
t
CP
t
CAH
t
ASC
Row
Column
t
RWL
t
CWL
t
RCS
Column
t
CWL
t
CWD
t
RAL
t
CAH
t
CRP
t
CP
t
CAS
t
CLZ
t
CAS
t
ASC
t
OED
t
OEZ
t
OED
t
CAC
t
OED
t
DH
t
OEZ
In
t
WP
t
DS
Column
t
RP
t
RSH
t
CAH
Out
t
CAC
t
PRWC
t
CAC
t
CLZ
t
CLZ
t
AWD
t
OEA
In
In
Out
Out
t
CPWD
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
I/OH
V
I/OL
"H" or "L"
Note: In = Valid Data-in, Out = Valid Data-out
t
ASR
t
RAH
t
CRP
t
RPC
t
RP
t
RAS
t
RC
t
OFF
Row
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
Address
V
OH
V
OL
DQ
"H" or "L"
Open
Note:
WE
,
OE
= "H" or "L"
FEDD5117400F-01
1Semiconductor
MSM5117400F
13/15
CAS before RAS Refresh Cycle
Hidden Refresh Read Cycle
t
WRH
t
WRP
t
WRP
t
CEZ
t
RPC
t
RP
t
RC
t
RAS
t
CHR
t
CSR
t
RP
t
CP
t
RPC
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
OH
V
OL
DQ
Open
Note:
OE
, Address = "H" or "L"
WE
V
IH
V
IL
"H" or "L"
t
REZ
t
RAC
t
CLZ
t
OEZ
t
ROH
t
OEA
t
CAC
t
RRH
t
AA
t
RAL
t
RCS
t
CAH
t
RAH
t
ASR
t
ASC
Column
t
RAD
t
RP
t
RAS
t
RC
t
RP
t
CHR
t
RAS
t
RSH
t
RCD
t
CRP
t
RC
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
OH
V
OL
Open
Row
Valid Data-out
"H" or "L"
t
CEZ
FEDD5117400F-01
1Semiconductor
MSM5117400F
14/15
Hidden Refresh Write Cycle
Test Mode-in Cycle
t
DH
t
DS
t
WCH
t
WCS
t
RWL
t
RAL
t
RAD
t
CAH
t
RAH
t
ASR
t
ASC
t
RCD
t
CRP
t
RSH
t
RP
t
CHR
t
RP
t
RAS
t
RC
t
RC
t
RAS
t
WP
RAS
V
IH
V
IL
CAS
V
IH
V
IL
Address
V
IH
V
IL
WE
V
IH
V
IL
OE
V
IH
V
IL
DQ
V
IH
V
IL
Row
Column
Valid Data-in
"H" or "L"
t
OFF
t
WTS
t
WTH
t
CP
t
RPC
t
CSR
t
RP
t
CHR
t
RAS
t
RC
RAS
V
IH
V
IL
CAS
V
IH
V
IL
WE
V
IH
V
IL
DQ
V
IH
V
IL
"H" or "L"
Open
Note:
OE
, Address = "H" or "L"
FEDD5117400F-01
1Semiconductor
MSM5117400F
15/15
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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