¡ Semiconductor

MSM6262-xx

1/52

GENERAL DESCRIPTION

The MSM6262-xx is a dot matrix LCD controller which is fabricated by OKI's low power
consumption CMOS silicon gate technology. In combination with 8-bit microcontroller, the
MSM6262-xx can control the dot matrix character type LCD module.

The MSM6262-xx is provided with a serial data transfer output. So, a maximum of 160 characters
can be controlled by combining this device with the MSM5259, MSM5839C, or MSM5260.
The MSM6262-xx is recommended for use in an LCD panel which is capable of displaying 81 to
160 characters. If an LCD panel of which display capacity is 80 characters or less is used, the
MSM6222B-xx is recommended.
The MSM6262-xx is best suited to be used as an LCD controller for applications such as electronic
typewriters, POS system terminals, and data banks.

FEATURES

· Dot matrix LCD controller/driver for three different font configuration

(5 x 7 dots, 5 x 11 dots and 5 x 12 dots)

· Up to 160 characters can be controlled

(Display data RAM ... 160 x 9-bit)

· On-chip character generator ROM (CGROM) for 256 different characters

5 x 7 dots ... 128 characters
5 x 11 dots ... 96 characters
5 x 12 dots ... 32 characters

· On-chip character generator RAM (CGRAM) (32 x 8-bit)

5 x 8 dots ... 4 kinds
5 x 12 dots ... 2 kinds

· Easy interface with Z80, 6809, 80C49, and 80C51
· Underline function
· Shift function for g, i, p, q and y
· Selectable driving duty

¡ Semiconductor

MSM6262-xx

DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER

E2B0033-27-Y2

Duty

Font Configuration (dots)

Cursor Display

Display (characters x lines)

1/16

5 x 7

80 x 2

1/24

5 x 11

80 x 2

1/32

5 x 7

40 x 4

1/48

5 x 11

40 x 4

Available

· Package :

80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6262-xxGS-BK)

xx indicates code number.

This version: Nov. 1997

Previous version: Mar. 1996

¡ Semiconductor

MSM6262-xx

5/52

PIN CONFIGURATION (TOP VIEW)

COM 46

COM 47

COM 48

(GND)

OSC1

OSC2

OSC3

TEST1

TEST2

TEST3

RESET

68 series/80 series

E (RD)

R/W (WR)

COM 29

COM 28

COM 27

COM 26

COM 25

COM 24

COM 23

COM 22

COM 21

COM 20

COM 19

COM 18

COM 17

COM 16

COM 15

COM 14

COM 13

COM 12

COM 11

COM 10

COM 9

COM 8

COM 7

COM 6

COM 45

COM 44

COM 43

COM 42

COM 41

COM 40

COM 39

COM 38

COM 37

COM 36

COM 35

COM 34

COM 33

COM 32

COM 31

COM 30

BUSY 1 OUT

BUSY 2 OUT

LOAD

COM 1

COM 2

COM 3

COM 4

COM 5

80-Pin Plastic QFP

¡ Semiconductor

MSM6262-xx

6/52

PIN DESCRIPTIONS

Symbol

Type

OSC1

OSC2, OSC3
RESET
68 series/80 series
CS

R/W (WR)

E (RD)

A0, A1

- DB

TEST1 - TEST3

, V

LOAD

COM1 - COM48

BUSY1 OUT

BUSY2 OUT

I/O

I
I
I

I/O

Clock oscillating pins required for internal operation upon receipt

of the LCD drive signal and CPU instruction.
Reset pin
Selection pin for either 68 series CPU or 80 series CPU
Chip select pin. By setting CS at "L" level, MSM6262-xx

is set at selecting condition.

R/W pin of 68 series CPU shall be connected to this pin,

while WR pin shall be connected to this pin in the case of

80 series CPU.

E pin of 68 series CPU shall be connected to this pin,

while RD pin shall be connected to this pin in the case of

80 series CPU.

The address bus of CPU shall be connected to these pins.

Instruction code is set by these pins.

The data bus of CPU shall be connected to these pins. These

pins are used to set the data of the instruction or to read

the data.

Test pins. Normally these pins should be set at V

open.

Voltage supply pins. V

is also used for the common

bias voltage level to drive the LCD.

Common bias voltage input pins to drive the LCD

Serial data output pin for SEGMENT drivers

Clock pulse output pin. The clock output from this pin

enables the character pattern data, which is output from

DO, to input to the SEGMENT drivers (MSM5839C or MSM5259).

Load signal output pin. The character pattern data to

the SEGMENT drivers, which was output from DO and

CP, is loaded to the LCD output of the SEGMENT

drivers, synchronized with the COMMON signal.

B-type AC signal output pin to drive the LCD

COMMON signal output pins to drive the LCD

This pin shows the internal condition of MSM6262-xx.

"H" shows that MSM6262-xx is in internal operation,

while "L" shows that MSM6262-xx is ready to receive

the instruction from the CPU.

This pin shows that MSM6262-xx is in internal operation

based on the instruction from the CPU, or MSM6262-xx

is in display revising operation based on the instruction

from the CPU.

"H" shows that MSM6262-xx is in internal operation,

while "L" shows that the display on the LCD has been

established and the MSM6262-xx is ready to receive an

instruction.

Description

¡ Semiconductor

MSM6262-xx

7/52

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Applicable Pin

Supply Voltage

Ta = 25°C, V

0.3 to +7.0

DD,

Supply Voltage

for Driving LCD

, V

Ta = 25°C

12 to

+ 0.3

, V

Input Voltage

Ta = 25°C

0.3 to V

+ 0.3

OSC1, RESET

68 series / 80 series

CS, A0, A1, R/W (WR)

E (RD), DB

- DB

Power Dissipation

Ta = 25°C

500

Storage Temperature

STG

55 to +125

°C

RECOMMENDED OPERATING CONDITOINS

Parameter

Symbol

Condition

Range

Unit

Applicable Pin

Supply Voltage

4.5 to 5.5

DD,

GND

LCD Driving Voltage

LCD

1/5 bias, V

3.0 to 11

Operating Temperature

°C

1/6, 1/7 bias, V

4.0 to 11

1/8 bias, V

4.5 to 11

DD,

, V

20 to +75

Note: For bias, refer to *3 in the section "DC Characteristics".

¡ Semiconductor

MSM6262-xx

8/52

ELECTRICAL CHARACTERISTICS

DC Characteristics

*1.

This is applicable to the voltage drop which is caused between V

, V

and COM1

- COM48 when a current of 50 mA is flowed in/out to/from all of COM1 - COM48. (When
the output level is either V

or V

, it should be applied only when the current flows in.

When the output level is either V

or V

, it should be applied only when the current flows

in.
In this case, +5V is applied to V

and V

, while 6 V is applied to V

and V

*2.

This is applicable to the current which flows in to V

under following conditions.

= 5 V, V

= 0 V, V

= 2.8 V, V

= -3.8 V, V

= 6 V, No load, No interface with CPU

*3.

to V

should be set at as follows.

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable Pin

CS, R/W (WR)
E (RD), A0, A1
DB

- DB

OSC1, RESET
68series/80series

DO, LOAD, DF

BUSY1 OUT
BUSY2 OUT

= ± 50 mA

COM1 - COM48

CS, R/W (WR)
E (RD), A0, A1
OSC1, 68series/
80series

Supply Current

DD1

DD2

= 4.5 to 5.5 V , Ta = 20 to +75°C)

LCD Driving
Voltage

, V

RESET

"H" Input Voltage

"L" Input Voltage

"H" Output Voltage

"L" Output Voltage

"H" Input Voltage

"L" Input Voltage

"H" Output Voltage

"L" Output Voltage

"H" Output Voltage

"L" Output Voltage

"H" Output Voltage

"L" Output Voltage

IH1

IL1

OH1

OL1

IH2

IL2

OH2

OL2

OH3

OL3

OH4

COM Voltage Drop

"H" Input Current

"L" Input Current

"H" Input Current

OL4

COM

ILH1

ILL1

LCD

ILH2

ILL2

= 250 mA

= 1.8 mA

= 500 mA

= 1 mA

= 100 mA

= 1.6 mA

= V

1/5 bias

1/6-1/7
bias

1/8 bias

= V

= 5 V

2.2

0.3

2.4

0.3

0.8

0.85 V

2.4

3.0

4.0

4.5

0.7

0.4

0.8

0.15 V

0.4

2.9

1.5

"L" Input Current

= 5 V,

OSC

= 500 kHz

(RC oscillation)

= 5 V,

= 500 kHz

(external oscillation)

¡ Semiconductor

MSM6262-xx

9/52

2 lines

4 lines

5 x 8

5 x 12

5 x 8

5 x 12

No. of lines

(N)

Font

configuration

LCD

1
5

4
5

LCD

1
6

5
6

LCD

1
7

6
7

LCD

1
8

7
8

LCD

= LCD driving voltage

AC Characteristics

Open

OSC3

OSC2

OSC1

Oscillation source

OSC3

OSC2

OSC1

= 39 kW ± 5%

= 22 pF ± 10%

(Keep the wiring from
OSC1, OSC2, and
OSC3 to R

and C

as short as possible.)

0.8 V

0.5 V

0.8 V

0.5 V

0.8 V

DUTY

= x 100%

+ T

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable Pin

= 4.5 to 5.5V , Ta = 20 to +75°C)

= V

= 5 V

OSC1, OSC2, OSC3

- DB

= V

300

Input Frequency

Input Clock Duty

Input Clock Rise Time

Input Clock Fall Time

RC Oscillation

Frequency

"H" Input Current

"L" Input Current

DUTY

ILH3

ILL3

*1, *2

300

OSC1

500

120

700

100

700

250

kHz

¡ Semiconductor

MSM6262-xx

19/52

FUNCTIONAL DESCRIPTION

1. Instruction Register (IR) and Data Register (DR)

The MSM6262-xx has two registers, instruction register (IR) and data register (DR).
IR is used to store the address code or instruction code of display data RAM (DD RAM) or
character generator RAM (CG RAM).
This register can be written by the CPU, but cannot be read out by the CPU.
DR is used to store the data to write into (or read out) the data to/from DD RAM or CG RAM.
The data written into DR by the CPU is automatically written into the DD RAM or CG RAM.
When an address code is written into IR, the data of the specified address is automatically
transferred to the DR from either DD RAM or CG RAM. By having the CPU subsequently read
the DR, it is possible to verify DD RAM or CG RAM data.
After the writing of DR by the CPU, the DD RAM or CG RAM of the next address is selected
to be ready for the next CPU writing.
Likewise, after the reading operation of the CPU, DD RAM or CG RAM data of the next
address is transferred to the DR, when CPU is ready for the next reading operation.

2. Busy Flag (BF)

When the output of BUSY 1 OUT is "H", MSM6262-xx is engaged in internal operation.
When the output of BUSY 2 OUT is "H", it indicates that MSM6262-xx is engaged in internal
operation or MSM6262-xx is engaged in the revising of the display starting line on the LCD.
(Refer to the instruction table.)
When the output of BUSY 1 OUT is "H", any input of new instruction is ignored. So, before
setting a new instruction, it is necessary to check whether BUSY 1 OUT and BUSY 2 OUT are
at "L".

3. Address Counter (ADC)

The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read
and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to IR,
after deciding whether it is DD RAM or CG RAM, the address counter code is transferred from
IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the
ADC increments (or decrements) by 1 automatically as its internal operation.

¡ Semiconductor

MSM6262-xx

20/52

4. Timing Generator Circuit

This circuit generates the timing signal for the internal operation by CPU's instruction as well
as to operate the internal circuit of DD RAM, CG RAM, CG ROM and so forth. It also generates
the transfer signal to the SEGMENT driver (MSM5839C or MSM5259).
The internal operation accessed by the CPU and internal operation for LCD display is
independent.
So, a manipulation such as writing data from CPU to DD RAM will not have an influence such
as display flickering upon any part other than the display part to which the data is written.

5. Display Data RAM (DD RAM)

DD RAM is used to store the 8-bit character code (refer to Table 1) and 1-bit under-line data.
The address of DD RAM corresponds to the display position on the LCD. The correspondence
is described below.

DD RAM address (set to ADC) is described as hexadecimal.

(1) Relation between DD RAM and display position in 2-line display mode

1st line

2nd line

Digit

Display position

DD RAM address
(hexadecimal)

1st line

2nd line

10 11

12 13

14 15 16

Digit

MSM5839C (2)
MSM5259 (2) }

MSM5839C (1)
MSM5259 (1)

{ or

Note: The address of the last digit of the first line and the first digit of the second line
does not have any continuity.

MSB

LSB

Hexadecimal

Example: When DD RAM address is 3A

ADC

(2) When 2 pieces of MSM5389C(or MSM5259) are connected to MSM6262-xx, 32

characters can be displayed from the first digit to yhe 16th degit.

¡ Semiconductor

MSM6262-xx

21/52

When the display is shifted by an instruction, the relation between the DD RAM address and
the display position becomes as follows.

(4) Relation between the DD RAM and display position in 4-line display mode

1st line

2nd line

Digit

MSM5839C (2)
MSM5259 (2) }

MSM5839C (1)
MSM5259 (1)

{ or

1st line

2nd line

(Shift to the left)

(Shift to the right)

1st line

2nd line

Digit

MSM5839C (2)

MSM5259 (2)

MSM5839C (1)

MSM5259 (1)

{ or

11 12

13 14

15 16

17 18

73 74

75 76 77 78

79 80

MSM5839C (3)-(9)

MSM5259 (3)-(9)

MSM5839C (10)

MSM5259 (10) }

1st line

2nd line

Digit

Display position

DD RAM address
(hexadecimal)

Note: The address of the last digit of the previous line and the first digit of the
next line does not have any continuity.

3rd line

4th line

(3) The maximum DD RAM capacity of MSM6262-xx is for 160 characters. So, up to 10 pieces

of MSM5839C (or MSM5259) can be connected in the case of 2-line display mode.

¡ Semiconductor

MSM6262-xx

22/52

When the display is shifted by an instruction, the relation between the DD RAM address and
the display position becomes as follows.

11 12 13 14 15 16 17

33 34 35 36

37 38 39

01 02 03 04

05 06

07 08 09

0A 0B 0C 0D 0E 0F

21 22 23

24 25

41 42 43 44

45 46

47 48 49

4A 4B 4C 4D 4E 4F

81 82 83 84

85 86

87 88 89

8A 8B 8C 8D 8E 8F

C1 C2 C3 C4

C5 C6

C7 C8 C9 CA CB CC CD CE CF

1st line

Digit

2nd line

3rd line

4th line

MSM5839C (1)

MSM5259 (1)

MSM5839C (2)

MSM5259 (2)

MSM5839C (3),(4)

MSM5259 (3),(4)

MSM5839C (5)

MSM5259 (5)

1st line

2nd line

Digit

MSM5839C (2)
MSM5259 (2) }

MSM5839C (1)
MSM5259 (1)

{ or

3rd line

4th line

(6) The maximum DD RAM capacity of MSM6262-xx is for 160 characters. So, up to 5pieces

of MSM5839C (or MSM5259) can be connected in the case of 4-line display mode.

(5) When 2 pieces of MSM5839C (or MSM5259) are connected to MSM6262-xx, 64 characters

can be displayed from the first digit to the 16th digit.

1st line

2nd line

Digit

MSM5839C (2)
MSM5259 (2) }

MSM5839C (1)
MSM5259 (1)

3rd line

4th line

(shift to right direction)

1st line

2nd line

3rd line

4th line

(shift to left direction)

{ or

¡ Semiconductor

MSM6262-xx

23/52

6. Cursor/Blink Control Circuit

This is the circuit to control the generation of cursor and its blinking. This circuit is controlled
by the program of the CPU.
The position of the cursor and its blink appears on the position according to the ADC contents,
which correspond to the address of DD RAM. For example, when the ADC is set as "07" (hex.),
the position of cursor and its blinking becomes as follows.

7. Underline Control Circuit

First, either underline display mode or underline blinking mode has to be set by the CPU.
When an instruction to enable the underline function is input from the CPU, the cursor
display shifts to the right direction (increment) or left direction (decrement). Display of
underline appears (or disappears) on the same position where cursor was displayed.
An input of "H" data enables the underline display, while an input of "L" data deletes the
underline.

8. Character Generator ROM (CG ROM)

CG ROM stores the character pattern. MSM6262-xx has 128 kinds of 5 x 7-dot patterns, 96
kinds of 5 x 11-dot patterns and 32 kinds of 5 x 12-dot patterns. The character pattern
corresponds to the character code which is written into the DD RAM.
The relation between 8-bit character code and character pattern is described in Table 1.
When the 8-bit character code of CG ROM is written into the DD RAM, the character pattern
of the corresponding character code of the CG ROM is displayed on the LCD position
corresponding to the DD RAM address.
When all of the upper 4 bits of CG ROM code are "L", CG ROM can be switched to CG RAM.

DB7

DB0

ADC

Digit

Cursor and its blinking position

2-line display

Digit

Cursor and its blinking position

4-line display

Note: Cursor display and blinking can be performed even when the CG RAM address is
set in the ADC. So, it is necessary to disable the cursor display and blinking when
the CG RAM address is set in the ADC.

¡ Semiconductor

MSM6262-xx

25/52

9. Character Generator RAM (CG RAM)

The CG RAM is used to display user's original character pattern other than CG ROM.
The CG RAM has capacity (32 bytes = 256 bits) to write 4 kinds of 5 x 8 dots and 2 kinds of 5
x 12 dots.
In displaying the character pattern stored in the CG RAM, CG RAM has to be enabled by an
instruction. When CG RAM is enabled, CG ROM code for 16 characters cannot be read out
since the CGROM code with all "L" on the upper 4 bits is used as CG RAM code.
The following describes how to write character patterns into the CG RAM and how to display
them on the LCD.

(1) When the character pattern is 5 x 8 dots (See Table 2-1)

· A method to write character pattern into the CG RAM by the CPU

The lower 3 bits (0 - 2) of the CG RAM address correspond to the line position of the

character pattern. The upper 2 bits (3, 4) of the CG RAM address correspond to the lower
2 bits (0, 1) of the character code.

First, set increment of decrement by the CPU, and then input CG RAM address. After this,

write character pattern data into CG RAM through DB0 to DB7 line by line.

DB0 - DB7 correspond to CG RAM data 0 - 7 in Table 2-1.
Display is turned on when "H" is set as input data and turned off when "L" is set as input

data.

Since the ADC is automatically incremented or decremented by 1 after the writing of data

to the CG RAM, it is not necessary to set the CG RAM address again.

To enable cursor display, set all input data on the line where the lower 3 bits of the CG RAM

(0-2) are all "H" to "L".

0 - 4 bits of CG RAM data are output to the LCD as the display data; however, 5 - 7 bits of

CG RAM data are not. But it can be used as the data RAM because the data can be written/
read through DB0 to DB7.

· A method to display the CG RAM character pattern to the LCD

First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is
selected only when all of the upper 4 bits of the character code is "L".
So, the character pattern of CG RAM is displayed on the LCD position that corresponds to
the DD RAM address, when the character code shown in Table 2-1 is written into DD RAM.
Since the bits 2 and 3 of the character code are regarded as invalid, "K" is displayed when
the character codes "01", "05", "'09", and "0D" are selected.

(2) When the character pattern is 5 x 12 dots (See Table 2-2)

· A method to write character pattern into the CG RAM by the CPU

The lower 4 bits of CG RAM address (0 - 3) correspond to the line position of the character
pattern.
The upper 1 bit of CG RAM address bit 4 corresponds to the bit 1 of the character code.
First, set increment or decrement by the CPU, and then input CG RAM address.
After this, write the character pattern data into CG RAM through DB

to DB

line by line.

- DB

correspond to CG RAM data 0 - 7 in Table 2-2.

Display is turned on when "H" is set as the input data and turned off when "L" is set

¡ Semiconductor

MSM6262-xx

26/52

as the input data.

Since the ADC is automatically incremented or decremented by 1 after the writing of data
to the CG RAM, it is not necessary to set the CG RAM address again.
To enable cursor display, set all input data on the line where the CG RAM address is "0B"
or "1B" (hex.) to "L".
The addresses "0" to "B" (hexadecimal) in the bits 0 to 4 of the CG RAM data are output on
the LCD as the display data. However, the addresses "C" to "F" (hexadecimal) in the bits
0 to 4, and 5 to 7 of the CG RAM data are not output on the LCD. But these CG RAM data
can be used as the data RAM so that they can be written into or read out through DB0 to
DB7.

· A method to display the CG RAM character pattern on the LCD

First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is
selected only when all of the upper 4 bits of the character code is "L".
So, the character pattern of CG RAM is displayed on the LCD position corresponding to
the DD RAM address, when the character code shown in Table 2-2 is written into the DD
RAM.
Since bits 0, 2 and 3 of the character code are regarded as invalid, the character of "m" is
displayed when the character codes "00", "01", "04", "05", "08", "09", "0C" and "0D" are
selected.

(3) A method to read out the CG RAM data

First, set the CG RAM address by inputting a CG RAM address set instruction from the

CPU.

Then, execute the CG RAM/DD RAM data read instruction. The set data of CG RAM

address is output from the DB0 to DB7. The 8-bit data, read out from the MSM6262-xx,
corresponds to the data which is written into the CG RAM. Since the CG RAM address is
automatically incremented or decremented by 1, the CG RAM read out instruction c a n
be successfully input. It is necessary, however, to set the DD RAM at data transferring
condition by executing the DD RAM address set instruction after all of CG RAM data are
read out.

¡ Semiconductor

MSM6262-xx

27/52

CG RAM DATA

(Character Pattern )

DD RAM DATA

CG RAM

ADDRESS

(Character Code )

7 6 5 4 3 2 1 0

L L L L L

7 6 5 4 3 2 1 0

LSB MSB

LSB

L
L
L
H
H
H
H

X X X L H H H L

H
H

L L L L X X L L

H
H
L
L

4 3 2 1 0

L H L L L

L
L
L
H
H
H
H

X X X H L L L H

L L L L X X L H

H H L L L

L
L
L
H
H
H
H

X X X L H H H L

L L L L X X H H

X: Don't care

L H
H L
H H
L L
L H
H L
H H

L
H
H
L
L
H
H

H
L
H
L
H
L
H

L L

H H

L L

H
H

H
H
H
L

L H

L L

H L

L L

L H

L L

L
L

L
L
L
L

L L

H H

L L

Table 2-1 Relation between CG RAM data (character pattern) vs. CGRAM

address and DDRAM data vs. character pattern when the character
pattern is 5

¥ 8 dots.

¡ Semiconductor

MSM6262-xx

28/52

Table 2-2 Relation between CGRAM data (character pattern) vs. CGRAM address

and DDRAM data vs. character pattern when the character pattern
is 5

¥ 12 dots.

7 6 5 4 3 2 1 0

LSB MSB

LSB

L
L
L
H
H
H
H

X X X

L
L

4 3 2 1 0

L
L
L
L

H
H
H

L
L
L
H
H
H
H

X X X

L L L L X X H

X: Don't care

L H
H L
H H
L L
L H
H L
H H
L L
L H
H L
H H

L L
L H
H L

L
H
H
L
L
H
H

H
L
H
L
H
L
H

L L

H L

H H

L H

H H

H L

H
L

H H

L H

L L

L
L

L
H
H
L

L L

H H

H H H

L
L
L

L
L
H

L
H
L

L
L
H

L L

H L

L L

L H H

L L L

H
H
H
H

L
L
H
H

L
H
L
H

X X X

L
L
L
L
L
L
L
H
H
H
H

H
H
H
H

L
L
L
L
L
L
L
H
H
H
H

H
H
H
H

L L L

L L L L X X L X

CG RAM DATA

(Character Pattern)

DD RAM DATA

CG RAM

ADDRESS

(Character Code)

X X X

¡ Semiconductor

MSM6262-xx

29/52

9. LCD Display Circuit (COM1 to COM48, DO, CP, LOAD, DF)

The MSM6262-xx is provided with COMMON signal output. So, maximum 160 characters
can be displayed when it is used together with SEGMENT drivers (MSM5259 or MSM5839C).
Interface between MSM6262-xx and SEGMENT drivers can be done by using DO, CP, LOAD
and DF.
The SEGMENT data is serially output from DO pin, synchronized with the pulse which is
output from the CP pin.
This data, input to the SEGMENT driver, is converted from serial data to parallel data by the
latch pulse which is output from the LOAD pin of MSM6262-xx and this converted data is
used as the display data. This parallel/serial conversion is performed synchronized with the
COMMON signal of MSM6262-xx and LCD display AC signal which is output from DF pin.
So, this signal can drive dot matrix LCD panel.

10. Reset Circuit

Power-on-reset is required for MSM6262-xx when it is powered-on. So, a capacitor has to be
connected between RESET pin and V

pin.

It is also advisable to connect a diode between RESET pin and V

pin when it is required to

connect a capacitor of more than 3.3

F to RESET pin.

When the power-on reset circuit normally operates, the busy flags 1 and 2 become at "H" level
for about 10 ms after the power-on. During this period, a initialization of MSM6262-xx is
performed by following procedures.

1 Display is cleared
2 CG ROM becomes enabled
3 No display shift
4 ADC is incremented
5 2-line display mode
6 5 x 8 dots font configuration
7 No display shift for "g", "j", "p", "q" and "y"
8 Display off
9 No display of cursor, blinking and underline

11. Data Bus with CPU

MSM6262-xx can be interfaced with 8-bit CPU, such as 6809, Z80, 80C49 and 80C51. When
MSM6262-xx is connected with 6809, the 68 series/80 series pin has to be connected to V

When MSM6262-xx is connected with Z80, 80C49 or 80C51, the 68 series/80 series pin has to
be connected to V

. The level at 68 series/80 series cannot be switched during MSM6262-xx's

operation. It must be connected with either V

or V

before MSM6262-xx is turned on.

Note: It is possible, indeed, to change the 68 series/ 80 series pin's level when a reset signal

is being input to RESET pin. However, the 68 series /80 series pin does not have
characteristics to have an interface with MCU, nor does it have an antichattering
circuit.
Further, if a reset signal is input, the MSM6262-xx is initialized as described above.
So, in this case, changing the 68 series/80 series pin level is not recommended.

¡ Semiconductor

MSM6262-xx

32/52

Instruction Table

80series CPU

68series CPU

Note

R/W

Explanation

Execution Time (MAX),

When fosc = 500kHz

Display Clear

Return

Under Line

Entry Mode Set

Display/Cursor Shift

CG RAM address Set

Function Set

Display Control

CG RAM/DD RAM
Data Write
DD RAM Address
Set

Read the Underlined
Data

Read the CG RAM/
DD RAM Data
Read the Address
Counter Content
Read Busy Flag

ULD

B1F

B2F

CG/

I/D

A/O

S/C

I/D

UD/

UR/

CR/C

A/O

( )

3.22 ms

1.62 ms

20 ms

0 ms

When
fosc =
600 kHz,
execution time
becomes

20 ms¥

= 16.7 ms

500
600

* : DON'T CARE

Note 1: In the case of 80 series CPU, access to MSM6262-xx is done by WR and RD. So, a bit for part of the read/write code is not required.

Clears all of the display. and sets

address 0 of DD RAM in the address

counter.
CR/C = L: Cursor home
CR/C = H: Carriage Return
UL = H: Writes the underline in the

cursor part before executing

this instruction.

UL = L : Erases the underline in the

cursor part before executing

this instruction.

Sets whether the display of the direction of
cursor (I/D) move should be shifted or not.
When the data is being written or read,
this operation is performed.
This instruction also sets whether the
character code of DD RAM is used as
CG ROM or CG RAM.(A/O)

Shifts the cursor and display without
changing the DD RAM contents.
(S/C, UD/RL,UR/DL)
The line to be displayed in the uppermost
position can be set.

Sets the CG RAM address.
The dara, which will be sent/received
after the CG RAM address is set, is
CG RAM data.

WRITE DATA

READ DATA

Sets the following:
No. of display digits (N), Character font
(F

), Cursor line font (F

), Font shift

of "g, j, p, q, y" (F

)

Sets the following:

All display on/off (D), Cursor display

on/off (C), Character on the cursor

position blink on/off (B), Underline display

on/off (UC), Character, on the

underline, blink on/off (UB)
Writes a data in either DD RAM or
CG RAM.
Sets DD RAM address.
The data which is sent/received after
that is DD RAM data.
Reads following data:
Data on the underline, DD RAM or
CG from RAM data.
Reads the data either from DD RAM
or from CG RAM.
Reads the address counter contents.

Busy 1 flag (B1F) shows that
MSM6262-xx's internal operation is going on.
Busy 2 flag (B2F) shows that the revising
of display starting line is going on.
CG/DD shows whether the data, being
transmitted or received, is of CG RAM
or DD RAM.
I/D shows the direction in which cursor moves.
S shows the display shift.
A/O shows that the DD RAM character
code is CG RAM character code or
CG RAM character code.
D shows the all display on/off.
UD shows underline display on/off.

CR/C = H
UL = H
I/D = H
S = H
A/O = L
S/C = H
UD/RL = H
D

UR/DL = H
N = L
N = H
F

= H

= L

= H

ULD = H
B1F = H
B2F = H

CG/DD = H

:
:
:
:
:
:
:
:

:
:
:
:
:
:

:
:
:

Carriage Return
Write underline
Increment
Accompany display shift
CG ROM ENABLE
Display move
Up/Down move
The bit to set the line to be displayed in the uppermost position.
D

is LSB. D

is MSB.

Upper-right move
2 lines
4 lines
5 x 11 dots
5 x 12 dots or 5 x 8 dots
Shift "g, j, p, q, y" to the
lower position by 1 dot.
Underline data exists
Internal operation going on
Revising the display starting
line or internal operation going on
Transmit /Receive CG RAM data

CR/C = L
UL = L
I/D = L

A/O = H
S/C = L
UD/RL = L

UR/DL = L

= L

= H

= L

ULD = L
B1F = L
B2F = L

CG/DD = L

:
:
:

:
:
:
:

:
:
:

Cursor home
Underline erase
Decrement

CG RAM ENABLE
Cursor move
Left/Right move

Down-left move

5 x 7 dots
5 x 11 dots or 5 x 7 dots
Disable character shift

No underline data
Ready to receive instruction
No revision on display
starting line
Transmit/Receive of DD RAM data

DD RAM
CG RAM

:
:

:
:
:

Display data RAM
Character generator
RAM
CG RAM address
DD RAM address
Address counter which
is used for both DD
RAM and CG RAM

( )

¡ Semiconductor

MSM6262-xx

33/52

When this instruction is executed, cursor and blinking position moves to the left end of the
LCD. (In the case of 2-line or 4-line display mode, it moves to the left end of the first line.)
When display is being shifted, the display returns to its original position for both
horizontally and vertically.
ADC becomes "00" (hex.).

· CR/C = H (Carriage return)

When this instruction is executed, cursor and blinking position moves to the left end of the
line on which the cursor and brink were positioned before execution of instruction.
If the display is being shifted when this instruction was executed, the cursor and blinking
position moves to the original position before it was shifted only concerning to the shift to
the right and left.
All bits other than line specifying bit of ADC will be reset to "0" (hex.).

Instruction
code

CR/C

12. Instruction Code

The instruction code is defined as the signal through which the MSM6262-xx is accessed by
the CPU. MSM6262-xx starts its operation upon receipt of the instruction code.
The internal processing operation starts with a timing that does not affect the LCD display,
so, the busy condition is longer than that of cycle time.
In the busy condition, MSM6262-xx does not execute any instruction other than the reading
of busy flag. Therefore, make certain that busy flag is set at "L" before inputting the instruc-
tion code.

(1) Display clear

When this instruction is executed, the LCD display is cleared.

When cursor display and/or character blink is being performed, their display position
moves to the left end of the LCD. (In the case of 2-line or 4-line display mode, it moves to
the left end of the first line.)
All of the DD RAM data becomes "20" (hex), while ADC data becomes "00" (hex.). If the
display is on a shifted position, it returns to the original position.

Data for underline is re-written as "L" and display turns off.

(2) Return
· CR/C = L (Cursor home)

¡ Semiconductor

MSM6262-xx

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· I/D (Increment/Decrement)

When this instruction is executed, DD RAM address will be incremented (I/D = "H") or
decremented (I/D = "L") by 1, after the character code or underline code is written into (or
read out from) the DD RAM.
In the case of increment, cursor moves to the right, while the cursor moves to the left in the
case of decrement.
Processing for writing/reading the data into/from CG RAM is performed the same way.

· S (Display shift upon writing)

When S = "H" and data is written into DD RAM, display is shifted either to the right or
left. When I/D = "H", the whole display shifts to the left, while it shifts to the right when
I/D = "L". So, display of cursor looks being stopped and display itself looks being shifted.
In the case of reading the data from DD RAM, display is not shifted. Also in the case of
reading/writing the data from/to CG RAM, display shall not be shifted.
When S = "L", display is not be shifted.

· A/O (CG RAM ENABLE/CG ROM ENABLE)

When A/O is "L", CG ROM will be enabled, and all CG ROM contets on Table 2 becomes
selectable and CG RAM cannot be selected.
CG RAM cannot be used as character code for display. But it can be used as data RAM.
When A/O = "H", CG RAM is enabled.
When the upper 4 bits of the character code in Table 1 are "00" (hex.), the bit pattern of CG
RAM is displayed on the LCD. (CG RAM has a RAM area for 4 kinds of 5 x 8 dots and 2
kinds of 5 x 12 dots)
CG ROM is selected when the upper 4 bits of the character code in Table 1 are "01" - "0F"
(hex.).

Instruction
code

*: Don't care

Instruction
code

I/D

A/O

(3) Underline

· UL = H (Write underline)

When this instruction is executed, the underline appears on the cursor position. Cursor
will move to the right or left if either increment or decrement is specified.

· UL = L (Erase underline)

When this instruction is executed, the underline on the cursor position disappears. Cursor
will move to the right or left if either increment or decrement is specified.
When this instruction is executed, ADC will be automatically incremented by +1 or
decremented by 1. Display is shifted accordingly.

(4) Entry mode set

¡ Semiconductor

MSM6262-xx

35/52

· S/C (Display move/Cursor move)

This is the bit to select either display or cursor to move. S/C = "H" enables the display
movement, while S/C = "L" enables the cursor movement.

· UD/RL (Upward or downward move/Right or left move)

UD/RL = "H" enables upward or downward move. UD/RL = "L" enables right or left
move.

· D

, D

(Starting line of display)

Upward or downward movement is enabled by setting the starting line of display. D

LSB and D

is MSB. Both D

and D

are expressed in 2-bit binary data.

Only D

is valid in 2-line mode. Both D

and D

are valid in 4-line mode.

Instruction
code

S/C

UD/

( )

(UR/

DL)

*: Don't care

DD RAM

Display of the LCD

1st line

2nd line

1st line

2nd line

1st line

2nd line

1st line

2nd line

, D

= "L"

, D

= "H"

[ 2-line mode ]

* : Don't care

(5) Display/Cursor move

¡ Semiconductor

MSM6262-xx

37/52

(6) CG RAM address set

S/C

UD/

Explanation

Move the cursor to the left by 1 digit

Move the cursor to the right by 1 digit

Move the cursor downward by 1 digit

Move the cursor upward by 1 digit

Move the display to the left by 1 digit

Move the display to the right by 1 digit

Set the first line as the display starting line

Set the 2nd line as the display starting line

Set the 3rd line as the display starting line s

Set the 4th line as the display starting line s

: Invalid in 2-line mode

Instruction
code

(UR/
DR)

* : Don't care

· UR/DL (Up-right move/Down-left move)

UR/DL = "H" enables up-right movement.
UR/DL = "L" enables down-left movement.

Combination of bit for Display/Cursor movement is as follwes

Set the CG RAM address which consists of 5 bits of Ac

- Ac

. The data which will be

transferred after this instruction is set will be limited to the CG RAM data (character font
data).

¡ Semiconductor

MSM6262-xx

38/52

· F

(5 x 11 dots/5 x 7 dots)

When F

= "H", 5 x 12-dot font is selected.

When F

= "L", 5 x 8-dot font is selected.

· F

(Font assignment of cursor line)

When F

= "L" and if character code, which has a display dot on the cursor position, is

selected, it is displayed on the cursor line of LCD.
When F

= "H" and if character code, which has a display dot on the cursor position, is

selected, cursor is displayed but the bit on the cursor position is not displayed.
However, this function does not apply to CG RAM and the bit on the cursor position is also
displayed.

· F

(Character shift of "g, j, p, q, y")

When F

= "H", each character of "g, j, p, q, y" is displayed shifted downward by 1 dot for

the whole character.
When F

= "L", display of these characters is the same as other characters, as shown in Table

1. This bit is valid only for 5 x 12-dot font.

Example

Instruction
code

*: Don't care

LCD lines

2-line mode

4-line mode

(7) Function set

· N (Selection of LCD lines to be displayed)

5 x 7-dot font ROM

5 x 11- or 5 x 12-dot font ROM

3 dots

7 dots

1 or 2 dots

Not displayed

Cursor

Cursor position

q F

= "L" (5 x 8-dot/font)

¡ Semiconductor

MSM6262-xx

40/52

Instruction
code

*: Don't care

· D (All display on/off)

When D = "H", display on the LCD is enabled.
When D = "L", display is disabled.
When display was disabled by setting D at "L", character code in the DD RAM does not
change. So, when D becomes "H" again, display is enabled immediately.

· C (Cursor display on/off)

C = "H", cursor display appears.
When C = "L", cursor display disappears.

· B (Cursor blinking)

When B = "H", blinking of character on the position corresponding to the cursor position,
starts. Blinking of all-dot's-on and character (and cursor)-on is performed alternately for
every 409.6 ms in case of fosc = 500 kHz and 5 x 8 dots font configuration (every 614.4 ms
in case of 5 x 12 dots font configuration)
When B = "L", blinking stops.
Cursor and blinking can be set together.

· UC (Underline display)

When UC = "H", underline is displayed on the cursor position.
When UC = "L", underline display is disabled.

· UB (Underlined character blinking)

When UB = "H", blinking of character on the position corresponding to the underline
position, starts. Blinking of character stops when UB = "L".
Cursor, blink, underline, and blinking of character on the underline can be set together.

(9) CG RAM and DD RAM data write

(8) Display control

Instruction
code

Write the 8-bit data (D

- D

) into either CG RAM or DD RAM. Determination of either

CG RAM or DD RAM is made by the previously set CC RAM or DD RAM address set.
After the data is written into the RAM, it is incremented or decremented by 1 according
to the entry mode of the address. Display shift is also determined by the entry mode.

¡ Semiconductor

MSM6262-xx

41/52

This instruction reads underline data, and CG RAM or DD RAM data.
Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD
RAM address set.
The first data read by this instruction is an invalied data. Normal data is read out from
the second instruction onward if the read instruction is executed continuously. This
instruction address will be incremented or decremented by 1 according to the entry
mode. Display shift is, however, not performed. Underline data is output to DB7 as either
"H" (when display is on) or "L" (when display is off).
The MSB of RAM data is not read. RAM data consists of 7 bits (DB0 to DB6).

Instruction
code

ULD

Instruction
code

(10) DD RAM address set

This instruction code sets the DD RAM address, which consists of 8 bits (A

to A

). The

data which is received after this instruction is set is limited to the DD RAM data (character
code data).
Do not input any address code other than those below.

2-line mode : 1st line

00 - 4F

2nd line

80 - CF

4-line mode : 1st line

00 - 27

2nd line

40 - 67

3rd line

80 - A7

4th line

C0 - E7

(11) Underline data read

¡ Semiconductor

MSM6262-xx

42/52

B1F (Busy 1 flag)
When B1F = "H", MSM6262-xx is engaged in internal operation and next instruction is not
accepted until when B1F becomes "L". So, subsequent instruction has to be input after B1F
is confirmed at "L". During B1F = "H", DB

to DB

are undefined.

B2F (Busy 2 flag)
B2F indicates that MSM6262-xx is engaged in its internal operation and it also indicates
that the display starting line is under being revised.
Instruction contents of B1F and B2F are the same except when setting the starting line of
display.
B2F = "H" indicates that MSM6262-xx is engaged in its internal operation. B2F = "L"
indicates that MAM6262-xx is ready for accepting new instruction.
Even when B2F = "H", new instruction can be accepted if B1F = "L". However, if the
starting line of display is revised under this condition, the previous set data about
starting line of display becomes invalid and the newly input data about starting line
becomes valid.

Instruction
code

B1F

CG/

B2F

I/D

A/O

(12) CG RAM and DD RAM data read

This instruction reads the 8-bit data (D

to D

) from either CG RAM or DD RAM.

Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD
RAM address set.
The CG RAM address set instruction or DD RAM address set instruction has to be input
just before executing this read instruction. If it is not input, the first output of the data
becomes invalid. When this read instruction is performed continuously, normal data is
output from the 2nd data onward.
In the case of DD RAM data read, normal data is output from the first data even if the
address set is not input, provided that cursor is moved by the cursor shift instruction.
After reading the data, the address is incremented or decremented by 1 by the entry
mode.
The shift of the display, however, is not performed.

(13) Address counter read

This instruction reads the 8-bit data (A

to A

) . Address counter is determined by the

previously set address set because it is used for both CG RAM and DD RAM.

(14) Busy flag read

¡ Semiconductor

MSM6262-xx

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· CG/DD (CG RAM/DD RAM)

This bit indicates whether the address counter contents are CG RAM or DD RAM when
B1F = "L". It indicates that CG RAM data has been selected when CG/DD = "H" and that
DD RAM data has been selected when CG/DD = "L".

· I/D (Increment/Decrement)

This bit indicates which has been set in the entry mode set, increment or decrement, when
B1F = "L". It indicates that increment has been set when I/D = "H" and that decrement has
been set when I/D = "L".

· S (Shift)

This bit reads the shift condition in the entry mode when B1F = "L". It indicates that shift
is set when S = "H" and shift is disabled when S = "L".

· A/O (CG RAM ENABLE/CG ROM ENABLE)

This bit indicates which has been selected in the entry mode, CG ROM or CG RAM, when
BIF = "L".
It indicates the CG ROM selected state when A/O = "L" and CG RAM selected state when
A/O = "H".

· D (Display)

This bit indicates which has been set by display control instruction, LCD display ON or
OFF, when B1F = "L". It indicates that the display is on when D = "H" and the display is
off when D = "L".

· UD (Underline)

This is the bit to indicate the condition of underline or blinking on the underline, both of
which were set by display control instruction, when B1F = "L".
When UD = "H", either (or both of) underline display or blinking on the underline is being
executed. When UD = "L", it indicates neither of underline display nor blinking on the
underline is performed.

¡ Semiconductor

MSM6262-xx

50/52

LCD duty and bias

No. of lines

2 lines

4 lines

Duty

Bias

1/16

1/24

1/32

1/48

1/5

1/6

1/7

1/8

Above are examples of relation between LCD duty and bias. Use these values for reference,
for they vary depending on the characteristics of LCD panel.
The value of resistor on bias circuit is determined by the operational margin and power
consumption. To make the power consumption lower, the value of resistor has to be larger,
but it makes the LCD driving output impedance high and causes the distortion on the LCD
driving waveform.
If a large LCD panel is used, the value of the resistor should be much lower because the
LCD capacitance increases.
Connecting a bypass capacitor to the bias resistor in parallel can improve the distortion of
LCD driving waveform. However, connecting a capacitor of too large value may cause a
level shift of the bias voltage.
So, it has to be determined carefully after checking experimentally.
Followings are the reference values.

R = 2 to 10 kW
V

= 10 to 50 kW

r = 0.2 to 2 kW
C = 0.0022 to 0.047 mF

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