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¡ Semiconductor

MSM6665-xx

¡ Semiconductor

MSM6665-xx

DOT MATRIX LCD CONTROLLER WITH 17-DOT COMMON DRIVER AND 80-DOT SEGMENT
DRIVER

GENERAL DESCRIPTION

The MSM6665-xx is a dot-matrix LCD control driver which has functions of displaying charac-
ters, cursor and arbitrators.
The MSM6665-xx is provided with a 17-dot common driver, 80-dot segment driver, display RAM
and character ROM, and is controlled with the commands from the serial interface.
The character ROM can change the font data by mask option.
The MSM6665-01 has standard ROM with 256 different character fonts.
The MSM6665-xx can drive a variety of LCD panels because of the bias voltage, which determines
the LCD driving voltage, can be optionally supplied from the external source.

FEATURES

· Logic supply voltage

: 2.5 to 5.5 V

· LCD driving voltage

: 3.0 to 6.0 V

· Serial interface
· Contains a 17-dot common driver and an 80-dot segment driver
· Contains ROM with character fonts of (5 x 7 dot) x 256
· Built-in RC oscillator circuit
· Provided with 80-dot arbitrators
· Switchable between 1/9 duty (1 line; characters + cursor + arbitrator) and 1/17 duty (2 lines;

characters + cursor, 1 line; arbitrator)

· Character blink operation can be switched between all-characters lighting-on mode and all-

characters lighting-off mode

· Arbitrator blink operation can be switched between 5-dot unit mode and 1-dot unit mode
· Package options:

128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: MSM6665-01GS-K)
Al pad chip

(Product name: MSM6665-xx)

xx indicates code number.

E2B0036-27-Y2

This version: Nov. 1997

Previous version: Mar. 1996

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¡ Semiconductor

MSM6665-xx

PIN CONFIGURATION (TOP VIEW)

NC : No connection

128-Pin Plastic QFP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46

S45
S44

S43
S42
S41
S40
S39
S38

S37
S36

S35
S34
S33
S32

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

TEST1
OSC3
OSC2
NC
OSC1
V

RST
9D/17D

SHT
SI
C/D
NC
CS
V

SS1

NC
V

SS2

SS3

SS4

SS5

(GND)

C1
NC
C2
C3
NC
C4
C5
C6
C7

S77

S76

S75

S74

S73

S72

S71

S70

S69

S68

S67

S66

S65

S64

S63

S62

S61

S60

S59

S58

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

31
32
33
34
35
36
37
38

S31
S30
S29
S28
S27
S26
S25
S24

72
71
70
69
68
67
66
65

C8
C9
C10
C11
C12
C13
C14
C15

C16

C17

TEST2

TEST3

S80

S79

S78

103

104

105

106

107

108

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¡ Semiconductor

MSM6665-xx

ABSOLUTE MAXIMUM RATINGS

*1:

The power dissipation depends on the heat sink characteristic of the package.
Set a junction temperature at 150

C or lower.

RECOMMENDED OPERATING CONDITIONS

*2:

RC oscillation, external input clock frequency

List of bias voltages

Symbol

SS1

SS2

SS3

SS4

SS5

1/5 bias

1/5V

2/5V

3/5V

4/5V

SS5

Remarks

Highest voltage

Lowest voltage

1/4 bias

1/4V

2/4V

3/4V

SS5

)

Parameter

Unit

Condition

Supply Voltage

Input Voltage

Power Dissipation

Symbol

Storage Temperature

Rating

Applicable pin

0.3 to +7

0.3 to V

+0.3

630

55 to +150

°C

, V

All inputs

Bias Voltage

Ta=25°C, V

SS5

0.3 to +7

, V

SS5

Ta=85°C

QFP128-1420

STG

Ta=25°C, V

Parameter

Unit

Condition

Supply Voltage

Operating Frequency

Symbol

Operating Temperature

Rating

Applicable pin

2.5 to 5.5

65 to 115

40 to +85

kHz

°C

, V

OSC1

Bias Voltage

SS5

3 to 6

, V

SS5

5/30

¡ Semiconductor

MSM6665-xx

ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

DC Characteristics (2)

Parameter

=2.5 to 3.5V, V

=3 to 6V, Ta=40 to +85°C)

"H" Input Voltage 1

IH1

"L" Input Voltage 1

IL1

"H" Input Voltage 2

IH2

"L" Input Voltage 2

IL2

"H" Input Current 1

IH1

"L" Input Current

"H" Input Current 2

IH2

"H" Output Voltage

"L" Output Voltage

OFF Leakage

OFF

OSC "H" Output Current

OSC "L" Output Current

COM Output Resistance

SEG Output Resistance

Supply Current 1

DD1

Supply Current 2

DD2

External clock input

=0V

Pull-down resistance, V

=1.5mA

=500mA

/0V

0.5V

=0.5V

=±50mA

=±10mA

RC oscillation, f=80kHz
C=56pF, R

=10kW

R=76kW, no load

External clock, f=80kHz

Symbol

Condition

Min. Typ. Max. Unit

Applicable pin

0.8V

OSC1

-- 0.2V

OSC1

0.8V

Input pins except OSC1

-- 0.2V

Input pins except OSC1

Input pins except TEST

Input pins

0.05

0.4

mA TEST1-TEST3

0.5

±1

0.25 mA OSC2, OSC3

0.25

mA OSC2, OSC3

kW C1-C17

kW S1-S80

0.5

100

Parameter

=4.5 to 5.5V, V

=3 to 6V, Ta=40 to +85°C)

"H" Input Voltage 1

IH1

"L" Input Voltage 1

IL1

"H" Input Voltage 2

IH2

"L" Input Voltage 2

IL2

"H" Input Current 1

IH1

"L" Input Current

"H" Input Current 2

IH2

"H" Output Voltage

"L" Output Voltage

OFF Leakage

OFF

OSC "H" Output Current

OSC "L" Output Current

COM Output Resistance

SEG Output Resistance

Supply Current 1

DD1

Supply Current 2

DD2

External clock input

=0V

Pull-down resistance, V

=1.5mA

=500mA

/0V

0.5V

=0.5V

=±50mA

=±10mA

RC oscillation, f=80kHz
C=56pF, R

=10kW

R=76kW, no load

External clock, f=80kHz

Symbol

Condition

Min. Typ. Max. Unit

Applicable pin

0.8V

OSC1

-- 0.2V

OSC1

0.8V

Input pins except OSC1

-- 0.2V

Input pins except OSC1

Input pins except TEST

Input pins

0.3

1.4

mA TEST1-TEST3

0.5

±1

0.5

mA OSC2, OSC3

0.5

mA OSC2, OSC3

kW C1-C17

kW S1-S80

1.1

400

6/30

¡ Semiconductor

MSM6665-xx

AC Characteristics

Parameter

Min.

Unit

Symbol

Condition

Max.

300
200

200
200

200

µs

200
200

=2.5 to 5.5V, Ta=40 to +85°C)

CS Setup Time

CS Hold Time

SO ON Delay Time

SO OFF Delay Time

OFF

SO Output Delay Time

DLY

Input Setup Time

Input Hold Time

Input Waveform Rise Time, Fall Time

Reset Pulse Input Pulse Width

=45pF

All inputs

C S

S I

C /

SHT

S O

RST

"Z"

DLY

OFF

"Z"

IH2

IL2

IH2

IL2

IH2

IL2

IH2

IL2

IH2

=0.8V

IL2

=0.2V

0.5V

=0.5V

Oscillation Circuit

C OSC3

OSC2

OSC1

8/30

¡ Semiconductor

MSM6665-xx

FUNCTIONAL DESCRIPTION

Pin Functional Description

· SI (Serial Input)

Input pin for inputting serially commands and display data in an 8-bit unit.
"H"="1" and "L"="0".
When CS pin is at "H" level, read-in is executed by the leading edge of SHT.
Whether input data is a command or data is determined by selecting a C/D level at the
8th leading edge of SHT.
The input data is a command if C/D="H", and display data if C/D="L".

· C/D (Command/Data)

Input pin for determining whether input data for SI pin is a command or display data.
Read-in is executed by the 8th leading edge of SHT. The input data is a command if C/
D="H", and display data if C/D="L".

· SHT (Shift Clock)

Clock input pin for reading-in SI input and C/D input.
Read-in is executed by the clock leading edge. Read-in operation is complete with 8
clocks. Inputting data during BUSY may cause malfunction.
Valid if CS pin is at "H" level.

· SO (Serial Out)

Serial output pin for reading-out BUSY/NON-BUSY and display data. "H"="1" and
"L"="0". If CS pin is at "H" level and Serial Out Enable is set with the command, output
is executed. Otherwise, this pin becomes high impedance.
BUSY/NON-BUSY is output when CS pin is at "H" level. BUSY if "L" and NON-BUSY
if "H". It goes BUSY after the 8th leading edge of SHT, then goes NON-BUSY
automatically after a specified time.
Display data is output synchronously with the leading edge of SHT.
Input the "SOE/D" instruction to set this output to serial out enable or a high impedance
state because the pin status is undefined after the power is applied.

· CS (Chip Select)

Chip Select input pin.
"Chip Select ON" if CS pin is at "H" level, and "Chip Select OFF" at "L" level. When "L"
level is input, SO pin becomes open and SHT pin becomes equivalent to "H" level inside
of the IC. Moreover, it prevents the input stages of SI, C/D and SHT pins from current
flowing.

* For SI, C/D, SHT, SO, and CS, refer to "I/O Procedure".

· RST

Direct input reset input pin.
By inputting "L" level pulse into RST pin, DISP, ABBC1/5, ABB, and BPC commands are
set as D0="0". Before turning on the power, be sure to set RST pin at "L" level once. Setting
this pin at "L" level during command execution may cause malfunction.

· 9D/17D (1/9Duty/1/17Duty)

Duty setting input pin.
1/9 duty is set if this pin is at "H" level, and 1/17 duty at "L" level. Choice depends on
the type of panel to be used.

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¡ Semiconductor

MSM6665-xx

If 1/9 duty is selected, common outputs C10 to C17 should be set open.

· TEST1, TEST2, TEST3

Test signal input pins.
The manufacturer uses these pins for testing.
The user should connect this pin to GND or leave open.

· OSC1, OSC2, OSC3

Pins used for 80kHz RC oscillation circuit formation and as external master clock input
pin. Leave OSC2 and OSC3 open during input of external master clock.

· V

, V

Supply voltage pins. V

should be set at "H" level.

Arbitrator

Cursor

S80

C17

C16

C10

Cursor

OSC1

OSC2

OSC3

10k W

76±5k W

56pF

OSC1

OSC2

OSC3

80kHz

OPEN

[External master clock input]

[RC oscillation circuit formation]

< Oscillation circuit wiring diagram >

· C1 - C17, S1 - S80 (Common 1 - 17, Segment 1 - 80)

LCD output pins to be connected with the LCD panel. Turning into AC is made by frame
inversion.
Use the C1 to C9 pins during use at 1/9 duty, and leave the C10 to C17 pins open.
Æ

Refer to "Relationship between panel and LCD output".

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¡ Semiconductor

MSM6665-xx

is a GND pin. If the battery is used, V

is connected to the positive pin, and V

the negative pin.

· V

SS1

, V

SS2

, V

SS3

, V

SS4

, V

SS5

LCD bias voltages input pins.

(EXAMPLE)

Case of 1/5 bias

SS5

)

Highest voltage :

SS1

1/5 V

)

SS2

2/5 V

)

SS3

3/5 V

)

SS4

4/5 V

)

Lowest voltage :

SS5

Case of 1/4 bias

SS5

)

Highest voltage :

SS1

1/4 V

)

SS2

, V

SS3

2/4 V

)

SS4

3/4 V

)

Lowest voltage :

SS5

11/30

¡ Semiconductor

MSM6665-xx

List of Commands

Mnemonic

Comments

Serial addresses 0 to 47

No.

LPA

Operation

Load Pointer Address

Arbitrator Blink

LOT

BKCG 1/0

SOE/D

DISP

ABBC 1/5

ABB

AINC

CHB

CSC

CSB

CCB

BPC

Load Option

Bank Change 1/0

Serial Out Enable/Disable

Display on/off

Arbitrator Blink Control
1/5 dot

Address Increment

Character Blink on/off

Cursor Control on/off

Cursor Blink on/off

Character & Cursor
Blink on/off

Blink Pattern Control

Meanings for I1 and I0 are set as in

the table below.

Valid only when 1/9duty is selected.

Switching between display addresses

0 to 15 and 16 to 31.

Switching between output and high
impedance of SO

Sets arbitrator blink in a 1dot unit or
a 5dot unit. 1dot if D0="1", 5 dot if
D0="0"

1/0

Data that is input via SI after setting
D0="1", is set as data for arbitrator
blink (1-dot unit). This is cancelled by
D0="0"

Pointer address is incremented by 1.

Controls blinking of characters and
arbitrators (in 5 dots). Though arbitrator
blink that is set as all-blank displayed is
acceptable, blinking does not occur.

Turns cursor on or off.

Controls blinking of cursor.
But, though blinking setting with
no cursor-on setting is acceptable,
blinking does not occur.

CHB + CSB

Sets blink patterns of characters.
( :chara.) if D0="1", ( :chara.)
if D0="0"

Display ON if D0="1"
Display OFF if D0="0"
When at Display OFF, V

level

voltage is output to all the COM and
SEG pins.

X : Don't care

Notes: 1. Entering commands number 1 to 7 and number 13 does not affect pointer address.

2. By entering commands number 8 to 12 or display code data, pointer address is

automatically incremented by 1.

3. When Reset is entered, commands number 5 to 7 and number 13 are set to D0="0".

Operation is cancelled. (No operation)
Hereafter, equivalent to writing blank code at each AINC execution.
Hereafter, cursor-off and blink-cancellation are executed at each AINC execution.
Both of above two operations are indicated.

Operation

12/30

¡ Semiconductor

MSM6665-xx

Command Description

[D7, D6, D5, D4, D3, D2, D1, D0], X=don't care

· LPA (Load Pointer Address)

[1,1,A5,A4,A3,A2,A1,A0]
The command sets "address" data into the address pointer to specify an address on
which command execution affects and an address where display data is stored. The
"address" is a number between 0H and 2FH, given by A0 through A5 in hexadecimal.
When addresses 30H through 3FH are specified, display data and CHB, CSC, CSB, CCB
commands become invalid through an address pointer is set up. Normally, the address
pointer is a loop of 0H through 2FH.

· LOT (Load Option)

[1,0,1,1,X,X,I1,I0]
This command indicates some specific operation of display at the current address which
is performed each time of AINC command execution.
Operation is specified by bit I1 and I0 of the command.

Operation

Operation is cancelled. (No operation)

Hereafter, equivalent to writing blank code at each AINC execution.

Hereafter, Cursor-off and blink-cancellation are executed at each AINC execution.

Both of above two operations are indicated.

Note) When blink-cancellation is executed, all RAM data, which controls blinks for each bit of the

arbitrator, go zeros.

· BKCG 1/0 (Bank Change 1/0)

[1,0,0,X,0,0,0,1/0]
Command used to do switching between display address groups (switching between
BANKs), which is valid only when 1/9duty display is selected.
When D0 is "0", display address range becomes 0 through 15, and 32 through 47.
When D0 is "1", display address range becomes 16 through 31, and 32 through 47.
Command execution and display data setting are not affected by Bank setting.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.

· SOE/D (Serial Out Enable/Disable)

[1,0,0,X,0,1,1,1/0]
Command used to control the impedance of SO output pin.
When D0 is "1", display data is output via SO pin. When D0 is "0", SO pin goes to high
impedance.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.

13/30

¡ Semiconductor

MSM6665-xx

· DISP (Display on/off)

[1,0,0,X,1,0,0,1/0]
Command used to control lighing-on and lighting-off for the LCD panel.
When D0 is "1", the display of the LCD panel goes on, and When D0 is "0", it goes off.
When the display is off, the V

level voltage is output on all of pins of both the segment

driver and the common driver.
D0 is set to "0" after inputting Reset.

· ABBC 1/5 (Arbitrator Blink Control 1/5 dot)

[1,0,0,1,1,1,0,1/0]
Command used to do switching between arbitrator's blinking in a 1-dot unit and or in
a 5-dot unit.
When D0 is "1", arbitrator's blinking comes in the 1-dot unit mode.
When D0 is "0", it comes in the 5-dot unit mode.
D0="0" is set after inputting Reset.

Note) 1-dot unit blink setting Æ · See ABB.

5-dot unit blink setting Æ · See CHB.

· ABB (Arbitrator Blink)

[1,0,0,0,1,1,0,1/0]
Command used to control on/off of blinking, which is valid only when arbitrator's
blinking is set in the 1-dot unit mode.
Data , which are entered via SI pin after setting D0="1", are taken as arbitrator blink data
(1-dot unit).
Input blink data correspond to each of arbitrator's dots. When "1", blinking is on, and
when "0", blinking is off.
Note that the arbitrator, which arbitrator-on is not specified, is not able to blink, though
blink-setting is available. Dummy data must be entered into the arbitrator blink data D5
thru D7.
It is impossible to write data in addressed 00H through 31H.
D0="0" is set after inputting Reset.

Note)

If blink is set in the 5-dot unit mode, ABB command setting (D0="1" or "0") is
available, but blink-on/off setting via input of display data is impossible.

· AINC (Address Increment)

[1,0,0,X,1,X,1,X]
Command used to increment the value of the address pointer by 1.
The pointer is increment by 1 each time this command is executed. The operation set by
LOT command is given to the address before being increased by 1 each time this
command is execution.

14/30

¡ Semiconductor

MSM6665-xx

· CHB (Character Blink on/off)

[0,X,X,X,0,0,1/0,X]
Command used to control blinking of characters and arbitrator (5-dot unit).
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
For blinking of characters, all lighting-on or all lighting-off, and characters-displaying
are repeated.
Choosing between all lighting-on and all lighting-off is controlled by BPC command.
For arbitrator, only lighting bits repeat lighting-off or lighting-off. The blink control or
arbitrator is valid only when ABBC1/5="0" and in the 5-dot unit mode.
Refer to "BPC".

· CSC (Cursor Control on/off)

[0,X,X,X,0,1,1/0,X]
Command used to control lighting-on and lighting-off of cursor.
This command is executed to the address indicated by the address pointer.The cursor
is lighting on by setting D1="1", and lighting off by setting D1="0".

· CSB (Cursor Blink on/off)

[0,X,X,X,0,1,1/0,X]
Command used to control blinking of cursor.
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
The blinking in the address, where cursor-lighting-on is not specified, does not occur,
though the command of blinking is acceptable. Blinking starts by specifying cursor-
lighting-on.

· CCB (Character & Cursor Blink on/off)

[0,X,X,X,1,1,1/0,X]
Command used to execute both CHB command and CSB command.

· BPC (Blink Pattern Control)

[1,0,0,X,0,0,1,1/0]
Command used to control blink patterns of characters.
When D0="1" is set, all lighting-off (35 dots) and characters-displaying are repeated.
When D0="0" is set, all lighting-on (35 dots) and characters-displaying are repeated.
When D0="1" is set, if characters are blank, their blinkings do not occur in appearance.
When D0="0" is set, if characters are in all lighting-on, their blinkings do not occur in
appearance.
D0 is set to "0" affer inputting Reset.

[D0 = "1"]

[D0 = "0"]

· Increment (+1) in address pointer

When display data or arbitrator data (1-dot unit) is entered or when the following
commands are executed, the address pointer is incremented by 1.
AINC, CHB, CSC, CSB and CCB.

15/30

¡ Semiconductor

MSM6665-xx

8-bit input synchronization is taken by this leading edge.
If input in an 8-bit unit is kept, the following leading edges of CS is not needed.

17D : Max=[Master clock cycle] x 10

9D : Max=[Master clock cycle] x 20

BUSY

LSB

MSB

BUSY

"Z"

don't care

C/D

C / D

C S

S O

S I

SHT

NON-BUSY/

I/O Procedure

· Input timing (command input, display data input)

· Output timing (display code data output)

Code data or arbitrator data indicated by the address pointer is always output, provided
that the SOE command has already been input.

BUSY

LSB

MSB

NON-BUSY/ BUSY

"Z"

don't care

C / D

C S

S O

SHT

Synchronization in an 8-bit unit.

17D : Max=[Master clock cycle] x 10

9D : Max=[Master clock cycle] x 20

NON-BUSY

Note) If CS is set at "L" level when 8-bit read-out is not complete, and CS is set at "H" level again, then

read-out operation is executed, uncomplete data will be output continually and the remaining
read-out data will be zero.

16/30

¡ Semiconductor

MSM6665-xx

Method of Calculating Various Types of Frequencies

· Original Clock Frequency and Blink Frequency

Blink cycle calculation
([Original clock cycle] x 5) x 2

= Blink cycle ............................................. Formula 1

From formula 1, the blink frequency can be calculated.

Example) When the original clock is 80kHz:

Clock cycle Ts=12.5 [

From formula 1,
Blink cycle Tb=(12.5 x 10

-6

x 5) x 2

= 1.024 [s]

Thus,
Blink frequency = 1 [Hz]

· Original Clock Frequency and Frame Frequency

Frame cycle calculation
1/9 DUTY: (Original clock cycle) x 1152 = Frame cycle ............................. Formula 2
1/17 DUTY: (Original clock cycle) x 1088 = Frame cycle ........................... Formula 3
From formulas 2 and 3, the frame frequency can be calculated.

Example) In the original clock 80kHz and 1/17 DUTY specifications:

Clock cycle Ts=12.5 [

From formula 3,
Frame cycle Tf=12.5 x 10

-6

x 1088 = 13.6 [ms]

Thus,
Frame frequency = 73.5 [Hz]

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¡ Semiconductor

MSM6665-xx

Flowchart for Power-On Timing

Turn on power

Reset input

5ms required; external reset input or power-on reset input

CS="H"

The device is enabled.

SOE/D, D0="1"

Make the SO output enable, to perform busy detection.

Wait for 20 clocks

Input a wait for the SOE/D command processing. (For the processing
of each command after this, perform busy detection. *1)

BPC and BKCG

command set

Set the blink pattern and bank change mode.

LOT, I1="1", I0="1"

Set the Load Option. (Blank-code writing and blink-cancellation
are executed each time the AINC command is executed.)

AINC executed 48 times

Input the AINC command to clear the RAM data.

LOT, I1="0", I0="0"

Release the Load Option.

Input display data for initial screen

DISP, D0="1"

Display is turned on and the initial screen is displayed.

Is Input of display data for

initial screen completed?

YES

Normal operation

After the required commands and display data are entered, perform busy detection
based on the SO pin status. When it is confirmed that the status has been changed
from BUSY (SO="L") to NON-BUSY (SO="H"), enter the next data.
If busy detection is not performed, wait for 10 master oscillation clocks when used at
1/17 duty or for 20 master oscillation clocks when at 1/9 duty, then enter the next
data.

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¡ Semiconductor

MSM6665-xx

Codes and Character Fonts of Code -01

00H :

08H :

10H :

18H :

20H : SP

28H : (

30H : 0

38H : 8

01H :

09H :

11H :

19H :

21H : !

29H : )

31H : 1

00H : 9

02H :

0AH :

12H :

1AH :

22H : "

2AH :

32H : 2

3AH : :

03H :

0BH :

13H :

1BH :

23H : #

2BH : +

33H : 3

3BH : ;

04H :

0CH :

14H :

1CH :

24H : $

2CH : ,

34H : 4

3CH : <

05H :

0DH :

15H :

1DH :

25H : %

2DH :

35H : 5

3DH : =

06H :

0EH :

16H :

1EH :

26H : &

2EH : .

36H : 6

3EH : >

07H :

0FH :

17H :

1FH :

27H : '

2FH : /

37H : 7

3FH : ?

23/30

¡ Semiconductor

MSM6665-xx

40H : @

48H : H

50H : P

58H : X

60H : `

68H : h

70H : p

78H : x

41H : A

49H : I

51H : Q

59H : Y

61H : a

69H : i

71H : q

79H : y

42H : B

4AH : J

52H : R

5AH : Z

62H : b

64H : j

72H : r

7AH : z

43H : C

4BH : K

53H : S

5BH : [

63H : c

6BH : k

73H : s

7BH : {

44H : D

4CH : L

54H : T

5CH :

64H : d

6CH : I

74H : t

7CH :

45H : E

4DH : M

55H : U

5DH : ]

65H : e

6DH : m

75H : u

70H : }

46H : F

4EH : N

56H : V

5EH : ^

66H : f

6EH : n

76H : v

7EH : ~

47H : G

4FH : O

57H : W

5FH : _

67H : g

6FH : o

77H : w

7FH : £

24/30

¡ Semiconductor

MSM6665-xx

8ØH : Ä

88H : ä

9ØH : n

98H :

A0H : ¥

A8H :

B0H : --

B8H :

81H : A

89H : a

91H : ö

99H : i

A1H :

49H :

B1H :

B9H :

82H : Æ

8AH : à

92H : Ù

9AH : ¿

A2H :

AAH :

B2H :

BAH :

83H : Ç

93H : ü

9BH : §

A3H :

ABH :

B3H :

BBH :

84H : É

8CH : æ

94H : a

9CH : °

A4H :

aCH :

B4H :

BCH :

85H : N

8DH : ç

95H : b

9DH : ¨

A5H :

ADH :

B5H :

BDH :

86H : Ö

8EH : é

96H : Ø

9EH : º

A6H :

AEH :

B6H :

BEH :

87H : Ü

8FH : è

97H : ø

9FH : ¢

27H :

2FH :

37H :

3FH :

8BH : a

27/30

¡ Semiconductor

MSM6665-xx

PAD CONFIGURATION

Pad layout

Chip size : 6.05 ¥ 4.98mm
Passivation film etched hole : 110 ¥ 110mm

117

C15

2486

2332

Pad Name

X (mm)

Y (mm)

Pad No.

Pad Name

X (mm)

Y (mm)

C14

2336

2332

C13

2186

2332

C12

2036

2332

C11

1886

C10

1736

1586

1436

1286

1136

C5
C4
C3
C2
C1
V

SS5

SS4

SS3

986
836
686
536
386
227

233

SS1

533

2332

683

C/D

833

983

SHT

1133

9D/17D

1283

RST

1433

1583

1733

30
31
32
33
34
35
36
37
38
39

OSC1
OSC2
OSC3
TEST1
TEST2
TEST3
S80
S79
S78
S77

1891
2308
2789
2659
2870
2870
2870
2870
2870
2870

SS2

383

S76

2870

2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332

2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
1797
1647
1347
1197
1047

897
747

Pad No.

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

Pad Coordinates

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¡ Semiconductor

MSM6665-xx

Pad No.

Pad Name

X (mm)

Y (mm)

Pad Name

X (mm)

Y (mm)

S75

2870

567

S74

2870

447

S73

2870

297

S72

2870

147

S71

2870

S70

2870

153

S69

2870

303

S68

2870

453

S67

603

50
51
52
53
54
55
56
57
58
59

S66
S65
S64
S63
S62
S61
S60
S59
S58
S57

753
903

1053
1203
1353
1503
1653
1803
1953
2332
2332
2332

60
61
62
63
64
65
66
67
68
69

S56
S55
S54
S53
S52
S51
S50
S49
S48
S47

2332
2332
2332
2332
2332
2332
2332
2332

70
71
72
73
74
75
76
77
78
79

S46
S45
S44
S43
S42
S41
S40
S39
S38
S37

2332
2332
2332
2332
2332
2332

218
368
518
668

S36

S35

818

2332

S34

968

S33

1118

S32

1268

S31

1418

S30

1568

S29

1718

S28

1868

S27

2018

S26
S25
S24
S23
S22
S21
S20
S19
S18
S17

2168
2318
2468
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870

S16
S15
S14
S13
S12
S11
S10
S9
S8
S7

2870
2870
2870
2870
2870
2870

S6
S5
S4
S3
S2
S1
C17
C16

2870
2870
2870
2870
2870
2870
2870
2870

2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2482
2332
2182
2032
1882
1732
1582
1432
1282
1132

982
832
682
532
382
232

2332
2332
2332
2332
2332

2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
1803
1653
1503
1353
1203
1053

903
753
603
453
303
153

147
297
447
597
747
897

1047
1197
1347
1497
1647
1797

Pad No.

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

29/30

¡ Semiconductor

MSM6665-xx

Pin and Pad Correspondence

The symbol for each chip pad and package pin is equal, but the numbers for each pad and pin
are not equal.
If both chips and packaged devices are used, the number for each chip pad should be
corresponded to the number for each package pin according to each symbol listed in the table
below.

Symbol

Chip Package

Pad

C15

Symbol

Chip Package

Pad

OSC2

100

Symbol

Chip Package

Pad

S55

Pad

S25

C14

OSC3

101

S54

S24

C13

TEST1

102

S53

S23

C12

TEST2

103

S52

S22

C11

TEST3

104

S51

S21

C10

S80

106

S50

S20

S79

107

S49

S19

S78

108

S48

S18

S77

109

S47

S17

S76

110

S46

S16

S75

111

S45

S15

100

S74

112

S44

S14

101

S73

113

S43

S13

102

S72

114

S42

S12

103

S71

115

S41

S11

104

(GND)

S70

116

S40

S10

105

SS5

S69

117

S39

106

SS4

S68

118

S38

107

SS3

S67

119

S37

108

SS2

S66

120

S36

109

SS1

S65

121

S35

110

S64

122

S34

111

C/D

S63

123

S33

112

S62

124

S32

113

SHT

S61

125

S31

114

9D/17D

S60

126

S30

C17

115

RST

S59

127

S29

C16

116

S58

128

S28

117

S57

S27

OSC1

S56

S26

Symbol

Chip Package

30/30

¡ Semiconductor

MSM6665-xx

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

QFP128-P-1420-0.50-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.

Mirror finish

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6665-xx

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6665-xx