1/21

MSM6889

¡ Semiconductor

GENERAL DESCRIPTION

The MSM6889 is best suited to be used as a signal transmitter/receiver LSI for a telemetering
system that employs a no-ringing communication system.

The meter terminal of a telemetering system consists of this device, meter, NCU, and
communication controller.

The MSM6889 contains a PB tone detector, a call progress tone (CPT) detector, a PB tone
generator, and a 300-bps full-duplex modem conforming to ITU-T V.21.

FEATURES

· Power supply : +5 V

10%, +2.5 V or higher for digital interface.

· Power consumption

Operating mode : 9 mA Typ., 12 mA Max.
Power down mode : 0.1 mA Max.

· The operating mode can be selected from PB tone transmit, PB tone detect, and FSK modem

(answer/originate). The FSK modem cannot be operated concurrently with other functions.
Modem test modes are also available.

· The call progress tone (CPT) detector operates in PB tone transmit mode or in FSK modem

mode.

· PB receiver output is 3-state, and externally connectable to 4-bit input for PB tone generator

through the bus line.

· Modem transmit/receive data, carrier detect, request to send, and call progress tone detect

have their dedicated pins.

· Prefilter and smoothing filter are provided in analog input and output.
· On-chip 3.579545 MHz crystal oscillator
· 3.579545 MHz master clock output pin (CMOS compatible)
· Power down mode
· Modem : Conforms to ITU-T V.21 (300 bps, full-duplex)
· Transmit analog signals (modem signal, DTMF tone) : Level is independently adjustable

externally. Carrier detect level is also adjustable externally.

· Package options:

42-pin plastic DIP

(DIP42-P-600-2.54)

(Product name : MSM6889RS)

56-pin plastic QFP

(QFP56-P-1519-1.00-K) (Product name : MSM6889GSK)

E2A0027-16-X1

¡ Semiconductor

MSM6889

Multi-Function Telecommunication LSI

This version: Jan. 1998

Previous version: Nov. 1996

2/21

MSM6889

¡ Semiconductor

BLOCK DIAGRAM

AIN-

AIN+

GAR

2765 Hz

Pre-LPF

SMOOTH

GAT2

GAT1

MOD

VR2

VR1

LPF

Vref

PON

VD2

Power ON

+5 V (A)

0 V (A)

+5 V (D)

0 V (D)

Digital Interface

PB Tone

Generator

PB-Tone Receiver

400 Hz

DET

TIMING

STATUS

I/O

CON-

TROL

Carrier

Detect

FSK Modem

MODE

SELECT

TEST

PB4

PB3

PB2

PB1

CLK

X'tal

3.58 MHz

MODE1

MODE2

MODE3

ICT1

ICT2

ICT3

TEN

PBG1

PBG2

PBG3

PBG4

Micro-

controller

Note) PB1 to PB4: 3-State Outputs

*With pull-up resistor

3/21

MSM6889

¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

42-Pin Plastic DIP

GAR

AIN+

AIN

GAT1

GAT2

MOD

VR1

VR2

PBG1

PBG2

PBG3

PBG4

TEN

VD2

PON

PB4

PB3

PB2

PB1

CLK

MODE3

MODE2

MODE1

ICT3

ICT2

ICT1

NC : No connect pin

4/21

MSM6889

¡ Semiconductor

56-Pin Plastic QFP

PBG4

TEN

ICT1

ICT2

ICT3

MODE1

MODE2

MODE3

AIN

AIN+

GAR

VD2

PON

PBG3

PBG2

PBG1

VR2

VR1

MOD

GAT2

GAT1

CLK

PB1

PB2

PB3

PB4

NC : No connect pin

5/21

MSM6889

¡ Semiconductor

PIN DESCRIPTION

+5 V Power Supply (Analog Circuit).

When power is turned on or the power down mode is released, the

device must be put into the PB tone transmit mode or PB tone

detect mode.

Output, non-inverting input and inverting input pins of on-chip

operational amplifier.

No hybrid transformer is required by use of these pins. (See Fig. 2.)

GAR

AIN+

AIN

Analog signal output.

PB tone or modem transmit signal is output from this pin.

On-chip signal ground, having a potential of about +2.5 V.

GAT1

GAT2

MOD

PB is the PB tone output and MOD is the modem signal output.

By connecting external resistors to GAT1 and GAT2 pins, signal level can

be set at required values for the modem signal and

the PB tone that are output from AO, independently. (See Fig. 3.)

These pins are used to externally adjust the received carrier

detect(CD) signal level.

The potential of VR1 to SG is about +1.1 V. The carrier

detect level can be set at the required value by a on-chip resistor

divider between VR1 and SG. The given potential to VR2 is set

about +0.88 V with high resistance inside the IC. (See Fig. 4.)

VR1

VR2

Analog Ground, 0 V.

PBG1

PBG2

PBG3

PBG4

Inputs used to specify PB tone to be sent.

PB1 to PB4 can be connected externally like 4-bit bus line. Data is

latched at the falling edge of TEN. (See Fig. 7 and Fig. 8.)

Description

I/O

Name

Pin Number

* Digital input pulled up by a high resistance inside the IC.

6/21

MSM6889

¡ Semiconductor

PB tone transmit enable.

PBG1 to PBG4 data are latched at the falling edge of TEN, and PB

tone is generated at digital "0" level. (See Fig. 7.)

TEN

Modem transmit serial data input.

Data stream less than 300 bps should be input.

Digital "1" and "0" correspond to "Mark" and "Space" respectively.

Request to send data input .

While RS is at digital "0" level, modem transmit is enabled.

Digital Ground, 0 V.

ICT2

ICT3

Used to check performance characteristics of the IC.

Description

I/O

Name

Pin Number

Input used to select call progress tone (CPT) detect output

waveform. (See Fig. 9.)

ICT1

Independent of operating mode. Leave these pins open.

MODE1

MODE2

Inputs used to specify operating mode.

(See Table 1.)

MODE3

3.579545 MHz crystal resonator should be connected to X1 and X2.

When applying external clock to the device, it should be connected

to X2 through the AC coupling capacitor of 100 pF and X1 has to be

open.

3.579545 MHz clock output.

CLK

Modem receive serial data output.

Digital "1" and "0" correspond to "Mark" and "Space" respectively.

When CD (Carrier Detect) is off, RD is hold at "Mark" state.

Carrier Detect output.

Digital "0" and "1" represent "Detect" and "No-detect" respectively.

* Digital input pulled up by a high resistance inside the IC.

7/21

MSM6889

¡ Semiconductor

Call progress tone (CPT) detect output.

When a CPT is detected, the waveform selected by ICT1 is output.

(See Fig. 9. )

Description

I/O

Name

Pin Number

PB2

PB3

Receive PB tone code outputs.

The output impedance of these pins becomes high except when the

device operates as PB tone receiver. (See Fig. 7 and Fig. 8. )

PB4

+5 V power supply (digital circuit).

When power is turned on or the power down mode is released, the

device must be put into the PB tone transmit mode or PB tone

detect mode.

PB1

PB tone receive data present.

Digital "1" represents that this pin is receiving the PB tone.

(See Fig. 8. )

PON

Power down mode select. Digital "1" on this pin puts the whole

circuit of the device into the power down state.

No connection.

VD2

Power supply for digital interface output.

The supply voltage from +2.5 V to VD is possible for VD2. For

example, when the device interfaces to the MCU working on +3 V

supply, the +3 V supply has to be applied to the VD2 pin.

Note that this function is effective to all of digital output pins

except X1, X2, and CLK.

There is no restriction regarding the power supplies (VD and VD2)

applying procedure.

8/21

MSM6889

¡ Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter

Condition

VA, VD

VD2

Rating

0.3 to 7

0.3 to VD

0.3 to VA(VD) + 0.3

65 to 150

260

Unit

°C

Symbol

Power Supply Voltage

Input Pin Voltage

Storage Temperature

Pin Soldering Temperature

Ta = 25°C

with respect to AG and DG

Within 10 sec

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage

Symbol

VA, VD

VD2

4.5

2.5

5.0

5.5

Digital Input Voltage

2.0

0.8

Digital Output Current

0.05

0.4

When VD2 = VD

(excluding) X2

+85

°C

Operating Temperature

CLK

0.1

+0.1

Input Clock Frequency

Bypass Capacitance

VD, VD2

0.1 + 10

Frequency Deviation

At 25°C ±5°C

100

+100

ppm

At 40°C to ±85°C

+50

Temperature

Characteristics

Equivalent Series

Resistance

Load Capacitance

Crystal

Condition

Min.

Typ.

Max.

Unit

Parameter

9/21

MSM6889

¡ Semiconductor

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(VA, VD, VD2 = +5 V ±10%, Ta = 40°C to +85°C)

Digital Output

Voltage

O =

Min.

2.4

VD2

Digital Input

Current*

I =

Max.

Power Supply

Current

PON = "0"

PON = "1"

0.01

0.1

I =

Min.

100

O =

Max.

0.4

+ I

(VD2 = VD)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Condition

* Internal pull-up resistor

VD2 = VD

Analog Interface and Dynamic Characteristics

Parameter

Condition

Min.

Typ.

Max.

Unit

VA
2

VA + 0.1

(VD = VA = 5 V ±10%, Ta = 40°C to +85°C)

dBm

P-P

2.46

1.95

1.55

PBG1 to PBG4 Input Data Hold

Time

PBG1 to PBG4 Input Data Setup

Time

PB Tone Distortion

PB Tone Frequency

Out-of-band Energy

Modem Transmit Carrier

Frequency

Output DC Voltage

Signal Level Relative Value

Output Load Resistance

Output Voltage Swing

PB Tone Send Level

Modem Transmit Level

MOD

MOD, PB, GAT2, AO

MODEM

PB Tone

MOD, PB
AO (When GAT1 and GAT2 are

connected)

With respect to nominal frequency

Harmonics/Fundamental

TPBGS, Fig. 7

TPBGH, Fig. 7

20 kW

"Mark" and "Space" Signals

20 kW

Low-Group Tone

High-Group Tone

"Mark" & "Space" Signals

High-Gr. Tone & Low-Gr. Tone

P : In-band Signal Energy

(0.3 kHz to 3.4 kHz)

Measured at primary side

of transformer line.

4 to 8 kHz

8 to 12 kHz

12 kHz to

8.5

7.5

2.2

0.1

976

1176

1.5

250

VA
2

6.5

5.5

980

1180

4.5

3.5

984

1184

P-20

P-40

P-60

+1.5

dBm

Vp-p

1646

1846

1650

1654

1850

1854

Originate

Mode

Answer

Mode

MARK

SPACE

MARK

SPACE

"1"

"0"

"1"

"0"

10/21

MSM6889

¡ Semiconductor

Analog Interface and Dynamic Characteristics (Continued)

(VD = VA = 5 V ±10%, Ta = 40°C to +85°C)

Parameter

Condition

Min.

Typ.

Max.

Unit

Modem Receive Signal Level

AIN+, FSK Demodulator Signal

dBm

Carrier Detect (CD) Signal

Level

VR2; Open

dBm

OFFÆON

ONÆOFF

Answer mode: 1080 Hz

Originate mode: 1750 Hz

dBm

Answer mode: 1080 Hz

Originate mode: 1750 Hz

CD Level Hysteresis

60 dBm Æ 20 dBm Step

CD Delay Time

20 dBm Æ 60 dBm Step

CD Hold Time

300 bps, 1/0 Alternative Pattern

±10

Demod. Data Bias Distortion

vNRTS/v Receive Modem Signal

NRTS: 2765 Hz ±30 Hz

NRTS Signal-to-Modem

Receive Signal Ratio

400 Hz

dBm

CPT Detect Level

400 Hz

dBm

CPT Non-detect Level

R > 20% (square waves output)

(See Fig. 9)

380

420

CPT Detect Frequency

R > 20% (square waves output)

(See Fig. 9)

CPT Non-detect Frequency

500

300

CPT Detect Delay Time

CPT Detect Hold Time

For Each Signal Tone

dBm

PB Tone Detect Amplitude

For Each Signal Tone

dBm

PB Tone Non-detect Amplitude

With respect to Nominal Frequency

±1.5

Detect Frequency

With respect to Nominal Frequency

±3.8

Non-detect Frequency

High-Gr. Tone/Low-Gr. Tone

Allowable twist

Noise (0.3 kHz to 3.4 kHz)

Level/Tone Level

Allowable Noise Level

380 Hz to 420 Hz

Dial Tone Rejection Ratio

120

Signal Repetition Time

Time to Receive

Invalid Tone Duration

Output Delay Time

Interdigit Pause

Acceptable Drop Out

SP Delay Time

Output Trailing edge Delay

Fig. 1

Input Impedance

AIN+, 0 to 10 kHz

12/21

MSM6889

¡ Semiconductor

Figure 2

is an ignorable impedance in the voice frequency band; therefore, if a line transformer and

phone line impedance are ideal (R

= 600 W pure resistance), the signal levels at each point are

as shown below.

VT, VR

: Transmit at 2W on phone line, receive signal level (balanced)

VT1, VR1

: Transmit at pin 3 (AIN+), receive signal level (unbalanced)

VAO

: Transmit signal level at pin 5 (AO) (unbalanced)

VT2

: Leaking of transmit signal into receive circuit (unbalanced)

VR2

: Receive signal level of the device (unbalanced)

1) VT = VT1 = 1/2 ¥ VAO

The transmit signal level (voltage) on phone line is half the level at the output pin (AO) of the
device. (600 W : a 600 W line transformer is used)

2) VR1 = VR

Then, where R2 = R3 (e.g., 51 kW), VT2 = 0.

This means that the transmit signal is no longer leaking into the receive circuit.

VT VR

600 W : 600 W

2.2 mF

600 W

VT1,VR1

VAO

R2,R3 20 kW

AIN+

AIN

GAR

VT2,VR2

FUNCTIONAL DESCRIPTION AND APPLICATION

Resistance Hybrid Condition (Ideal Condition)

VT2 = VT1 ¥ (1+ ) + VAO ¥ ( )

R3
R2

= VAO ¥ (1+ ) VAO ¥ = VAO ¥ (1 )

R3
R2

1
2

R3
R2

1
2

VR2 = VR1 ¥ (1+ ) , where R2 = R3, VR2 = 2 ¥ VR1 = 2 ¥ VR

R3
R2

13/21

MSM6889

¡ Semiconductor

Figure 3

The modulation analog signal and PB tone from the modem are not sent at a time. The signal to
be sent is determined by the operating mode specified.
This device is provided with the pins for specifying levels of these transmit signals independently.
The answer tones, which are generated from MODULATOR, are handled as modem signals.

VM : Modem signal level (voltage) at MOD (pin 9)
VP

: PB tone level (voltage) at PB (pin 10)

When the external resistors are R4, R5 and R6, the signal levels at AO (pin 5) are as shown below.

Note : R4, R5, R6

20 kW

As described in "Resistance Hybrid Condition", signal levels actually sent over a phone line will
be half the above mentioned values under the ideal condition.

Setup of Transmit Signal Levels

VAO

GAT2

GAT1

MOD

PB Tone
Generator

Modulator

R4,R5,R6 20 kW

LPF

+
_

VAO (modem) =

VAO (PB) =

14/21

MSM6889

¡ Semiconductor

External Setup of Carrier Detect Level

VR1

VR2

VREF

COMP

R1//r1 + R2//r2 20 kW

r1: 250 kW, r2 : 1 MW

Mode Select

Functional Block

Operating Mode

CPT REC.

PB GEN.

PB REC.

FSK

MODEM ICT1 = "1" ICT1 = "0"

PB Tone Transmit

PB Tone Detect

Originate Mode

Modem (O)

Answer Mode

Modem (A)

Analog Loop Back

Test (ALB)

Remote Digtal Loop

Back Test (RDLB)

* : Active

When power is turned on or the power down mode is released, put the device into the PB tone
transmit mode or PB tone detect mode.

Figure 4

Operating Mode

Table 1 Operating Mode Table

15/21

MSM6889

¡ Semiconductor

Line

AIN

Transmit

Filter

Demodulator

Modulator

Receive Data

Transmit
Data

Receive

Filter

Signal flow concept for the modem normal operating mode is shown in Fig. 5.

Figure 5

In the test modes, signal flow shown in Fig. 6 is used. O/(originate)/A(answer) in the test mode
is the expression where the modulator side is referred to as the basis.

[ALB]

AIN

Receive

Filter

Demodulator

Receive Data

Transmit
Data

[RDLB]

AIN

Receive

Filter

Demodulator

Modulator

Receive Data

Transmit
Data

Transmit

Filter

Modulator

Transmit

Filter

Figure 6

16/21

MSM6889

¡ Semiconductor

PB Tone Transmit Mode and PB Tone Detect Mode
When PBG1 to PBG4 are externally connected to PB1 to PB4 so as to use them as 4-bit bus lines,
their tone generation timings are as shown below.

PB Tone Transmit Mode
When TEN is in the digital "0" state, PB tone is generated according to Table 2.

TEN

PBG1/PB1

PBG2/PB2

PBG3/PB3

PBG4/PB4

TPBGS

TPBGH

941 Hz + 1477 Hz

Figure 7

PB Tone Detect Mode

AIN

PB1/PBG1

PB2/PBG2

PB3/PBG3

PB4/PBG4

"0"

"1"

"0"

"1"

TSP

"0"

941 Hz + 1477 Hz

852 Hz + 1209 Hz

Figure 8

17/21

MSM6889

¡ Semiconductor

Table 2 PB Tone Code Table

Button

Low-Group Freq. (Hz)

High-Group Freq. (Hz)

697

770

852

941

1209

1336

1477

1633

PB4/

PBG4

PB3/

PBG3

PB2/

PBG2

PB1/

PBG1

Call Progress Tone (CPT) Detect Mode

AIN

ICT1 = "1"

ICT1 = "0"

400 Hz

TW TD

R = TW/(TD + TW) ¥ 100 [%]

Figure 9

18/21

MSM6889

¡ Semiconductor

APPLICATION CIRCUIT

Pin Connection

GAR

AIN+

AIN

GAT1

GAT2

MOD

VR1

VR2

PBG1

PBG2

PBG3

PBG4

TEN

VD2

PON

PB4

PB3

PB2

PB1

CLK

MODE3

MODE2

MODE1

ICT3

ICT2

ICT1

MSM6889RS

3.579545

MHz

R1 = 600 W, R2 = R3 = R4 = R5 = R6 = 51 kW
C1 = 2 mF, C2 = C3 = 10 mF

19/21

MSM6889

¡ Semiconductor

Bypass Capacitor Connections

The MSM6889 contains analog circuits.

Note that noise occurred in the power supply by trouble in other circuits may cause degradation
in characteristics of the device.

The examples of connected bypass capacitors of the MSM6889 are shown below.

VA, VD

AG, DG

MSM6889

10 mF to 47 mF

VA, VD

AG, DG

MSM6889

10 mF to 47 mF

1 mF

VA, VD

AG, DG

MSM6889

10 mF to 47 mF

*1 mF

10 mF

* Laminated ceramic capacitor

21/21

MSM6889

¡ Semiconductor

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

QFP56-P-1519-1.00-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
1.46 TYP.

Mirror finish

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6889RS

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6889RS