¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

1/21

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

Single Chip CODEC

GENERAL DESCRIPTION

The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel
CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from
300 Hz to 3400 Hz.

FEATURES

· Compliance with ITU-T companding Law

MSM6996H/MSM6996V/MSM6998 :

A-law

MSM6997H/MSM6997V/MSM6999 :

m-law

· Capable of independent operation of transmission and reception
· Transmission clock in the range of 64 kHz to 2048 kHz
· Adjustable transmit gain
· 600 W drive for analog output

MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive
MSM6998/MSM6999 Push-pull drive

· Built-in analog loop back fanction

MSM6996V/MSM6997V

· Built-in reference voltage source
· Low Power Dissipation (60 mW to 70 mW Typ.)
· Package options :

16-pin plastic DIP (DIP16-P-300-2.54)

(Product name : MSM6996HRS/MSM6997HRS)
(Product name : MSM6996VRS/MSM6997VRS)
(Product name : MSM6998RS/MSM6999RS)

16-pin cer DIP (DIP16-G-300-2.54-1)

(Product name : MSM6996HAS/MSM6997HAS)
(Product name : MSM6996VAS/MSM6997VAS)
(Product name : MSM6998AS/MSM6999AS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K)

(Product name : MSM6996VGS-K/MSM6997VGS-K)
(Product name : MSM6998GS-K/MSM6999GS-K)

E2U0010-28-81

This version: Aug. 1998

Previous version: Nov. 1996

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

2/21

BLOCK DIAGRAM

MSM6996H/V
MSM6997H/V

AIN+

AIN

GSX

AOUT

XSYNC

XCLOCK

PCMOUT

RCLOCK

RSYNC

PDN/BS

PCMIN

Voltage

REF.

5th

LPF

3rd

HPF

Auto

Zero

C Ladder

SAR

Receive

Controller

Transmit

Controller

R.PWD

COMP

SAMPLE

5th

LPF

MSM6998, MSM6999

AIN+

AIN

GSX

AOUT+

Voltage

REF.

Pre Filter

5th

LPF

3rd

HPF

Auto

Zero

SAR

COMP

SAMPLE

5th

LPF

AOUT

Transmit

PLL

Receive

PLL

T.PWD

TMC

XSYNC

XCLOCK

PCMOUT

RCLOCK

RSYNC

PDN/BS

PCMIN

Receive

Controller

Transmit

Controller

R.PWD

Transmit

PLL

Receive

PLL

T.PWD

1 BS : Only MSM6997H/V

2 Only MSM6996V, MSM6997V

3 BS : Only MSM6999

Pre Filter

C Ladder

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

3/21

16-Pin Plastic DIP

MSM6996HRS
MSM6997HRS

16-Pin Plastic DIP

MSM6996VRS
MSM6997VRS

16-Pin Plastic DIP

MSM6998RS
MSM6999RS

AIN+

AIN

GSX

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

16-Pin Cer DIP

MSM6996HAS
MSM6997HAS

16-Pin Cer DIP

MSM6996VAS
MSM6997VAS

16-Pin Cer DIP

MSM6998AS
MSM6999AS

RSYNC

AIN+

AIN

GSX

AOUT

TMC

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN

GSX

AOUT+

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN

GSX

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN

GSX

AOUT

TMC

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN

GSX

AOUT+

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

PIN CONFIGURATION (TOP VIEW)

NC : No connect pin

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

4/21

24-Pin Plastic SOP

MSM6996HGS-K
MSM6997HGS-K

AIN+

AIN

GSX

AOUT

PCMOUT

PDN/BS

XSYNC

RSYNC

24-Pin Plastic SOP

MSM6996VGS-K
MSM6997VGS-K

PCMIN

XCLOCK

RCLOCK

24-Pin Plastic SOP

MSM6998GS-K
MSM6999GS-K

AIN+

AIN

GSX

AOUT

TMC

PCMOUT

PDN/BS

XSYNC

RSYNC

PCMIN

XCLOCK

RCLOCK

AIN+

AIN

GSX

AOUT+

AOUT

PCMOUT

PDN/BS

XSYNC

RSYNC

PCMIN

XCLOCK

RCLOCK

NC : No connect pin

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

5/21

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN, GSX

These three pins are used for the transmit level adjustment.
AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit
amplifier.
AIN is an inverting analog input pin which is connected to the inverting input of the transmit
amplifier.
GSX is a transmit amplifier output pin.
Adjustment can be done by following method.

AIN

Gain = 1 +

AIN+

GSX

Active

Filter

Analog
Input

R2
R3

< 10

Notes: 1. R

+ R

> 10 kW

2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should

provide for DC blocking.
In this case, cut-off frequency of HPF, composed by R

and C

, should be less than 30 Hz.

3. R

should be less than 20 kW

AG is an analog ground.
AG is connected to the analog system ground.

AOUT

AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V.
The output voltage range is 5 V

. This output can drive the 600 W resistor.

AOUT+, AOUT

Analog output for the MSM6998 and MSM6999.
The output signal amplitudes are 5 V

. The AOUT output is inverted to the AOUT+ output. These

outputs can drive a 600 W impedance.

is the positive power supply.

The voltage supplied to this pin should be +5 V

5%.

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

6/21

PCMIN

PCM signal input.
The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous
signal RSYNC and clock signal RCLOCK.
The data rate of PCM signal ranges from 64 kbps to 2048 kbps.
The PCM signal is read at the falling edge of the clock signal and latched into the internal register
when finished to read eight bits data.
The top of the PCM data is specified by RSYNC pulse timing.

RCLOCK

Receive clock pulse input.
The frequency of this clock pulse should be identified with the data rate of PCM input signal at the
PCMIN pin.
This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.

XCLOCK

Transmit clock input.
The PCM output data rate from the PCMOUT pin is set by this clock frequency.
The applicable clock frequencies range from 64 kHz to 2048 kHz.
This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.

MSD

PCMOUT

XCLOCK

XSYNC

9 Clocks are required

MSD

PCMIN

RCLOCK

RSYNC

9 Clocks are required

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

7/21

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
The whole timing signal in the receive section are synchronize by this synchronizing signal.
This signal must be synchronize in phase with RCLOCK.
The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics of receive section.

However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz

2 kHz, with

no guarantee of adherence to the electrical characteristics in this specification as a catalogue value.
Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal.
All transmit timing signals are triggered to synchronize with this signal. This signal should be
synchronized in phase with XCLOCK pulse.
The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics of transmit section.

Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state.

Ground of digital signal.
This pin is electrically separated from the AG pin in this device.
The DG pin must be connected to the AG pin on the printed circuit board to make common to the
AG pin.

PDN/BS

Power down signal input.
When this input is held at low level more than 1 ms, the device is put into the power-down mode.

PCMOUT

PCM signal output.
The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly
from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse,
according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except
the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily
possible at this pin.
The code companding law and output code format depend on ITU-T Recommendation G.711, and
for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by
inverting the even bits of signals.

Input/Output

Level

+Full scale

+0
0

Full scale

PCMIN/PCMOUT

MSM6996 (A-law)

MSM6997 (

m-law)

MSM6998 (A-law)

MSM6999 (

m-law)

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

9/21

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

* : The value for the MSM6997 and MSM6999

Parameter

Power Supply Voltage

Analog Input Voltage
Digital Input Voltage
Storage Temperature

Symbol

AIN

DIN

STG

Rating

0 to 7

0.3 to V

+ 0.3

0.3 to V

+ 0.3

55 to +150

Unit

V
V

°C

7 to 0

Condition

--
--
--

(Ta = 0°C to 70°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

Analog Input Voltage

AIN

Input High Voltage
Input Low Voltage

--
--

Connect AIN and GSX

XSYNC, XCLOCK, PCMIN,

RSYNC, RCLOCK, TMC, PDN/BS

4.75

5.25

4.75

P-P

2.0

0.8

Clock Frequency

XCLOCK, RCLOCK

kHz

Sync Pulse Frequency

XSYNC, RSYNC

kHz

Clock Duty Ratio

XCLOCK, RCLOCK

Digital Input Rise Time

Digital Input Fall Time

XSYNC, XCLOCK, PCMIN,

RSYNC, RCLOCK (Fig. 1)

Transmit Sync Timing

100

XCLOCKÆXSYNC (Fig. 2)
XSYNCÆXCLOCK (Fig. 2)

Receive Sync Timing

100

RCLOCKÆRSYNC (Fig. 2)
RSYNCÆRCLOCK (Fig. 2)

1/fc

Transmit Sync Pulse Width
Receive Sync Pulse Width

100

PCMIN Set-up Time
PCMIN Hold Time

200

BS Set-up Time *

200

BS Hold Time *

600

Analog Output Load

100

Digital Output Load

100

AOUT, AOUT+, AOUT

200

+200

Allowable Analog Input
Offset Voltage

Transmit gain stage, Gain = 1

2048

+20

Transmit gain stage, Gain = 10

GSK

Operating Temperature

°C

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

10/21

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

* : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999

= +5 V ±5%, V

= 5 V ±5%, Ta = 0°C to 70°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Current

Power Supply Current
(Stand-by)

DD1

SS1

DD2

SS2

Input High Voltage

XCLOCK, RCLOCK

2048 kHz

7.0

6.5

3.0

1.5

2.2

Input Low Voltage

< 0.5

2.0

Input Leakage Current

< 0.2

0.5

Output Leakage Current

< 5

Analog Output Offset Voltage

OFF

150

+150

Input Capacitance

< 3.4 kHz

Analog Input Resistance

(Operating)

0.8

0.1

0.4

Output Low Voltage

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

11/21

AC Characteristics

Parameter

Transmit Frequency Response

Symbol

OSS

Level

Min.

Typ.

Max.

Unit

= +5 V ±5%, V

= 5 V ±5%, Ta = 0°C to 70°C)

Freq.

Condition

OSS

300

0.15

+0.25

OSS

820

Reference

OSS

2020

0.15

+0.25

OSS

3000

0.15

+0.25

OSS

3400

0.8

Receive Frequency Response

OSS

300

0.1

+0.2

OSS

820

Reference

OSS

2020

0.1

+0.2

OSS

3000

0.1

+0.2

OSS

3400

0.8

Transmit Signal to Noise

SD T1

SD T2

SD T3

SD T4

1020

SD T5

SD R1

SD R2

SD R3

SD R4

1020

SD R5

(dBm0)

(Hz)

Ratio *1

Receive Signal to Noise
Ratio *1

820

Transmit Gain Tracking

GT T1

0.2

+0.2

1020

Reference

0.2

+0.2

0.4

+0.4

0.8

+0.8

Receive Gain Tracking

GT R1

0.2

+0.2

GT R2

Reference

GT R3

1020

0.2

+0.2

GT R4

0.4

+0.4

GT R5

0.8

+0.8

GT T2
GT T3
GT T4
GT T5

10
40
50
55

820

Note: *1 The measurement is taken with P-message filter

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

12/21

AC Characteristics (Continued)

Parameter

Symbol

Level

Min.

Typ.

Max.

Unit

= +5 V ±5%, V

= 5 V ±5%, Ta = 0°C to 70°C)

Freq.

Condition

Idle Channel

IDL

0.75

500

0.35

0.125

0.75

0.35

0.125

(dBm0)

(Hz)

Noise

Transmit Group Delay Time

Transmit
Receive

dBmOp

Absolute Gain

AV T

0.5

+0.5

AV R

0.5

+0.5

1020 or 820

Transmit
Receive

1020 or 820

0.52

Absolute Delay Time

600

1000

2600

2800

0.75

500
600

1000
2600
2800

Receive Group Delay Time

0.125

Crosstalk Attenuation

1020 or 820

T to R
R to T

1020 or 820

Out-of-Band Spurious

dBmO

300 to 3400

IMD 1

dBmO

= 470

Intermodulation Distortion

= 320

Noise Rejection

PPSR T

PPSR R

Transmit
Receive

Noise Rejection

NPSR T

NPSR R

200

Transmit
Receive

0 to 300

mVp-p

Ratio

kHz

Discrimination

DIS

4.6 kHz to

72 kHz

100

= 2 kW

XD1

XD2

XD3

150

300

100

300

100

300

180

300

Digital Output Delay Time

Digital Output Fall Time

= 100 pF

Notes: *1 The measurement is taken with P-message filter

*2 MSM6996/MSM6998 0 dB = 1.231 Vrms

MSM6997/MSM6999 0 dB = 1.227 Vrms

*3 Reference : 1800 Hz

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

13/21

TIMING DIAGRAM

Wave Time Measurement Level

DOf

2.4 V

1.4 V

0.4 V

Note: Timing between signal waves is judged at 1.4 V

2.4 V

1.4 V

0.4 V

Basic Timing

XCLOCK

XD1

XD2

XD3

1/f

MSD

Transmitter
Section

Receiver
Section

XSYNC

PCMOUT

RCLOCK

RSYNC

Note 1):

When t

£ 1/2 ¥ fc, the Delay of the MSD bit is defined as t

XD1

When t

£ 1/2 ¥ fc, the Delay of the MSD bit is defined as t

Note 2):

Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be
asynchronous mutually.

Note 3):

The threshold level is 1.4 V.

PCMIN

MSD

Invalid Data

Figure 1

Figure 2

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

14/21

RSYNC

Allowable Range

8 Bits Decode

7 Bits Decode

8 Bits Decode

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 9

Disable

PCMIN

RCLOCK

Decoder

Operation

Notes: Follow these procedures when the Bit-steal function is used:

1. Set the RSYNC pin to OFF ("L") after the PDN/BS pin is set at "H" for 10ms or more.
2. Set the RSYNC to ON after a pulse is input at the PDN/BS pin.
3. The Bit-steal function starts to operate.

more than 10ms

RSYNC

PCMIN

RCLK

,,,,

more than 10ms

PDN/BS

125

~ ~

Timing for 7 bits Decode (Specified for MSM6997/6999)

Figure 3

Timing for Bit-steal Function Setting

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

15/21

APPLICATION CIRCUIT

Basic Circuit

Notes: 1. Insert diode for preventing from Latch-Up at turn on Power.

Recommended Diode Specification.
· High Speed Switching
· Allowerable Power dissipation 250 mW to 300 mW
· Forward Voltage Drop < 1.3 V (at 100 mA)

2. AG and DG must be connected in the printed circuit board mounted this device, for

preventing from Latch-Up.

2 kW

OUT

X R

OUT

PCM

ANALOG

+5 V

Note 1

0 V

5 V +5 V

Power Down
1 : NOR
0 : Power Down

R E C

E C

15 10 9

16 6

+5 V

10 M

XTAL
2.048 MHz

4049

AIN+

AOUT

PDN/BS

OUT

M4520RS

GSX AIN

10 mF

CLOCK SYNC

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

16/21

Example of Multi-Channel Connections (8ch)

No.1

8 No.1 2

7 8

MSD

LSD

Output

Multiple PCM

512K CLK

74161(1)

74161(2)

74164

Output

Example of Multi-Channel Timing

1 kW

+5 V

Multiple
PCM

PCM

OUT

PCM

CLR Q

12
11
15

CLR Q

+5 V

512 kHz

+5 V

5
6

74161(1)

74161(2)

74164

No.7

No.6

No.5

No.4

XS
RC
RS

No.1

No.3

No.8

CLR

+5 V

No.2

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

17/21

Transmit and Receive Level Adjustment (MSM6996H/V, MSM6997H/V)

4WS
600 W

AIN+

AOUT

a. Transformer of turns ratio 1 : 1

1 : 1

600 W

20 kW

4WR
600 W

1 : 1

600 W Attenuator

600 W

1
2
3

AIN
GSX

4WS
600 W

AIN+

AOUT

300 W

20 kW

4WR
600 W

300 W Attenuator

300 W

1
2
3

AIN
GSX

b. Transformer of turns ratio 1 : 2

2 : 1

4WS
600 W

AIN+

AOUT+

1 : 1

600 W

20 kW

4WR
600 W

1 : 1

600 W Attenuator

300 W

1
2
3

AIN
GSX

300 W 6

AOUT

Transmit and Receive Level Adjustment (MSM6998, MSM6999)

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +7.17 + L

(dBm)
4 WR maximum output level = +1.15 L

(dBm)
L

: Transformer loss

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +10.18 + L

(dBm)
4 WR maximum output level = +4.16 L

(dBm)
L

: Transformer loss

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +7.17 + L

(dBm)
4 WR maximum output level = +7.17 L

(dBm)
L

: Transformer loss

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

18/21

RECOMMENDATIONS FOR ACTUAL DESIGN

· To assure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

· Connect the AG pin and the DG pin each other as close as possible.

Connected to the system ground with low impedance.

· Mount the device directly on the board when mounted on printed circuit board.

Do not use IC sockets.
If an IC socket is unavoidable, use the short lead type socket.

· When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source

such as power supply transformers surround the device.

· Keep the voltage on the V

pin not lower than 0.3 V and the voltage on the V

pin more than

+0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on.

· Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power

supply to avoid erroneous operation and the degradation of the characteristics of these devices.

¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

21/21

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SOP24-P-430-1.27-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.

Mirror finish

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6999GS-K

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM6999GS-K