1/15

MSM7540L/7560L

¡ Semiconductor

MSM7540L/7560L

Single Rail ADPCM CODEC

GENERAL DESCRIPTION

The MSM7540L/7560L are single channel ADPCM CODEC ICs which perform mutual transcoding
between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data.
Using advanced circuit technology, these devices operate from a single 3 V power supply and
provide low power consumption.
The MSM7540L/7560L are optimized for advanced digital cordless telephone system applications.

FEATURES

· Single 3 V Power Supply Operation
·

· ADPCM Algorithm :

Complies completely with 1988's version ITU-T

G.721 (32 kbps)

· Transmit/Receive Full-Duplex Operation
·

· Transmit/Receive Synchronous Mode Only
·

· Serial ADPCM Transmission Data Rate :

32 kbps to 2048 kbps

· Serial PCM Transmission Data Rate :

64 kbps to 2048 kbps

· PCM Interface Coding Format

MSM7540L :

A-law or Linear (14 bit, 2's compliment) Selectable

MSM7560L :

m-law or Linear (14 bit, 2's compliment) Selectable

· Low Power Consumption

Operating Mode :

18 mW Typ. (V

= 3.0 V)

Power-Down Mode :

0.3 mW Typ. (V

= 3.0 V)

· Two Analog Input Amplifier Stages :

Externally Adjustable Gain

· Analog Output Stage :

Push-pull Drive (direct drive of 350 W + 120 nF)

· Built-in Crystal Oscillator (10.368 MHz)
·

· Built-in Reference Voltage Supply
·

· Option Reset Specified by ITU-T G. 721/ADPCM
·

· Package:

28-pin plastic SOP

(SOP28-P-430-1.27-K)

(Product name: MSM7540LGS-K)
(Product name: MSM7560LGS-K)

32-pin plastic TSOP

(TSOPI32-P-814-0.50-1K) (Product name: MSM7560LTS-K)

E2U0027-28-83

This version: Aug. 1998

Previous version: Nov. 1996

3/15

MSM7540L/7560L

¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

RES

PCMRI

PCMRO

PCMSI

PCMSO

LPS

AIN1

GSX1

AIN2

GSX2

VFRO

PWI

AOUT

AOUT+

PDN

MCK

RSYNC

XSYNC

BCLKA

BCLKB

28-Pin Plastic SOP

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

X1
X2

MCK

RSYNC

XSYNC

BCLKA
BCLKB

RES

PCMRI

PCMRO

PCMSI

PCMSO

PDN
V

NC
AOUT+
AOUT
PWI
VFRO
GSX2
AIN2
GSX1
AIN1
SG
AG
NC
DG
LPS

NC: No connection

32-Pin Plastic TSOP

4/15

MSM7540L/7560L

¡ Semiconductor

PIN AND FUNCTIONAL DESCRIPTIONS

AIN1, AIN2, GSX1, GSX2

Transmits analog input and the output for transmit gain adjustment.
AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2)
connects to the output of the internal transmit amplifier output. Refer to Fig. 1 for gain
adjustment.

VFRO, AOUT+, AOUT, PWI

Receives analog output and the output for receive gain adjustment.
VFRO is receive filter output. AOUT+ and AOUT are differential analog signal outputs which
can directly drive Z

= 350 W + 120 nF. Refer to Fig. 1 for gain adjustment.

Figure1 Analog Input/Output Interface

AIN1

GSX1

Analog Input

to ENCODER

from DECODER

Analog Output

=120 nF

+ 350

*: Side Tone Pass (Gain = R6/RS)

AIN2

GSX2

AOUT

PWI

RS*

VFRO

AOUT+

Transmit Gain:
= (R2/R1)

¥ (R4/R3)

Receive Gain:
= (R6/R5)

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MSM7540L/7560L

¡ Semiconductor

Analog signal ground voltage output.
The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin
and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if
necessary, should be used via a buffer.

Analog ground.

Digital ground.
This ground is separated internally from the analog signal ground pin (AG). The DG pin must
be kept as close as possible to AG on the PCB.

+3 V power supply.

LPS

PCM coding law selection.
MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).

PDN

Power down control input.
If this pin is "0", this device is in the power-down state.
Normally, this pin is set to "1".

RES

Optional reset input specified by ITU-T Recommendation G. 721.
If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125 ms or
more.

MCK

Master clock input.
The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,
BCLKB, XSYNC, and RSYNC.

PCMSO

Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.

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MSM7540L/7560L

¡ Semiconductor

PCMSI

Transmit PCM data input.
This signal is converted to transmit ADPCM data. PCM is shifted in synchronization with the
falling edge of BCLKB. Normally, this pin is connected to PCMSO.

PCMRO

Receive PCM data output.
PCM is the output signal after ADPCM decoder processing. This signal is output serially from
MSB in synchronization with the rising edge of BCLKB and RSYNC.

PCMRI

Receive PCM data input.
PCM is shifted on the falling edge of the BCLKB input from MSB. Normally, this pin is connected
to PCMRO.

Transmit ADPCM signal output.
After having encoded PCM with ADPCM, this signal is output from MSB in synchronization
with the rising edge of BCLKA and XSYNC. This pin is an open drain output and remains in a
high impedance state during power-down. IS requires a pull-up resistor.

Receive ADPCM signal input.
The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and
RSYNC and output from MSB.

BCLKB

Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI).
The frequency is set in the 64 kHz to 2048 kHz range.

XSYNC

8 kHz synchronous signal input for transmit PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
Be sure to input the XSYNC signal because it is also used as the imput of the timing generator.

RSYNC

8 kHz synchronous signal input for receive PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.

BCLKA

Shift clock input for the ADPCM data (IS, IR).
The frequency is set in the of 32 kHz to 2048 kHz range.

8/15

MSM7540L/7560L

¡ Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

AIN

DIN

STG

Condition

Rating

0.3 to +5

0.3 to V

+ 0.3

0.3 to V

+ 0.3

55 to +150

Unit

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

Voltage must be fixed

2.7

3.6

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

Input High Voltage

0.45

¥ V

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

Input Low Voltage

0.16

¥ V

Master Clock Frequency

MCK

0.01%

10.368

+0.01%

MHz

Bit Clock Freqency

BCKA

BCLKA

2048

kHz

BCKB

BCLKB

2048

kHz

Synchronous Signal Frequency

SYMC

XSYNC, RSYNC

8.0

kHz

Clock Duty Ratio

MCK, BCLKA, BCLKB

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

Digital Input Rise Time

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

Digital Input Fall Time

Transmit Sync Signal Setting Time

BCLKA, BCLKB to XSYNC

100

XSYNC to BCLKA, BCLKB

100

Receive Sync Signal Setting Time

BCLKA, BCLKB to RSYNC

100

RSYNC to BCLKA, BCLKB

100

Synchronous Signal Width

XSYNC, RSYNC

1 BCLK

100

PCM, ADPCM Set-up Time

100

PCM, ADPCM Hold Time

100

Digital Output Load

IS (Pull-up Resistor)

500

100

IS, PCMSO, PCMRO

Operating Temperature

+25

+75

°C

Bypass Capacitor for SG

10+0.1

´GND

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MSM7540L/7560L

¡ Semiconductor

Parameter

Input Resistance

Output Load Resistance

Output Capacitance

Symbol

INPW

LVF

LAO

LVF

LAO

Condition

PWI

Min.

1.2

Typ.

Max.

100

Unit

VFRO

Output Voltage Level

Offset Voltage

OVF

OAO

OFVF

OFAO

100

*1.300

+100

+20

VFRO,

AOUT+, AOUT

VFRO

AOUT+, AOUT

AOUT+,
AOUT

VFRO

AOUT+, AOUT (GAIN = 0 dB),

Power amp only

Power amp (0.3 to 3.4 kHz,

= 350

W + 120 nF)(See Fig.1)

= 50 k

= 350

+ 120 nF(See Fig.1)

= 1.2 k

*1.300

Open Loop Gain

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

Input High Voltage

Input Low Voltage

Output Low Voltage

Output Leakage Current

Input Capacitance

Symbol

DD1

DD2

Condition

Operating Mode,

Power Down Mode (V

= 3.0 V)

1 LSTTL, Pull-up: 500

Min.

0.45

¥ V

0.0

Typ.

0.1

0.2

Max.

0.2

0.16

¥ V

0.4

Unit

2.7 V to 3.6 V, Ta = 25°C to +70°C)

Input Leakage Current

0 V

2.0

0.5

No Signal (V

= 3.0 V)

Transmit Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Input Offset Voltage

Symbol

INX

LGX

OGX

OFGX

Condition

AIN1, AIN2

Min.

Typ.

Max.

100

*1.300

+20

Unit

GSX1, GSX2

GSX1, GSX2, R

= 20 k

PreOPAMPs

SG Output Voltage

1.4

SG Output Inpedance

SG Rise Time

700

GND

´SG 10 mF + 0.1 mF

(Rise Time to 90% of max.

level)

Receive Analog Interface Characteristics

7.7 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 1.300 V

(MSM7540L)

7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.300 V

(MSM7560L)

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MSM7540L/7560L

¡ Semiconductor

AC Chracteristics

Parameter

Transmit Frequency

Response

Symbol

OSS

Level

0 to 60

Min.

Typ.

Max.

Unit

Freq.

Others

OSS

T2 300 to 3000

0.15

+0.20

OSS

1020

Reference

OSS

3300

0.15

+0.80

OSS

3400

0.80

OSS

3968.75

Receive Frequency

Response

0 to 3000

0.15

+0.20

1020

Reference

3300

0.15

+0.80

3400

0.80

3968.75

Transmit Signal

to Distortion Ratio

SD T1

SD T2

SD T3

SD T4

1020

SD T5

Receive Signal

to Distortion Ratio

SD R1

SD R2

SD R3

SD R4

1020

SD R5

Transmit Gain

Tracking

GT T1

0.2

+0.2

GT T2

Reference

GT T3

1020

0.2

+0.2

GT T4

0.5

+0.5

GT T5

1.2

+1.2

Receive Gain

Tracking

GT R1

0.2

+0.2

GT R2

Reference

GT R3

1020

0.2

+0.2

GT R4

0.5

+0.5

GT R5

1.2

+1.2

Condition

OSS

(*1)

2.7 V to 3.6 V, Ta = 25°C to +70°C)

(dBm0)

(Hz)

*1 Use the P-message weighted filter

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MSM7540L/7560L

¡ Semiconductor

Digital Output

Delay Time

SDX

200

SDR

200

XD1

200

XD2

200

1 LSTTL + 100 pF,

Pull-up: 500

SRRT

Noise Freq.

: 0 to 50 kHz

Power Supply Noise

Rejection Ratio

Noise Level

: 50 mV

SRRR

XD3

200

Parameter

Symbol

Level

Min.

Typ.

Max.

Unit

2.7 V to 3.6 V, Ta = 25°C to +70°C)

Freq.

Others

Condition

(dBm0)

(Hz)

IDLT

(75.7)

dBm0p

(dBmp)

IDLR

1020

0.285

0.320

(*3)

0.359

0.285

0.320

(*3)

0.359

(79.7)

Idle Channel Noise

AIN = SG

(*1)

(*2)

Vrms

GSX2

Absolute Signal

Amplitude

VFRO

(*1)

AC Characteristics (Continued)

*1 Use the P-message weighted filter
*2 PCMRI input code

"11010101"(MSM7540L)
"11111111"(MSM7560L)

*3 0.320 Vrms = 0 dBm0 = 7.7 dBm

Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation

G.721.

12/15

MSM7540L/7560L

¡ Semiconductor

TIMING DIAGRAM

Transmit Side PCM/ADPCM Data Interface

Receive Side PCM/ADPCM Data Interface

MSB

LSB

txs

tsx

txd1

txd2

tsdx

txs

tsx

txd1

txd2

tsdx

txd3

MSB

LSB

txd3

BCLKB

XSYNC

PCMSO

(during linear)

BCLKA

XSYNC

tws

MSB

LSB

tsr

tds

tdh

txd3

trd3

trs

tsr

trd1

trd2

BCLKA

RSYNC

BCLKB

RSYNC

PCMRO

(during linear)

tsdx

trs

MSB

LSB

tws

Note: Linear format

A code of an input/output level is determined by the 14-bit 2'compliment.
Refer to the table below for code format.

Input/Output level

+Full-scall

Full-scall

MSB to LSB

01111111111111

00000000000000

10000000000000

13/15

MSM7540L/7560L

¡ Semiconductor

APPLICATION CIRCUIT

MSM7540L/7560L

8 kHz Sync Signal Input

Power Down Input

Receive ADPCM Input

Transmit ADPCM Output

Transmit Analog Input

Receive Analog Output

(Push-Pull)

ADPCM Algorithm
Reset Input

Shift Clock Input for
PCM, ADPCM Data
(64 kHz to 2048 kHz)

10.368 MHz

Receive
PCM Output

Transmit
PCM Output

AIN2

GSX2

GSX1

VFRO

AIN1

PWI

AOUT

RES

PCMRI

PCMRO

PCMSI

PCMSO

LPS

BCLKB

BCLKA

XSYNC

RSYNC

MCK

PDN

AOUT+

14/15

MSM7540L/7560L

¡ Semiconductor

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SOP28-P-430-1.27-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

mm or more

0.75 TYP.

Mirror finish

15/15

MSM7540L/7560L

¡ Semiconductor

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

TSOPI32-P-814-0.50-1K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5

mm or more

0.27 TYP.

Mirror finish

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM7560L

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM7560L