Semiconductor
MSM7582/7582B
1/24
Semiconductor
MSM7582/7582B
p/4 Shift QPSK MODEM
GENERAL DESCRIPTION
The MSM7582/7582B are CMOS ICs for the p/4 shift QPSK modem developed for the digital
cordless telephone systems.
The devices are designed for Personal and Cell station applications, the MSM7582B is the
improved MSM7582 in modulator burst rise-up and fall-down characteristics.
FEATURES
Single Power Supply (V
DD
: 2.7 V to 3.6 V)
(Modulator Block)
Built-in Root Nyquist Filter for Baseband Limiting (50% Roll-off)
Ramp Bit for Burst Signal Rise-up:
MSM7582/1.75 symbols
MSM7582B/2.0 symbols
Ramp Bit for Burst Signal Fall-down:
MSM7582/2.75 symbols
MSM7582B/2.0 symbols
Built-in D/A converters for Analog Output of Quadrature Signal I/Q Components and Power
Envelope Output
I
2
+ Q
2
Differential I/Q Analog output format
I/Q Output DC Offset / Gain Adjustable
(Demodulator Block)
Full Digital System, p/4 shift QPSK Demodulation
Input IF signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz
Built-in Clock Recovery: 4 Circuits useful for Cell station
(Common)
Various Power-down Modes: Tramsmit/Receive Independant
Built-in Precise Analog Voltage Reference
MCU Serial Interface for Mode setting and Built-in Test circuit
Test Modes:
Eye pattern / AFC Compensating Signal / Phase Detection Signal, possible to
monitor
Transmission Speed: 384 kbps
Low Power consumption
Operating mode : 15 mA Typ. / Modulator (V
DD
= 3.0 V)
: 9 mA Typ. / Demodulator (V
DD
= 3.0 V)
Whole system Power-down mode: 0.01 mA Typ. (V
DD
= 3.0 V)
Package:
32-pin plastic TSOP (TSOPI32-P-814-0.50-1K)(Product name : MSM7582TS-K)
(Product name : MSM7582BTS-K)
E2U0035-16-X2
This version: Jan. 1998
Previous version: Nov. 1996
Semiconductor
MSM7582/7582B
2/24
BLOCK DIAGRAM
IFIN
AGND
DGND
V
DD
Phase Detector
Delay Detector
IFCK
MCK
X1
DEN
EXCK
DIN
DOUT
S
E
L
X2
Control
Register (CR)
To each
block
PDN0
PDN1
PDN2
AFC
DPLL
Decision
Unit
RXC
RXD
S
E
L
SLS1
SLS2
+1
-1
+1
-1
+1
I+
I
Q+
Q
ENV
Root Nyquist
LPF
S
E
L
S/P
MAPPING
S
E
L
APLL
TXD
TXW
TXCI
1/10
TXCO
SG
To internal SG
To each block
IFSEL0
(From CR)
IFSEL1
(From CR)
SL4
SL3
SL2
SL1
To monitor output
of each block
To modem ENV
PS/CS
RPR
RCW
AFC
TEST1, TEST0
(From CR)
To
Monitor
output of
each block
TXCSEL
(From CR)
3.84 MHz
384 kHz
Decoder
ENV D/A CONV
VREF
I D/A CONV
Q D/A CONV
To D/A
Semiconductor
MSM7582/7582B
3/24
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AGND
SG
I+
I
Q+
Q
ENV
PDN0
PDN1
PDN2
V
DD
SLS1
SLS2
RCW
AFC
RPR
DGND
IFIN
TXCI
TXCO
TXD
TXW
DEN
EXCK
DIN
DOUT
MCK
RXD
RXC
IFCK
X2
X1
32-Pin Plastic TSOP
Semiconductor
MSM7582/7582B
4/24
PIN AND FUNCTIONAL DESCRIPTIONS
TXD
Transmit data input for 384 kbps.
TXCI
Transmit clock input.
When the control register CR0 B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because these devices use APLL to
generate the internal clock pulse.
When CR0 B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the
3.84 MHz to TXCI by 10. The transmit data, synchronous 384 kHz clock pulse, should be input
to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be
continuous. (Refer to Fig. 1.)
TXCO
Transmit clock output.
When CR0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CR0 B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)
When CR0 B6 = "0" and CR5 B7 = "1", this pin outputs the burst timing position.
TXW
Transmit data window input.
The transmit timing signal for the burst data is input to the device pin. If TXW is "1", the
modulation data is output. However, the MSM7582 is different from the MSM7582B in the ramp
response time for burst rise-up and burst fall-down of I, Q modulated outputs, as shown in the
table below. (Refer to Fig, 1-1 for the MSM7582 and Fig, 1-2 for the MSM7582B)
MSM7582
MSM7582B
Ramp Rise-up
1.75 symbols
2 symbols
Ramp Fall-down
2.75 symbols
2 symbols
The TXCO burst position output timing discribed before, is different, according to this table.
Semiconductor
MSM7582/7582B
5/24
MSM7582
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
,
Ramp rise-up
1.75 symbols
Delay of 6.25 symbols
Ramp
Fall-down
2.75 symbols
Delay of 6.25 symbols
(1) CR0 B6 = "0"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(384 kHz)
I, Q
,
Ramp rise-up
1.75 symbols
Delay of 6.25 symbols
Ramp
Fall-down
2.75 symbols
Delay of 6.25 symbols
(2) CR0 B6 = "1"
Figure 1-1 Transmit Timing Diagram
Semiconductor
MSM7582/7582B
6/24
MSM7582B
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
,
Ramp rise-up
2 symbols
Delay of 6.25 symbols
Ramp fall-down
2 symbols
Delay of 6.25 symbols
(1) CR0 B6 = "0"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(384 kHz)
I, Q
,
Ramp rise-up
2 symbols
Delay of 6.25 symbols
Ramp fall-down
2 symbols
Delay of 6.25 symbols
(2) CR0 B6 = "1"
Figure 1-2 Transmit Timing Diagram
I+, I
Quadrature modulation signal I component differential analog outputs.
Their output levels are 500 mV
pp
with 1.6 Vdc as the center value. The output pin load conditions
are: R
10 kW, C
20 pF. The gain of these pins can be adjusted using the control register CR1
B7 to B4, and the offset voltage at the I pin can be adjusted using CR3 B7 to B3.
Q+, Q
Quadrature modulation signal Q component differential analog outputs.
Their output levels are 500 mV
PP
with 1.6 Vdc as the center value. The output pin load conditions
are: R
10 kW, C
20 pF. The gain of these pins can be adjusted using the control register CR1
B3 to B0, and the offset voltage at the Q pin can be adjusted by using CR4 B7 to B3.
Semiconductor
MSM7582/7582B
7/24
ENV
Quadrature modulation signal envelope (
I
2
+ Q
2
)output.
Its output level is 500 mV
PP
with 1.6 Vdc as a center value. The output pin load conditions are
: R
10 kW, C
20 pF. The gain of this output can be adjusted using the control register CR2 B7
to B4.
This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of
the demodulator block during the test mode. Refer to the description of the control register for
details.
SG
Internal reference voltage output.
The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and
the AGND pin.
PDN0, PDN1, PDN2
Inputs for power-down control.
PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2
controls the demodulator. Refer to Table 1 for details.
Table-1 Power Down Control
PDN0
Standby
Mode
Communication
Mode
PDN2 PDN1
0
0/1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1
Function
All power-down. The control register is reset.
Modulator power is off (VREF and PLL power are also off).
Demodulator power is on.
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Only demodulator clock recovery block power is on.
Modulator power is on
Only demodulator clock recovery block power is on.
Modulator power is off (VREF and PLL power is on).
I and Q outputs are in a high-impedance state.
Demodulator power is on.
Demodulator power is on.
Modulator power is on
Mode
Mode A
Mode C
Mode D
Mode E
Mode F
Mode G
0
0
0
All power-down. The control register is not reset.
Mode B
V
DD
+3 V power supply voltage.
AGND
Analog signal ground.
DGND
Digital signal ground.
AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on
the PCB as close as possible from the device.
Semiconductor
MSM7582/7582B
8/24
MCK
Master clock input.
The clock frequency is 19.2 MHz.
IFIN
Modulated signal input for the demodulator block.
Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CR0 B4
and B3.
IFCK
Clock signal input for demodulator block IF frequencies (10.7 MHz or 10.75 MHz).
If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111
MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or
"1". (Refer to Fig. 2.)
X1, X2
Crystal oscillator connection pins.
When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins (Refer to Fig. 2.)
X1
IFCK
19.0222 MHz or 19.1111 MHz
When IFIN = 10.7 MHz or 10.75 MHz
X2
MSM7582/7582B
X1
IFCK
X2
MSM7582/7582B
When IFIN = 1.2 MHz or 10.8 MHz
Figure 2 How to Use IFCK, X1, and X2
RXD, RXC
Receive data and clock output. When power is turned on, the outputs of circuits selected by SLS1
and SLS2 appear at these pins. (Refer to Fig. 3)
RXD1
RXC
SLS2
The recovery data and clock pulse are selected
asynchronously using the SLS signals.
SLS1
Figure 3 RXD and RXC Timing Diagram
Semiconductor
MSM7582/7582B
9/24
SLS2, SLS1
Receiver slot select signal inputs.
The devices have four sets of clock recovery circuit to each channel and four AFC information
storage registers. One these circuits is selected from a combination of the signals at these pins.
(SLS2, SLS1) = (0, 0): Slot 1, (0, 1): Slot 2
(1, 0): Slot 3, (1, 1): Slot 4
RPR
High-speed phase clock control signal input for the clock recovery circuit.
If this pin is "1", the clock recovery circuit starts in the high-speed phase clock mode. When the
phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode
automatically. When this pin is "0", the circuit is always in the low-speed phase clock mode.
AFC
AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC
operation starts after a fixed number of clock cycles and after the AFC information is reset. If RPR
is set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If
AFC is "0", frequency error is not calculated, but the frequency is corrected using an error that
is held.
RCW
Clock recovery circuit operation ON/OFF control signal input. If RCW pin is "0", DPLL does not
make any phase corrections.
AFC
AFC information
is reset.
RPR
Average
number of times
AFC is low.
AFC information
is maintained.
AFC
RPR
AFC information
is maintained.
The clock recovery circuit
starts with the previous
AFC information.
"0"
(CASE1)
(CASE2)
Average number of times
AFC is high.
Average number of times
AFC is high.
Figure 4 AFC Control Timing Diagram
Semiconductor
MSM7582/7582B
10/24
DEN , EXCK, DIN, DOUT
Serial control ports for the microprocessor interface.
The MSM7582 and MSM7582B contain a 6-byte control register. An external CPU uses these pins
to read data from and write data to the control register. DEN is an enable signal input pin. EXCK
is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output
pin. Figure 5 shows an input/output timing diagram.
High Impedance
High Impedance
(a) Data Write Timing Diagram
(b) Data Read Timing Diagram
DEN
W
EXCK
DIN
A2
DOUT
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
R
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
DEN
EXCK
DIN
DOUT
,
,
Figure 5 MCU Interface Input/Output Timing Diagram
Semiconductor
MSM7582/7582B
11/24
The register map is shown below
Table-2 Control Register Map
Register
Address
A2
A1
A0
Data
R/W
B7
B6
B5
B4
B3
B2
B1
B0
CR0
CR1
CR2
CR3
CR4
CR5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
PS/CS
TXCSEL
MODOFF
IFSEL1
IFSEL0
ENVSEL
TEST1
TEST0
ENV
GAIN3
ENV
GAIN2
ENV
GAIN1
ENV
GAIN0
BSTO
ENBL
ICT6
ICT5
ICT4
LOCAL
INV1
LOCAL
INV0
CLK
SEL1
CLK
SEL0
Ich
GAIN3
Ich
GAIN2
Ich
GAIN1
Ich
GAIN0
Qch
GAIN3
Qch
GAIN2
Qch
GAIN1
Qch
GAIN0
--
--
--
--
Ich
Offset3
Ich
Offset2
Ich
Offset1
Ich
Offset0
Ich
Offset4
Qch
Offset3
Qch
Offset2
Qch
Offset1
Qch
Offset0
Qch
Offset4
--
--
--
--
--
--
R/W : Read/Write enable R : Read-only register
Semiconductor
MSM7582/7582B
12/24
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Digital Input Voltage
Operating Temperature
Storage Temperature
Symbol
V
DD
V
DIN
T
op
T
STG
Condtion
--
--
--
--
Rating
0 to 5
0.3 to V
DD
+0.3
25 to +70
55 to +150
Unit
V
V
C
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condtion
Min.
Typ.
Max.
Unit
Power Supply Voltage
V
DD
--
2.7
--
3.6
V
Input High Voltage
V
IH
--
V
DD
V
Input Low Voltage
V
IL
0
--
V
Master Clock Frequency
f
MCK
MHz
Clock Duty Cycle
D
CCK
MCK, IFCK, TXCI
40
50
60
%
IF Input Duty Cycle
D
CIF
IFCK
45
50
55
%
--
19.2
--
f
TXC2
MHz
--
3.84
--
TXCI (when CR0 B6 = "1")
MCK
0.45
V
DD
0.16
V
DD
Operating Temperature Range
Ta
--
25
--
+70
C
All digital input pins
All digital input pins
f
TXC1
kHz
--
384
--
TXCI (when CR0 B6 = "0")
Modulator Input Frequency
f
IFCK2
MHz
50 ppm
19.1111
+50 ppm
IFCK (when IFIN = 10.75 MHz)
f
IFCK1
MHz
50 ppm
19.0222
+50 ppm
IFCK (when IFIN = 10.7 MHz)
Demodulator Input Frequency
(V
DD
= 2.7 V to 3.6 V, Ta = 25C to +70C)
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Power Supply Current
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
I
DD1
I
DD2
I
IH
I
IL
Condition
Mode A, Mode B (when V
DD
= 3.0 V)
I
OH
= 0.4 mA
I
OL
= 1.2 mA
Min.
--
--
--
--
0.5
V
DD
0.0
Typ.
0.02
5.5
--
--
--
--
Max.
0.05
11.0
10
10
V
DD
0.4
Unit
mA
mA
mA
mA
V
V
(V
DD
= 2.7 V to 3.6 V, Ta = 25C to +70C)
V
OH
V
OL
I
DD3
I
DD4
Mode C (when V
DD
= 3.0 V)
Mode D (when V
DD
= 3.0 V)
--
--
5.5
11.5
11.0
23.0
mA
mA
I
DD5
I
DD6
Mode E (when V
DD
= 3.0 V)
Mode F (when V
DD
= 3.0 V)
--
--
9.5
14.0
19.0
28.0
mA
mA
--
--
Mode G (when V
DD
= 3.0 V)
Semiconductor
MSM7582/7582B
13/24
Parameter
Output Resistance Load
Output Capacitance Load
Output DC Voltage Level
Output AC Voltage Level
Symbol
R
LIQ
C
LIQ
V
DC1
V
AC
Condtion
Min.
1.0
--
1.55
--
Typ.
--
--
1.6
360
Max.
--
20
--
Unit
k
W
pF
V
mV
PP
I+, I, Q+, Q, ENV
I+, I, Q+, Q, ENV
I+, I, Q+, Q (TXW = 0)
I+, I, Q+, Q
(TXD = 0)
(V
DD
= 2.7 V to 3.6 V, Ta = 25C to +70C)
V
DC2
--
1.77
V
I+ (CR0 B5 = 1)
when not modulated
V
DC3
--
1.67
V
Q+ (CR0 B5 = 1)
when not modulated
V
DC4
--
1.35
V
ENV (TXW = 0)
V
DC5
--
1.72
V
ENV (TXW = 1, CR0 B2 = 0, TXD = 0)
V
DC6
--
1.63
V
ENV (TXW = 1, CR0 B2 = 1, TXD = 0)
Output DC Voltage Adjustment Level Range
DCVL
--
45
--
mV
--
Output AC Voltage Adjustment Level Range
ACVL
--
4
--
%
--
Out-of-band Spectrum
P600
60
--
--
dB
600 kHz detuning (*)
P900
65
--
--
dB
900 kHz detuning (*)
Modulation Accuracy
EVM
--
1.0
3.0
% rms
--
Demodulator IF Input Level
IFV
0.5
--
V
DD
V
PP
IFIN input level
IFIN Input Impedance
RIF
--
20
--
k
W
--
CIF
--
5
--
pF
--
SG Output Voltage
VSG
--
2.0
--
V
--
SG Output Impedance
RSG
--
1.5
--
k
W
--
1.65
--
--
--
--
--
Analog Interface Characteristics
* Power attenuation at 600 kHz or 900 kHz
96 kHz as referred to two times of the power in
frequency band of 0 to 96 kHz
Semiconductor
MSM7582/7582B
14/24
Digital Interface Characteristics
Transmitter Digital
Input/Output Setting Time
t
SX
200
--
200
t
DS
0
--
200
t
XD1
0
--
200
ns
t
XD3
0
--
200
Parameter
Symbol
Min.
Typ.
Max.
Unit
(V
DD
= 2.7 V to 3.6 V, Ta = 25C to +70C)
Other
Condtion
C load = 50 pF
Fig. 6
ns
ns
ns
t
DH
t
XD2
t
XD4
t
M1
50
--
--
ns
t
M2
50
--
--
ns
t
M3
50
--
--
ns
t
M4
50
--
--
ns
t
M5
100
--
--
ns
t
M6
50
--
--
ns
t
M7
50
--
--
ns
t
M8
0
--
100
ns
t
M9
50
--
--
ns
t
M10
50
--
--
ns
t
M11
0
--
50
ns
Serial Port Digital
Input/Output Setting Time
C load = 50 pF
Fig. 8
f
EXCK
--
--
10
MHz
--
EXCK
EXCK Clock Frequency
t
RD1
t
RD2
t
RS1
to
t
RW
t
RS4
Receiver Digital Input/Output
Setting Time
C load = 50 pF
Fig. 7
0
--
200
ns
0
--
200
ns
10
--
--
ms
10
--
--
ms
Semiconductor
MSM7582/7582B
15/24
TIMING DIAGRAM
1
2
3
N-2
N-1
N
N+1
t
DS
t
SX
TXCI [TXCO*]
(384 kHz)
TXW
TXD
t
DH
1
2
3
N-2
N-1
N
t
SX
TXCI
(3.84 MHz)
1
2
3
4
5
6
7
8
9
10
t
XD1
t
XD2
t
XD1
TXCO
(384 kHz)
Transmit Data Input Timing
Transmit Clock (TXCO) Output Timing
(when CR0 B6 = 1)
TXCI
(384 kHz)
1
2
8
9
N
N+1
N+17
t
XD3
TXCO
Transmit Burst Position Output (TXCO) Timing
(when CR0 B6 = 0 and CR5 B7 = 1)
TXW
N+18
N+19
t
XD4
M7582
TXCI
(384 kHz)
1
2
8
9
N
N+1
N+17
t
XD3
TXCO
TXW
N+18
N+19
t
XD4
M7582B
* [ ]: When CR0 B6 = "1", TXCO is indicated.
Figure 6 Transmit (Modulator) Digital Input/Output Timing
Semiconductor
MSM7582/7582B
16/24
RXC
AFC
RXD
t
RD1
t
RS4
t
RS3
t
RD2
RPR
t
RW
RCW
t
RS2
t
RS1
SLS1
SLS2
Figure 7 Receiver (Demodulator) Digital Input/Output Timing
t
M1
t
M3
t
M4
t
M2
1
2
3
4
5
6
t
M6
t
M7
t
M5
11
12
t
M10
t
M11
W/R
A2
A1
A0
B7
B7
t
M8
B1
B0
B1
B0
t
M4
DEN
EXCK
DIN
DOUT
Figure 8 Serial Control Port Interface
Semiconductor
MSM7582/7582B
17/24
FUNCTIONAL DESCRIPTION
Control Registers
(1) CR0 (basic operation mode setting)
B7
B6
B5
B4
B3
B2
B1
B0
PS/CS
TXC SEL
MOD OFF
IFSEL 1
IFSEL 0
ENV SEL
TEST 1
TEST 0
0
0
0
0
0
0
0
0
Initial value (*)
CR0
* the initial value is set when a reset signal is supplied by a PDN.
B7: PS/CS selection
1/CS (4 Clock recovery DPLLs are on.)
0/PS (2 Clock recovery DPLLs are on.)
B6: Transmit timing clock selection
0/TXCI input: 384 kHz.
TXCO output: 384 kHz output from APLL. Transmit data TXD is input in synchronization
with the rising edge of TXCI (APLL is on.)
1/TXCI input: 3.84 MHz.
TXCO output: 384 kHz (one-tenth of the TXCI frequency). Transmit data TXD is input in
synchronization with the rising edge of TXCO (APLL is off.)
B5: Modulation on/off control
1/modulation OFF (with phase fixed)
0/modulation ON.
B4, B3: Receiver input IF frequency selection
(0, 0), (0, 1):
1.2 MHz
(1, 0):
10.8 MHz
(1, 1):
10.7 MHz/10.75 MHz
B2: Transmit envelope (I
2
+ Q
2
or
I
2
+ Q
2
)output selection
1/I
2
+ Q
2
output
0/
I
2
+ Q
2
output
B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin.
(0, 0): Transmit envelope (I
2
+ Q
2
or
I
2
+ Q
2
) output
(0, 1): receiver phase detection signal output
(1, 0): receiver delay detection signal output
(1, 1): receiver AFC information output
Semiconductor
MSM7582/7582B
18/24
(2) CR1 (I, Q gain adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
Ich
GAIN3
Ich
GAIN2
Ich
GAIN1
Ich
GAIN0
Qch
GAIN3
Qch
GAIN2
Qch
GAIN1
Qch
GAIN0
0
0
0
0
0
0
0
0
Initial value
CR1
B7 to B4: I+/I output gain setting, in 3 mV steps (Refer to Table-3.)
B3 to B0: Q+/Q output gain setting, in 3 mV steps (Refer to Table-3.)
(3) CR2 (ENV gain adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
ENV
GAIN3
ENV
GAIN2
ENV
GAIN1
ENV
GAIN0
--
--
--
--
0
0
0
0
0
0
0
0
Initial value
CR2
B7 to B4: ENV output gain adjustment (Refer to Table-3.)
B3 to B0: Not used
Table-3 I, Q, and ENV Output Gain Values
CR1-B7
-B6 -B5 -B4
CR1-B3
-B2 -B1 -B0
CR2-B7
-B6 -B5 -B4
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
Amplitude 1.042
1.036
1.030
1.024
1.018
1.012
1.006
1.000
0.994
0.988
0.982
0.976
0.970
0.964
0.958
0.952
Reference value
(Reference value)
Description
Semiconductor
MSM7582/7582B
19/24
(4) CR3 (I output offset voltage adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
Ich
Offset4
Ich
Offset3
Ich
Offset2
Ich
Offset1
Ich
Offset0
--
--
--
0
0
0
0
0
0
0
0
Initial value
CR3
B7 to B3: I output pin offset voltage adjustment (Refer to Table-4.)
B2 to B0: Not used
(5) CR4 (Q output offset voltage adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
Qch
Offset4
Qch
Offset3
Qch
Offset2
Qch
Offset1
Qch
Offset0
--
--
--
0
0
0
0
0
0
0
0
Initial value
CR4
B7 to B4: Q output pin offset voltage adjustment (Refer to Table-4.)
B3 to B0: Not used
Table-4 I and Q Channel Offset Adjustment Values
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CR4-B7
B6
B5
B4
B3
+45
+42
+39
+36
+33
+30
+27
+24
+21
+18
+15
+12
+9
+6
+3
0
Description
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CR4-B7
B6
B5
B4
B3
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
CR3-B7
B6
B5
B4
B3
CR3-B7
B6
B5
B4
B3
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Offset
Offset
Semiconductor
MSM7582/7582B
20/24
(6) CR5
B7
B6
B5
B4
B3
B2
B1
B0
BSTO
ENBL
ICT6
ICT5
ICT4
LOCAL
INV1
LOCAL
INV0
CLK
SEL1
CLK
SEL0
0
0
0
0
0
0
0
0
Initial value
CR5
B7: Modulator burst window output enable bit.
1/The timing of the I and Q baseband modulation output burst is output at the TXCO pin.
0/The 384 kHz transmit timing clock pulse is output at the TXCO pin.
B6 to B4: ICT6 to ICT4. Device test control bits.
B3, B2: Local inverting mode setting bits.
(1, 1) = local inverting mode
(0, 0) = normal mode
B1: Clock pulse shaping mode selection bit.
1/Clock pulse shaping mode (Refer to Fig 9.)
0/Oscillator circuit mode
B0: Power-on control bit for X1, X2 pins, when the clock pulse shaping mode.
1/ Always power-on
0/ Power-down in the whole device power-down state when Power on otherwise.
Note: CR5 B6 to B4 are used to test the device. They should be set to "0" during normal
operation.
X1
MCK
X2
MSM7582/82B TS-K
TCXO
19.2 MHz
About
0.7 to 1.0 V
PP
Pulse shape
within about 3 V
PP
To other input
of 19.2 MHz
Figure 9 Example of Application Circuit when the Clock Pulse Shaping Mode is
Generated by CR5-B1
Semiconductor
MSM7582/7582B
21/24
Mode E
Mode B
Mode D
Mode G
Mode C
Mode F
PDN1 = 0
PDN2 = 0
PDN1 = 0
PDN2 = 1
PDN1 = 0
PDN2 = 1
PDN1 = 0
PDN2 = 0
PDN1 = 1
PDN2 = 1
PDN1 = 1
PDN2 = 0
1 ms
5
ms
40
ms
40
ms
5
ms
5 ms
Standby mode (PDN0 = 0)
Communication mode (PDN0 = 1)
Note: The transition time is 1
ms or
less unless otherwise stated
Mode A
PDN1 = 1
State Transition Time
Figure 10 Power-Down State Transition Time
Semiconductor
MSM7582/7582B
22/24
Figure 11 Example of Circuit Configuration
APPLICATION CIRCUIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AGND
SG
I+
I
Q+
Q
ENV
PDN0
PDN1
PDN2
V
DD
SLS1
SLS2
RCW
AFC
RPR
DGND
IFIN
TXCI
TXCO
TXD
TXW
DEN
EXCK
DIN
DOUT
MCK
RXD
RXC
IFCK
X2
X1
MSM7582TS-K
C3
C2
C1
V
DD
Modulator I component output
Power-down control signal
Demodulator control signal
Demodulator IF input
Modulator 384 kHz input
Modulator input data
Modulator data window
Receive clock output
Receive data output
19.2 MHz input
Control register
control signal
C4
C1 = 10
mF
C2 = C3 = 0.1
mF
C4 = 1000 pF
+
To orthogonal modulator
Modulator Q component output
Semiconductor
MSM7582/7582B
23/24
Demodulator Control Timing Diagram (Example)
Democulator unit
Modulator
input data
PDN2
SLS2
240 bits 625
ms
R1
G
Slot 1
R2
G
Slot 2
R3
G
Slot 3
R4
G
Slot 4
G
SLS1
"0"
"0"
"0"
"1"
"1"
"0"
"1"
"1"
AFC
R1
R2
RXD
R3
R4
RXC
Timing for CS
G G G G G G G G R R R R SS SS PR PR
UW
PR
CR
CR
G G G G G G G G
RXD
AFC
RPR
RCW
56 bits
64 bits
G G G G G G G G R R R R SS SS PR PR
UW
PR
CR
CR
G G G G G G G G
RXD
8 bits
RPR
RCW
"0"
When the strength of the received wave is small.
Less than 30 bits
AFC
G
R
SS
PR
UW
CR
:
:
:
:
:
:
Guard bit
Ramp bit
Start symbol bit
Preamble bit
Unique word bit
CRC bit
For PS, the window is initially open to
wait for the control signal from CS.
RPR is closed after UW is detected.
PDN2
SLS2
SLS1
"0"
"0"
AFC
,
R1
RXD
RXC
Timing for PS
RPR
RCW
AFC
(1) Control channel / synchronous burst (SS + PR = 64 bits)
(3) Communication channel (SS + PR = 8 bits)
When the strength of the received wave is large
(2) When synchronization is not established (for PS only)
Semiconductor
MSM7582/7582B
24/24
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
TSOPI32-P-814-0.50-1K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5
mm or more
0.27 TYP.
Mirror finish
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