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¡ Semiconductor

MSM7617

GENERAL DESCRIPTION

The MSM7617 cancels echoes (acoustic or line echoes) generated in voice channels. It is a low-
power CMOS LSI device with two channels.

MSM7617 echo canceling is performed by digital signal processing. It negates echoes by
estimating the echo channel and then generating a pseudo-echo signal.

When used as an acoustic echo canceler, the MSM7617 can cancel acoustic echoes between
speaker and microphone that occur during hands-free speaking with car phones, conferencing
system phones, etc. When used as a line echo canceler, the MSM7617 can cancel line echoes
returned by hybrid impedance mismatches.

By setting its mode for use as a single cross-connected channel, the MSM7617 can cancel both
acoustic and line echoes.

Also, the MSM7617 can improve voice communication by using its howling detection, double-
talk detection, attenuation, and gain control functions to prevent and suppress howling levels,
and by using its center clipping function to suppress low level noise.

Furthermore, the MSM7617 can disable echo canceling during data communication with its 2100
Hz tone detector and 2100 Hz phase reversal detector. It also provides the ability to attenuate SIN
levels, to amplify SOUT levels, and to adjust input/output levels.

An economical and highly efficient echo canceler unit can be constructed by using a 2-channel
single-chip CODEC like the MSM7533 together with the MSM7617.

¡ Semiconductor

MSM7617

2-Channel Echo Canceler

E2U0057-38-21

This version: Feb. 1999

Previous version: Aug. 1998

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¡ Semiconductor

MSM7617

FEATURES

·Echo canceler has two channels, which can be used for acoustic and line echoes. Set as a single

cross-connected channel, it can be used for both acoustic and line echoes.

·ITU-T G164/G165 standard tone disabler.

·PCM line level adjustment possible with SIN level attenuator (SA pin) and SOUT level

amplifier (SG pin). Can also be used for ERL amplification with the SIN level attenuator (SA
pin).

·RGC pin provides input/output adjustment mode (

6LR mode) that can prevent malfunction

due to excessive inputs without changing the RIN-ROUT input/output levels.

·Cancelable echo delay time:

55 ms (max.)

·Echo attenuation:

30 dB (typ.)

·Clock frequency:

18 to 20 MHz
19.2 MHz if using internal clock signal

·Power supply voltage:

4.5 to 5.5 V

·Package:

64-pin plastic QFP (QFP64-P-1414-0.80-BK)

·Product name:

MSM7617-001GS-BK (m-law)

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¡ Semiconductor

MSM7617

BLOCK DIAGRAM

S/P

6LR

+6LR

P/S

Non-linear/

Linear

Linear/

Non-linear

Adaptive

FIR Filter

(AFF)

P/S

S/P

Linear/

Non-linear

Non-linear/

Linear

Center

Clip

+6LR

ATT

Howling

Detector

Double Talk

Detector

Power

Calculator

6LR

ROUT1

2100 Hz Tone,

Phase Reverse

Detector

RIN1

DF1

WDT1

SIN1

SOUT1

ATT

S/P

6LR

+6LR

P/S

Non-linear/

Linear

Linear/

Non-linear

Adaptive

FIR Filter

(AFF)

P/S

S/P

Linear/

Non-linear

Non-linear/

Linear

Center

Clip

+6LR

ATT

Howling

Detector

Double Talk

Detector

Power

Calculator

6LR

ROUT2

2100 Hz Tone,

Phase Reverse

Detector

RIN2

DF2

WDT2

SIN2

SOUT2

ATT

CH1

CH2

SYNCO

SCKO

Clock Generator

(PLL)

PLL

EC-A Controller

EC-B Controller

I/O Controller

IOM0,1

SYNC2

SYNC1

SCK

GC20,21

SA20,21

SG20,21

ATT2

HD2

RST2

ADP2

HCL2

NLP2

ECM

SA10,11

SG10,11

ATT1

HD1

RST1

ADP1

HCL1

NLP1

PWDWN

CLKIN

ECDM0,1

RGC1011

The above diagram shows internal connections for 2-channel parallel mode. The internal
connections for 2-channel serial I/O mode and 1-channel cross-connected mode are shown
below.

CH1

ROUT1

RIN1

SIN1

SOUT1

RIN

ROUT

SOUT

SIN

AFF

CH2

ROUT2

RIN2

SIN2

SOUT2

RIN

ROUT

SOUT

SIN

AFF

2-channel parallel I/O mode

CH1

RIN1

SIN1

SOUT1

RIN

ROUT

SOUT

SIN

AFF

CH2

RIN

ROUT

SOUT

SIN

AFF

2-channel serial I/O mode

CH1

ROUT1

SIN1

RIN

ROUT

SOUT

SIN

AFF

CH2

ROUT2

SIN2

RIN

ROUT

SOUT

SIN

AFF

1-channel cross-connected mode

ROUT1

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¡ Semiconductor

MSM7617

PIN CONFIGURATION (TOP VIEW)

RST2

ADP2

HCL2

SYNC2

NLP2

IOM0

IOM1

SCK

ECM

NLP1

(PLL)

CLKIN

TST
PWDWN

ECDM1

ECDM0

SCKO

SYNCO

HD2

ATT2

SOUT2

SIN2

ROUT2

RIN2

SG21

SG20

SA21

SA20

HD1

ATT1

SOUT1

SIN1

ROUT1

RIN1

SG11

SG10

SA11

SA10

SYNC1

HCL1

ADP1

RST1

RGC11

RGC10

DF1

WDT1

37 V

36 V

35 V

34 V

33 V

RGC21

RGC20

DF2

WDT2

64-Pin Plastic QFP

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MSM7617

PIN DESCRIPTIONS

Pin

Symbol

Type

Description

RST2

Reset signal input pin for channel 2.

"L": Reset

"H": Normal operation

Input signals are invalid for 100 ms after reset (after RST returns to "H"

from "L") for setting initial values.

Input the basic clock during reset. Output pins will be placed in the

following states during reset.

Hi-Z: ROUT2, SOUT2

No effect: SYNCO, SCKO, ROUT1, SOUT1, DF1, WDT1

Previous state: DF2, WDT2

ADP2

AFF coefficient control pin for channel 2.

This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the

coefficients. It allows once acquired AFF coefficients to be saved.

"H": Fixed coefficient mode

"L": Normal mode (variable coefficients)

HCL2

Echo canceler disable pin for channel 2.

This pin disables the echo canceler and enables data from SIN to SOUT to be output

in "through mode". The input and output levels of SIN and SOUT are changed by the

setting of the SG and SA pins; therefore, to output data from SIN to SOUT in

"through mode", set the SA and SG pins to "0 dB".

It simultaneously clears the adaptive FIR filter coefficients.

"H": Disable mode

"L": Normal mode (echo canceller enabled)

SYNC2

Sync signal input pin for channel 2 transmit/receive PCM data while in

parallel I/O mode.

Input the transmit/receive sync signal (8 kHz) of the PCM CODEC connected

to channel 2. Input "L" if not in parallel I/O mode.

NLP2

NLP control pin for channel 2.

This pin controls center clipping, forcing SOUT2 output to the minimum

positive value when it is below 54 dBm0. It is effective for reducing

uncanceled echoes and low-level noise.

"H": Center clipping on

"L": Center clipping off

IOM0

IOM1

Sets I/O mode of PCM data.

IOM0

Mode Setting

2-channel parallel I/O mode

2-channel serial I/O mode

1-channel cross-connected mode

Inhibited

IOM1

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¡ Semiconductor

MSM7617

PIN DESCRIPTIONS (Continued)

Pin

Symbol

Type

Description

ECM

Not used. Fix input to "H".

SYNC1

Sync signal input pin for channel 1 transmit/receive PCM data while in 2-

channel parallel I/O mode, 2-channel serial I/O mode, or 1-channel cross-

connected mode.

Input the transmit/receive sync signal (8 kHz) of the PCM CODEC.

HCL1

Echo canceler disable control pin for channel 1.

This pin disables the echo canceler and enables data from SIN to SOUT to be output

in "through mode". The input and output levels of SIN and SOUT are changed by the

setting of the SG and SA pins; therefore, to output data from SIN to SOUT in "through

mode", set the SA and SG pins to "0 dB".

It simultaneously clears the adaptive FIR filter coefficients.

"H": Disable mode

"L": Normal mode (echo canceler enabled)

ADP1

AFF coefficient control pin for channel 1.

This pin stops coefficient variation of the adaptive FIR filter (AFF), fixing the

coefficients. It allows once acquired AFF coefficients to be saved.

"H": Fixed coefficient mode

"L": Normal mode (variable coefficients)

RST1

Reset signal input pin for channel 1.

"L": Reset

"H": Normal operation

Input signals are invalid for 100 ms after reset (after RST returns to "H" from

"L") for setting initial values.

Input the base clock during reset. Output pins will be placed in the following

states during reset.

Hi-Z: ROUT1, SOUT1

No effect: SYNCO, SCKO, ROUT2, SOUT2, DF2, WDT2

Previous state: DF1, WDT1

NLP1

NLP control pin for channel 1.

This pin controls center clipping, forcing SOUT1 output to the minimum

positive value when it is below 54 dBm0. It is effective for reducing

uncancelled echoes and low-level noise.

"H": Center clipping on

"L": Center clipping off

SCK

Common pin for channel 1 and channel 2. Clock input pin for PCM data

transmission.

Input the same clock as the transmit/receive clock of the PCM CODEC.

Frequencies below 128 kHz cannot be used in serial mode.

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MSM7617

Pin

Symbol

Type

Description

ATT1

ATT control pin for channel 1.

This pin controls the ATT function for preventing howling with the

attenuators (ATT) provided on RIN and SOUT. When input is only on RIN,

the SOUT attenuator is activated. When there is no input on RIN or there is

input on both SIN and RIN, the RIN input attenuator is activated. Either the

ATT for the RIN output or the ATT for the SOUT is always activated in all

cases, and the attenuation of ATT is 6 dB.

"H": Attenuator off

"L": Attenuator on

Because the attenuator is inserted opposite the speaker, it is effective for

further reducing echo.

SOUT1

PCM data output pin. Output signal changes depending on the setting of

the IOM pins (refer to the block diagram).

Data is always output on the rising edge of SCK. This pin is put in high

impedance state while there is no data or during reset.

In 2-channel parallel I/O mode, this pin becomes SOUT for channel 1 and

outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O

mode, this pin outputs the SOUT signal as a multiplexed PCM signal of

SOUT signal for channel 1 and channel 2 synchronous with SYNC1.

In 1-channel cross-connected mode, this pin becomes high impedance.

HD1

Howling detection control pin for channel 1.

This pin controls detection and canceling of howling generated by the

acoustics of handsfree telephones.

"L": Howling detector on

"H": Howling detector off

PIN DESCRIPTIONS (Continued)

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MSM7617

Pin

Symbol

Type

Description

ROUT1

PCM data output pin. Output signal changes depending on the setting of

the IOM pins (refer to the block diagram).

Data is always output on the rising edge of SCK. This pin becomes high

impedance while there is no data or during reset.

In 2-channel parallel I/O mode, this pin becomes ROUT for channel 1 and

outputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O

mode, this pin outputs the ROUT signal as a multiplexed PCM signal of ROUT

signals for channel 1 and channel 2 synchronous with SYNC1.

In 1-channel cross-connected mode, this pin becomes the cross-connected

ROUT pin for channel 1, and outputs the PCM signal synchronous with SYNC1.

RIN1

PCM data input pin. Pin use changes depending on the setting of the IOM

pins (refer to the block diagram).

In 2-channel parallel I/O mode, this pin becomes RIN for channel 1 and

inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O

mode, this pin sequentially inputs RIN as a multiplexed PCM signal from

channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-

connected mode, this pin is not used, and should be fixed at "L".

Data is captured on the falling edge of SCK.

SIN1

PCM data input pin. Pin use changes depending on the setting of the IOM

pins (refer to the block diagram).

In 2-channel parallel I/O mode, this pin becomes SIN for channel 1 and

inputs the PCM signal synchronous with SYNC1. In 2-channel serial I/O

mode, this pin sequentially inputs SIN as a multiplexed PCM signal from

channel 1 and channel 2 synchronous with SYNC1. In 1-channel cross-

connected mode, this pin becomes the cross-connected SIN pin for channel

1, and inputs the PCM signal synchronous with SYNC1.

Data is captured on the falling edge of SCK.

PIN DESCRIPTIONS (Continued)

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MSM7617

Pin

Symbol

Type

Description

RGC11

RGC10

R input level control pins for channel 1 (refer to the block diagram).

Excessive input (PCM level is at maximum value) causes a malfanction.

Use these pins when there is a possibility of excessive input.

RGC10

Level Control Mode

Off

GC: On (control level = 20 dBm0)

By the R gain controller, levels from 20 to 11.5 dBm0 will

be suppressed to 20 dBm0 and those above 11.5 dBm0 will

always be attenuated by 8.5 dB. This is effective to prevent

excessive input and howling for hands-free applications.

Inhibited

±6LR: On

Applies 6 dB to excessive inputs using the level adjuster

provided on R and S I/O. Since +6 dB also is applied at the

output, the total level will not change, making this effective

against line echo.

SG11

SG10

S output gain control pins for channel 1 (refer to the block diagram).

These pins amplify the output level of SOUT. The gain level can be set even

during the echo canceler disable mode.

SA11

SA10

S input attenuator control pins for channel 1 (refer to the block diagram).

These pins attenuate the input level of SIN. Use them if ERL is large.

The attenuation level can be set even during the echo canceler disable mode.

SG10

Gain Level

0 dB

+6 dB

+12 dB

Not used

SA10

Attenuation Level

0 dB

6 dB

12 dB

Not used

SG11

SA11

RGC11

PIN DESCRIPTIONS (Continued)

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MSM7617

Pin

Symbol

Type

Description

ECDM0

ECDM1

Tone disabler control pin common to channel 1 and channel 2.

These pins detect answer tones generated by modems (2100 Hz), and then

disable the echo canceler.

PWDWN

Common pin for channel 1 and channel 2.

This pin controls the power-down mode to reduce current consumption

when the device is not being used.

"L": Power down

"H": Normal operation

During power-down mode all input pins are invalid, and output pins will enter

the following states.

Hi-Z: SOUT1, SOUT2, ROUT1, ROUT2

"L": SYNCO, SCKO

Previous state: DF1, WDT1, DF2, WDT2

Reset the device after power-down mode is released.

Tone Disabler Mode

Off

2100 Hz tone detection: On

2100 Hz and phase reversal detection: On

Inhibited

ECDM0

DF1

Tone disabler flag output pin for channel 1.

This pin outputs a disable flag when the ECDM pins are used for tone disabler

mode.

"H": Echo canceler disabled

"L": Echo canceler enabled

SCKO

Output pin for internal SCK signal (256 kHz).

This pin is used for the transfer clock of PCM signals. Connect it to the PCM

CODEC's synchronization signal pin. Leave open if using an external SYNC.

WDT1

Not used. Leave this pin open.

SYNCO

Output pin for internal SYNC signal (8 kHz).

This pin is used as the transmit/receive synchronization signal for PCM signals.

Connect it to the SYNC pin and PCM CODEC's synchronization signal pin. Leave

this pin open if using an external SYNC.

ECDM1

PIN DESCRIPTIONS (Continued)

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MSM7617

Pin

Symbol

Type

Description

RGC20

RGC21

R input level control pins for channel 2 (refer to the block diagram).

Excessive input (PCM level is at maximum value) causes a malfunction.

Use these pins when there is a possibility of excessive input.

Level Control Mode

Off

GC: On (control level = 20 dBm0)

By the R gain controller, levels from 20 to 11.5 dBm0

will be suppressed to 20 dBm0 and those above 11.5

dBm0 will always be attenuated by 8.5 dB. This is

effective to prevent excessive input and howling for

hands-free applications.

Inhibited

±6LR: On

Apply 6 dB to excessive inputs using the level

adjuster provided on R and S I/O. Since +6 dB also

is applied at the output, the total level will not

change, making this effective against line echo.

RGC20

RGC21

(PLL)

Power supply for PLL circuit that uses the basic clock.

Insert a 0.1mF capacitor with excellent high frequency characteristics

between V

(PLL) and V

(PLL).

TST

Not used. Leave this pin open.

CLKIN

Basic clock input pin.

Input a clock 18 to 20 MHz. Use 19.2 MHz if using internal synchronization

signals (SYNCO, SCKO).

(PLL)

Ground for PLL circuit that uses the basic clock.

Insert a 0.1mF capacitor with excellent high frequency characteristics

between V

(PLL) and V

(PLL).

WDT2

Not used. Leave this pin open.

DF2

Tone disabler flag output pin for channel 2.

This pin outputs a disable flag when the ECDM pins are used for tone

disabler.

"H": Echo canceler disabled

"L": Echo canceler enabled

PIN DESCRIPTIONS (Continued)

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MSM7617

Pin

Symbol

Type

Description

RIN2

PCM data input pin. Pin use changes depending on the setting of the IOM

pins (refer to the block diagram).

In 2-channel parallel I/O mode, this pin becomes RIN for channel 2 and

inputs the PCM signal synchronous with SYNC2. Data is captured on the

falling edge of SCK. In other modes, this pin is not used, and should be

fixed at "L".

ROUT2

PCM data output pin. Output signal changes depending on the setting of

the IOM pins (refer to the block diagram).

Data is always output on the rising edge of SCK. This pin becomes high

impedance while there is no data.

In 2-channel parallel I/O mode, this pin becomes ROUT for channel 2 and

outputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O

mode, this pin is not used and should be left open. In 1-channel cross-

connected mode, this pin becomes the cross-connected ROUT pin for

channel 2, and outputs the PCM signal synchronous with SYNC1.

SA20

SA21

S input attenuator control pins for channel 2 (refer to the block diagram).

These pins attenuate the input level of SIN. Use them if ERL is large.

The attenuation level can be set even during the echo canceler disable mode.

SG20

SG21

S output gain control pins for channel 2 (refer to the block diagram).

These pins amplify the output level of SOUT. The gain level can be set even

during the echo canceler disable mode.

SG20

Attenuation Level

0 dB

6 dB

12 dB

Not used

SG20

Gain Level

0 dB

+6 dB

+12 dB

Not used

SA21

SG21

PIN DESCRIPTIONS (Continued)

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¡ Semiconductor

MSM7617

Pin

Symbol

Type

Description

ATT2

ATT control pin for channel 2.

This pin controls the ATT function for preventing howling with the

attenuators (ATT) provided on RIN and SOUT. When input is only on RIN,

the SOUT attenuator is activated. When there is no input on SIN or there is

input on both SIN and RIN, the RIN input attenuator is activated. Either the

ATT for the RIN output or the ATT for the SOUT is always activated in all

cases, and the attenuation of ATT is 6 dB.

"H": Attenuator off

"L": Attenuator on

Because the attenuator is activated opposite the speaker, it is effective for

further reducing echo.

HD2

Howling detection control pin for channel 2.

This pin controls detection and canceling of howling generated by the

acoustics of handsfree telephones.

"L": Howling detector on

"H": Howling detector off

SIN2

PCM data input pin. Pin use changes depending on the setting of the IOM

pins (refer to the block diagram). Data is captured on the falling edge of SCK.

In 2-channel parallel I/O mode, this pin becomes SIN for channel 2 and

inputs the PCM signal synchronous with SYNC2. In 2-channel serial I/O

mode, this pin is not used and should be fixed at "L". In 1-channel cross-

connected mode, this pin becomes the cross-connected SIN pin for channel

2, and inputs the PCM signal synchronous with SYNC1.

SOUT2

PCM data output pin. Output signal changes depending on the setting of

the IOM pins (refer to the block diagram).

Data is always output on the rising edge of SCK. This pin becomes high

impedance while there is no data.

In 2-channel parallel I/O mode, this pin becomes SOUT for channel 2 and

outputs the PCM signal synchronous with SYNC2. In other modes, this pin

is not used and should be left open.

PIN DESCRIPTIONS (Continued)

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MSM7617

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

High Level Input Voltage

Operating Temperature

Symbol

Condition

Unit

°C

Low Level Input Voltage

Min.

2.4

4.5

Typ.

+25

Max.

+85

0.8

5.5

= 4.5 V to 5.5 V)

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

High Level Output Leakage Current

Symbol

OZH

Condition

= V

Unit

µA

Low Level Input Current

µA

= V

= 1.6 mA

= 40 µA

Min.

4.2

Typ.

0.1

Max.

0.4

= 4.5 V to 5.5 V, Ta = 40°C to +85°C)

Low Level Output Leakage Current

Power Supply Current (operation mode)

Power Supply Current (power-down mode)

Output Load Capacitance

OZL

DDO

DDS

LOAD

µA

Input Capacitance

PWDWN = "L"

= V

0.1

130

0.5

Parameter

Power Supply Voltage

Input Voltage

Power Dissipation

Storage Temperature

Symbol

STG

Condition

Ta = 25°C

Rating

0.3 to + 7

0.3 to V

+ 0.3

55 to +150

Unit

°C

15/28

¡ Semiconductor

MSM7617

Echo Canceler Characteristics (refer to characteristics diagram)

Parameter

Echo Reduction

(Common to Channel 1 and

Channel 2)

Symbol

RES

Condition

Unit

= 10 dBm0

(5 kHz white noise band)

E. R. L. = 6 dB

= 50 ms

ATT, GC, NLP: OFF

Min.

Typ.

Max.

Cancelable Echo Delay Time

(Common to Channel 1 and

Channel 2)

= 10 dBm0

(5 kHz white noise band)

E. R. L. = 6 dB

ATT, GC, NLP: OFF

Tone Disabler Characteristics

Parameter

Tone Detection

Phase Reversal Detection

Detection frequency

Detection level

Detection time

Detection frequency

Unit

dBm0

Detection condition

Min.

2075

380

2075

Typ.

2100

Max.

2125

2100Hz. 180° out-of-phase detected before and after 450±25ms.

2125

Release

Detection level

Phase reversal

Detection level

dBm0

135

180

225

Release time

250

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¡ Semiconductor

MSM7617

AC Characteristics

Parameter

Clock Frequency

If Used Without Internal Sync Signal

Clock Cycle Time

Clock Duty Cycle

Symbol

MCK

DMC

Unit

MHz

If Used Without Internal Sync Signal

Min.

Typ.

52.08

19.2

Max.

55.56

= 4.5 V to 5.5 V, Ta = 40°C to +85°C)

Clock High Level Pulse Width

Clock Low Level Pulse Width

Clock Rise Time

Internal Sync Clock Output Time

MCH

MCL

DCM

Clock Fall Time

MCK

¥ 0.4

MCK

¥ 0.6

Internal Sync Clock Frequency

kHz

256

Internal Sync Clock Cycle Time

µs

3.9

Internal Sync Clock Duty Cycle

DCO

Internal Sync Signal Output Time

DCC

Internal Sync Signal Period

CYO

µs

125

Internal Sync Signal Pulse Width

WSO

µs

Transmit/Receive Sync Clock Frequency

SCK

kHz

2048

In Serial I/O Mode

128

2048

Transmit/Receive Sync Clock Cycle Time

In Serial I/O Mode

Transmit/Receive Sync Clock Duty Cycle

DSC

Transmit/Receive Sync Signal Period

CYC

µs

125

Sync Timing

Receive Signal Setup Time

Receive Signal Hold Time

WSY

µs

SCK

CYC

SCK

Receive Signal Input Time

In 2-Channel Serial Mode

MCK

¥ 0.4

MCK

¥ 0.6

SCK

µs

0.488

15.62

0.488

7.81

µs

SCK

Sync Signal Width

ID2

µs

15t

SCK

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¡ Semiconductor

MSM7617

Parameter

Serial Output Delay Time

Reset Signal Input Width

Symbol

Unit

µs

Min.

Typ.

Max.

= 4.5 V to 5.5 V, Ta = 40°C to +85°C)

Reset Start Time

Reset End Time

Power-Down Start Time

DRS

DRE

DIT

DPE

µs

Process Operation Start Time

DPS

111

Power-Down End Time

WPR

RST Width After Power-Down

DSR

RST Control Pin Setup Time

DHR

RST Control Pin Hold Time

DCS

120

SCK Control Pin Setup Time

DCH

120

SCK Control Pin Hold Time

100

AC Characteristics (Continued)

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MSM7617

Serial Data Output Timing (Parallel Mode, FTF Mode)

SCK

SYNC

SOUT

ROUT

MSB

CYC

SCK

, t

SCK

WSY

LSB

MSB

DSC

High-Z

Serial Data Output Timing (Serial Mode)

Note: Refer to parallel mode for detailed timing

SCK

SYNC1

ROUT1

SOUT1

CYC

SCK

, t

SCK

WSY

CH1 data

CH2 data

High-Z

Operation Timing After Reset

DRS

RST

DRE

Internal operation

Proccessing starts

DIT

Reset

Initial setting

Note: Reset timing can be asynchronous.

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MSM7617

Power-Down Timing

Note: All inputs are invalid during power-down. Always reset the device after power-down.

DPS

DPE

WPR

Internal operation

Power-down

PWDWN

RST

Capture Timing of Control Pins

Control pin states are captured during reset and during each period's serial data capture.

RST

Control Pin

DSR

DHR

Channel 1 Control Pin

Channel 2 Control Pin

(when not in serial mode)

Channel 2 Control Pin (when in serial mode)

ID2

DCS

DCH

DCS

DCH

SCK

SYNC

22/28

¡ Semiconductor

MSM7617

HOW TO USE THE MSM7617

The echo canceler cancels the echo on the RIN signal as returned by SIN. Connect the original
signal to the R side, and the signal generating the echo to the S side.

Connection Methods According to Echoes

Example 1. Cancel Acoustic Echo (applies to acoustic echo from line input)

AFF

ROUT

SIN

RIN

SOUT

CODEC

Input

Acoustic echo

Example 2. Cancel Line Echo (applies to line echo from microphone input)

AFF

SOUT

RIN

SIN

ROUT

CODEC

Line echo

Input

Example 3. Cancel Both Acoustic Echo And Line Echo

SIN2

ROUT2

CODEC

Input

Acoustic echo

AFF

ROUT1

SIN1

MSM7617

AFF

Input

CH1

Line echo

CODEC

CH2

23/28

¡ Semiconductor

MSM7617

ECHO CANCELER CHARACTERISTICS DIAGRAM

Characteristics of m-law and A-law are identical. (Characteristic graphs below are reference
data.)

ERL vs. Echo Attenuation

Echo Attenuation [dB]

E. R. L. [dB]

Measuring Conditions:
RIN input level = 10 dBm0 white noise
Echo delay time = 50 ms
ATT, GC, NLP, LR all off

RIN Input Level vs. Echo Attenuation

Echo Attenuation [dB]

RIN Input level [dBm0]

Measuring Conditions:
RIN input = white noise
Echo delay time = 50 ms
E.R.L. = 6 [dB]
ATT, GC, NLP, LR all off

Echo Delay Time vs. Echo Attenuation

Echo Attenuation [dB]

Measuring Conditions:
RIN input level = 10 dBm0 white noise
Echo delay time = 50 ms
E.R.L = 6 dB
ATT, GC, NLP, LR all off

50 40 30 20 10

Echo Delay Time [ms]

Note: regarding dBm0:

The "dBm0" unit used in the characteristic graphs is a unit that expresses PCM CODEC digital
values. Therefore, be aware that the same value 0 [dBm0] might correspond to different analog
input levels depending on the PCM CODEC being used. Please check the data sheet of the PCM
CODEC being used.

Example

MSM7533

0 [dBm0] = 0.85 [Vrms] = 2.4 [Vp-p] = 0.8 [dBm] 600 W

10 [dBm0] = 0.27 [Vrms] = 0.76 [Vp-p] = 9.2 [dBm] 600 W

MSM7543

0 [dBm0] = 0.6007 [Vrms] = 1.7 [Vp-p] = 2.2 [dBm] 600 W

10 [dBm0] = 0.19 [Vrms] = 0.54 [Vp-p] = 12.2 [dBm] 600 W

25/28

¡ Semiconductor

MSM7617

NOTES ON USE

1. Set echo return loss (E. R. L) to be attenuated. If the echo return loss is set to be amplified, the

echo cannot be canceled. (Refer to the "E. R. L vs Echo Attenuation" characteristic graph.)

When the echo return loss is amplified, adjust the input level to be attenuated by setting the
mode with the SA pin. If the level from the SA pin is too low by setting the mode with the SA
pin, then amplify the output level by setting the mode with the SG pin.

2. Set RIN input so that there is not excessive input (above 0 dBm0) from the PCM CODEC. Echo

cancellation is not possible with excessive input. (Refer to the "RIN vs Echo Attenuation"
characteristic graph.)

Recommended input levels are 10 to 20 dBm0. If there is a possibility of excessive input,
then set GC mode or 6LR mode with the RGC pins.

3. Applying the tone signals to this echo canceler will decrease echo attenuation.

4. For changes in the echo path (retransmit, circuit switching during transmission, and so on),

convergence may be difficult.
Perform a reset to make it converge.
If the state of the echo path changes after a reset, convergence may again be difficult.
In cases such as a change in the echo path, perform a reset each time.

5. If a clock is not input after power is applied, then the internal circuits will not stabilize,

possibly damaging the device.

When power is applied, set the PWDWN pin to "H" and input the basic clock.

If the device is put into PWDWN immediately after power has been applied, be sure to input
10 or more clocks of the basic clock before setting to the power down mode.

6. Always reset after power is applied or power-down is released.

For power-on reset operation, an external oscillator may require a certain setting time after
powered on. Allow 10 ms for a reset time after the oscillator has settled.

7. When the device is used as an acoustic echo canceler, equipment noise and environment noise

from the microphone amp may be amplified, and echo attenuation may be below 30 dB.

26/28

¡ Semiconductor

MSM7617

APPLICATION CIRCUITS

4-Channel Serial Interface

Line Echo Canceler Example

MSM7617

RIN1

ROUT1

SOUT1

SIN1

RIN2

ROUT2

SOUT2

SIN2

SYNC1

SYNC2

SCK

WDT1

WDT2

DF1

DF2

NLP1

NLP2

HCL1

HCL2

ADP1

ADP2

HD1

HD2

ATT1

ATT2

SG11

SG21

SG10

SG20

SA11

SA21

SA10

SA20

RGC11

RGC21

RGC10

RGC20

RST1

RST2

ECDM1

IOM1

ECDM0

IOM0

TST

ECM

CLKIN

SYNCO

PWDWN

SCKO

(PLL)

ch1 SYNC

+5 V
GND

GND

CLOCK

GND

+5 V

GND

CH1

CH2

ch1 RST

MSM7617

RIN1

ROUT1

SOUT1

SIN1

RIN2

ROUT2

SOUT2

SIN2

SYNC1

SYNC2

SCK

WDT1

WDT2

DF1

DF2

NLP1

NLP2

HCL1

HCL2

ADP1

ADP2

HD1

HD2

ATT1

ATT2

SG11

SG21

SG10

SG20

SA11

SA21

SA10

SA20

RGC11

RGC21

RGC10

RGC20

RST1

RST2

ECDM1

IOM1

ECDM0

IOM0

TST

ECM

CLKIN

SYNCO

PWDWN

SCKO

(PLL)

+5 V
GND

GND

+5 V

GND

CH3

CH4

ch2 RST
ch3 RST
ch4 RST

SCK

ch3 SYNC

SOUT Bus

RIN Bus

SIN Bus

ROUT Bus

Terminal side

Line side

27/28

¡ Semiconductor

MSM7617

Cross-Connection Example

Microphone Input

Speaker Output

Line Input

Line Output

24
23
2

8
1

(AG)

21
22

12
15
10
16
19

5
6

AIN1
GSX1
AOUT1

DOUT1
DIN1
XSYNC
RSYNC

BCLK
A/m
PDN
CHP

AIN2

GSX2

AOUT2

DOUT2

DIN2

SGC

2ch CODEC

MSM7533VGS-K

MSM7617

31
11

43
46

RST

PWDWN

CLK

RIN1

SOUT1

RIN2

SOUT2

SYNC1

SCK

WDT1

DF1

NLP1
HCL1

ADP1

HD1

ATT1

SG11

SG10

SA11

SA10

RGC11

RGC10
RST1
ECDM1

ECDM0

TST

CLKIN
PWDWN

(PLL)

ROUT1

SIN1

ROUT2

SIN2

SYNC2

WDT2

DF2

NLP2
HCL2

ADP2

HD2

ATT2

SG21

SG20

SA20

RGC21

RGC20

RST2

IOM1

IOM0

ECM

SYNC0

SCK0

R1 = 20 kW

R2 = 20 kW

R3 = 2.2 kW

R4 = 10 kW

R5 = 20 kW

R6 = 20 kW

R7 = 2.2 kW

R8 = 10 kW

C1 = 1 mF

C2 = 1 mF

C3 = 0.1 mF

C4 = 10 mF

C5 = 0.1 mF

C6 = 0.1 mF

C7 = 0.1 mF

C8 = 10 mF

SA21

28/28

¡ Semiconductor

MSM7617

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

QFP64-P-1414-0.80-BK

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.

Mirror finish

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

E2Y0002-29-11

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