¡ Semiconductor

MSM7620

1/28

¡ Semiconductor

MSM7620

Echo Canceler

GENERAL DESCRIPTION

The MSM7620 is an improved version of the MSM7520 with the same basic configuration. The
MSM7620 includes following improvements: a modified through mode, timing control of the
control pin input, and a thinner package. The MSM7620 also provides a pin-for-pin replacement
with the MSM7520.
The MSM7620 is a low-power CMOS IC device for canceling echo (in an acoustic system or
telephone line) generated in a speech path.
Echo is canceled (in digital signal processing) by estimating the echo path and generating a
pseudo-echo signal.
Used as an acoustic echo canceler, the MSM7620 cancels the acoustic echo between the loud
speaker and the microphone which occurs during hands free communication, such as on a car
phone or a conference system phone.
Used as a line echo canceler, the device cancels the line echo impedance mismatching in a hybrid.
In addition, a quality conversation is made possible by controlling the level and preventing
howling with a howling detector, double talk detector, attenuation function and a gain control
function, and by controlling the low level noise with a center clipping function.
The MSM7620 I/O interface supports m-law PCM. The use of a single chip CODEC, such as the
MSM7543, allows the configuration an economic and efficient echo canceler to be configured.

Note: If the object is to cancel line echo, the use of the MSM7602 is recommended, for the
MSM7602 is provided with a howling detect control pin. In addition, the MSM7602, while having
characteristics equivalent to the MSM7620, is packaged small.

FEATURES

· Handles both acoustic echoes and telephone line echoes.
· Cancelable echo delay time:

MSM7620-001 ................. For a single chip: 23 ms (max.)
MSM7620-011 ................. For a cascade connection (can also be used for a single chip)

Master chip: 23 ms (max.)
Slave chip: 31 ms (max.)
Cancelable up to 213 ms (one master plus six slaves)
For a single chip: 23 ms (max.)

· Echo attenuation

: 30 dB (typ.)

· Clock frequency

: 18 MHz (36 MHz cannot be used)

External input and internal oscillator circuit are provided.

· Power supply voltage : 5 V (4.5 V to 5.5 V)
· Power consumption

: 150 mW (typ.) When powered down: 20 mW (typ.)

· Package options:

32-pin plastic SSOP (SSOP32-P-640-0.80-K) (Product name : MSM7620-001GS-K)
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name : MSM7620-011GS-BK)

E2U0038-28-81

This version: Aug. 1998

Previous version: Nov. 1996

¡ Semiconductor

MSM7620

2/28

BLOCK DIAGRAM

MSM7620-001 (Single chip only)

RIN

P/S

Non-linear/
Linear

Linear/
Non-linear

S/P

ATT

Howling
Detector

Double Talk
Detector

Power
Calculator

Adaptive

FIR Filter

(AFF)

S/P

Linear/
Non-linear

Non-linear/
Linear

P/S

Center
Clip

Clock Generator

Mode Selector

I/O Controller

Gain

ATT

ROUT

SOUT

RST

PWDWN

SYNC

X1/CLKIN

X2 SCKO

SYNCO NLP

HCL ADP

ATT GC

IRLD INT SCK

SIN

WDT

MSM7620-011 (Cascade connection or Single chip)

RIN

P/S

Non-Linear
/Linear

Linear/
Non-linear

S/P

ATT

Howling
Detector

Double Talk
Detector

Power
Calculator

S/P

Linear/
Non-linear

Non-linear/
Linear

P/S

Center
Clip

Clock Generator

Mode Selector

I/O Controller

Gain

ATT

ROUT

SOUT

RST

PWDWN

SYNC

X1/CLKIN

* If the MSM7620-011 is used in the slave mode, only the diagonally hatched blocks and
the pins marked with * are used.

X2 SCKO

SYNCO NLP

HCL

ADP

ATT GC

IRLD INT

SCK

SIN

WDT

PD15 *

PD 0 *

OF1 *

OF2 *
SF1 *

SF2 *

Parallel

I/O Port

Parallel

I/O

Controller

Adaptive

FIR Filter

(AFF)

¡ Semiconductor

MSM7620

3/28

PIN CONFIGURATION (TOP VIEW)

32-Pin Plastic SSOP

*: No connect pin

Pin

Symbol

Pin

Symbol

Pin

Symbol

NLP

HCL

ADP

ATT

INT

IRLD

SIN

RIN

SCK

SYNC

SOUT

ROUT

X1/CLKIN

PWDWN

SYNCO

SCKO

RST

WDT

Note:

Pin 26 of the MSM7520 is CKSEL, while that of the MSM7620 is in open state.
It is possible to replace the MSM7520 with the MSM7620.

¡ Semiconductor

MSM7620

4/28

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64-Pin Plastic SSOP

Note:

Pins 43, 53, and 61 of the MSM7520 are CKSEL, V

, and TST2 respectively. While these

pins of the MSM7620 are in open state, it is possible to replace the MSM7520 with the
MSM7620.

*: No connect pin

Pin

Symbol

Pin

Symbol

Pin

Symbol

NLP

PD12

HCL

PD13

ADP

PD0

X1/CLKIN

PD14

PD1

PD15

ATT

PD2

INT

PD3

PWDWN

SF2

PD4

OF1

IRLD

PD5

SYNCO

PD6

SCKO

SIN

PD7

RIN

PD8

SF1

SCK

PD9

RST

OF2

SYNC

PD10

WDT

SOUT

PD11

ROUT

¡ Semiconductor

MSM7620

5/28

PIN DESCRIPTIONS

(1/5)

Pin

32-pin

SSOP

64-pin

QFP

Symbol

Type

Description

NLP

The control pin for the center clipping function. This forces the SOUT

output to a minimum value (FF) when the SOUT signal is below -54

dBm0. Effective for reducing low-level noise.

· Single Chip or Master Chip in a Cascade Connection

"H": Center clip ON

"L": Center clip OFF

· Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of

the

INT signal or the rising edge of the RST signal.

The through mode control.

When this pin is in the through mode, RIN and SIN data are output to

ROUT and SOUT. At the same time, the coefficient of the adaptive FIR

filter is cleared.

· Single Chip or Master Chip in a Cascade Connection

"H": Through mode

"L": Normal mode (echo canceler operates)

· Slave Chip in a Cascade Connection

Same as master

This input signal is loaded in synchronization with the falling edge of

the

INT signal or the rising edge of the RST signal.

AFF coefficient control pin. This pin stops updating of the adaptive FIR

filter (AFF) coefficient and sets the coefficient to a fixed value, when this

pin is configured to be the coefficient fix mode.

This pin is used when holding the AFF coefficient which has been once

converged.

· Single Chip or Master Chip in a Cascade Connection

"H": Coefficient fix mode

"L": Normal mode (coefficient update)

· Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of

the

INT signal or the rising edge of the RST signal.

Selection of the Master Chip and slave chip when used in a cascade

connection.

"L": Single chip or master chip

"H": Slave chip

HCL

ADP

¡ Semiconductor

MSM7620

6/28

(2/5)

Control for the ATT function that prevents howling by attenuators (ATT)

for the RIN input and SOUT output.

If there is input only to RIN, then the ATT for the SOUT output is

activated.

If there is no input to SIN, or if there is input to both SIN and RIN, the

ATT for the RIN input is activated.

Either the ATT for the RIN output or the ATT for the SOUT is always

activated in all cases, and the attenuation of ATT is 6 dB.

· Single Chip or Master Chip in a Cascade Connection

"H": ATT OFF

"L": ATT ON

"L" is recommended for echo cancellation.

· Slave Chip in a Cascade Connection

· Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the

INT signal or the rising edge of the RST signal.

Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.

Signal processing starts when H-to-L transition is detected.

· Single Chip or Master Chip in a Cascade Connection

Connect the

IRLD pin.

· Slave Chip in a Cascade Connection

Connect the

IRLD pin of the master chip.

INT input is invalid for 100 ms after reset due to initialization. Refer to
the control pin connection example.

Load detection signal when the SIN and RIN serial input data is loaded

in the internal registers.

· Single Chip

Connect to the

INT pin.

· Master Chip in a Cascade Connection

Connect to the

INT pin of the master chip and all the slave

chips.

· Slave Chip in a Cascade Connection

Leave open.

Refer to the control pin connection example.

Transmit serial data.

Input the m-law PCM signal synchronized to SYNC and SCK. Data is

read in at the fall of SCK.

Description

Symbol

Type

Pin

32-pin

SSOP

64-pin

QFP

ATT

INT

IRLD

SIN

¡ Semiconductor

MSM7620

7/28

(3/5)

Receive serial data.

Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK.

Pin

32-pin

SSOP

64-pin

QFP

Symbol

Type

Description

Clock pin for transmit/receive serial data. This pin uses the external

SCK or the SCKO.

Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).

Sync signal for transmit/receive serial data. This pin uses the external

SYNC or SYNCO.

Input the PCM CODEC transmit/receive sync signal (8 kHz).

Transmit serial data.

This pin outputs the m-law PCM signal synchronized to SYNC and SCK.

This pin is in a high impedance state while there is no data output.

Receive serial data.

This pin outputs the m-law PCM signal synchronized to SYNC and SCK.

This pin is in a high impedance state while there is no data output.

Bidirectional bus for parallel data transfer between the Master Chip and

Slave Chip when used in a cascade connection.

The PD15 pin corresponds to MSB.

This pin is in a high impedance state while there is no data output. Data

is loaded in at the falling edge of

SFx.

Power-down mode control.

"L": Power-down mode

"H": Normal operation mode

During power-down, all input pins are disabled and output pins are in

the following sates :

High impedance : SOUT, ROUT, PD0 to 15

"L": SYNCO, SCKO

"H":

OF1, OF2

Holds the last state : WDT,

IRLD

Not affected: X2, MCKO

Reset after power-down is released.

Crystal oscilator.

Used to configure the oscillation circuit.

Refer to the internal clock generator circuit example.

When inputting the basic clock externally, insert a 5 pF capacitor with

excellent high frequency characteristics between X2 and GND.

External input for the basic clock or for the crystal oscillator.

Input the basic clock (18 MHz).

Refer to the internal clock generator circuit example.

RIN

SCK

SYNC

SOUT

ROUT

I/O

PD0

PD11

PD12

PD13

PD14

PD15

X1/CLKIN

PWDWN

¡ Semiconductor

MSM7620

8/28

(4/5)

Input signal for the gain controller when RIN input is controlled and the

RIN input level is controlled and howling is prevented.

The gain controller adjusts the RIN input level when it is 20 dBm0 or

above. RIN input levels from 20 to 11.5 dBm0 will be suppressed to

20 dBm0 in the attenuation range from 0 to 8.5 dB.

RIN input levels above 11.5 dBm0 will always be attenuated by 8.5 dB.

· Single Chip or Master Chip in a Cascade Connection

"H": Gain control ON

"L": Gain control OFF

"H" is recommended for echo cancellation.

· Slave Chip in a Cascade Connection

Fixed at "L"

This pin is loaded in synchronization with the falling edge of the

INT

signal or the rising edge of

RST.

Reset signal.

"L": Reset mode

"H": Normal operation mode

During initialization, input signals, except for

PWDWN are disabled for

100 ms after reset (after

RST is returned from "L" to "H").

Input the basic clock during the reset.

Output pins during reset are in the following sates :

High impedance: SOUT, ROUT, PD0 to 15

"L": WDT

"H":

OF1, OF2

Not affected: X2, SYNCO, SCKO,

IRLD, MCKO

Transmit clock signal (200 kHz) for the PCM CODEC.

Connect this pin to the SCK pin and the PCM CODEC transmit/receive

clock pin.

Not affected by reset. Outputs "0" during power-down.

Leave it open if using an external SCK.

8 kHz sync signal for the PCM CODEC.

Connect this pin to the SYNC pin and the PCM CODEC transmit/receive

sync pin.

Leave it open if using an external SYNC.

Test pin.

Leave this pin open.

Description

Symbol

Type

SYNCO

SCKO

RST

WDT

Pin

32-pin

SSOP

64-pin

QFP

¡ Semiconductor

MSM7620

9/28

(5/5)

Description

Symbol

Type

Parallel data transfer flag.

· Single Chip

Fixed at "H"

· Master Chip in a Cascade Connection

Fixed at "H"

· Slave Chip in a Cascade Connection

Connect

OF2 of the master chip to the first stage slave chip.

Connect

OF1 of the previous stage slave chip to the second and

later stage slave chips.

Refer to the control pin connection example.

Parallel data transfer flag.

· Single Chip

Leave this pin open.

· Master Chip in a Cascade Connection

Connect to the

SF1 of all slaves.

· Slave chip in a Cascade Connection

Connect to the

SF2 of the next stage slave chip.

Connect the last stage slave chip to the

SF1 of the master chip.

Refer to the control pin connection example.

Parallel data transfer flag.

· Single Chip

Connect

OF2.

· Master Chip in a Cascade Connection

Connect

OF1 of the last stage slave chip.

· Slave Chip in a Cascade Connection

Connect

OF1 of master chip for all slave chips.

Refer to the control pin connection example.

Parallel data output flag.

· Single Chip

Connect to

SF1.

· Master Chip in a Cascade Connection

Connect to

SF2 of the first stage slave chip.

· Slave Chip in a Cascade Connection

Leave open.

Refer to the control pin connection example.

OF2

SF1

OF1

SF2

32-pin

SSOP

64-pin

QFP

Pin

¡ Semiconductor

MSM7620

10/28

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Input Voltage

Power Dissipation

Storage Temperature

Symbol

STG

Condition

Ta = 25°C

Rating

0.3 to +7

0.3 to V

+ 0.3

55 to +150

Unit

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Operating Temperature

Symbol

Condition

Pins other than X1

Min.

4.5

2.4

Unit

°C

Typ.

+25

Max.

5.5

0.8

+85

X1 pin

3.5

ELECTRICAL CHARACTERISTICS

DC Characteristics

(Ta = 40°C to +85°C)

Min.

Typ.

Max.

Unit

Condition

Symbol

Parameter

4.2

0.4

100

0.1

100

+10

0.1

Output High Voltage

Output Low Voltage

High Level Input Current

Low Level Input Current

High Level Output Current

Low Level Output Current

Power Supply Current

(Operating)

Power Supply Current(Stand-by)

PWDWN="L"

Input Capacitance

Output Load Capacitance

OZH

OZL

DDO

DDS

LOAD

When oscillation circuit is

used as basic clock

to V

Input other than

the above

PD15 to PD0

with pull-up

= V

to V

Input other than

the above

SF1, SF2
with pull-up

= 40 mA

= 1.6 mA

= V

When extarnal input is used

as basic clock

¡ Semiconductor

MSM7620

11/28

Echo Canceler Characteristics (Refer to Characteristics Diagram)

= 10 dBm0

(5 kHz band white noise)

E. R. L. (echo return loss)

= 6 dB

= 20 ms

ATT, GC, NLP: OFF

= 10 dBm0

(5 kHz band white noise)

E.R.L. = 6 dB

ATT, GC, NLP: OFF

Cancelable Echo Delay Time for a

Slave Chip in a Cascade

Cancelable Echo Delay Time for a

Single Chip or a Master Chip in a

Cascade

Echo Attenuation

Parameter

Symbol

Condition

RES

Min.

Typ.

Max.

Unit

¡ Semiconductor

MSM7620

12/28

AC Characteristics

(Ta = 40°C to +85°C)

Parameter

Clock Frequency

Clock Cycle Time

Clock Duty Ratio

Clock "H" Level Pulse Width

Clock "L" Level Pulse Width

Clock Rise Time

Clock Fall Time

Sync Clock Output Time

Internal Sync Clock Frequency

Internal Sync Clock Output Cycle Time

Internal Sync Clock Duty Ratio

Internal Sync Signal Output Delay Time

Internal Sync Signal Period

Internal Sync Signal Output Width

Transmit/receive Operation Clock Frequency

Transmit/receive Sync Clock Cycle Time

Transmit/receive Sync Clock Duty Ratio

Transmit/receive Sync Signal Period

Sync Timing

Sync Signal Width

Receive Signal Setup Time

Receive Data Input Time

IRLD Signal Output Delay Time

IRLD Signal Output Width

Serial Output Delay Time

= 18 MHz

Symbol

Condition

MCK

DMC

MCH

MCL

DCM

DCO

DCC

CYO

WSO

SCK

DSC

CYC

WSY

DIC

WIR

Min.

17.5

54.1

23.5

0.488

123

SCK

Typ.

18.0

55.56

200

125

SCK

Max.

18.5

57.1

100

2048

15.6

CYC

SCK

138

Unit

MHz

kHz

= 18 MHz

Receive Data Hold Time

¡ Semiconductor

MSM7620

13/28

AC Characteristics (Continued)

(Ta = 40°C to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

DRS

DRE

DIT

100

DPS

111

DPE

DTS

DTH

120

DSR

DHR

WPD

MCK

WFO

MCK

WFI

OFz connected to SFx

WFO

Reset Signal Input Width

Reset Start Time

Reset End Time

Processing Operation Start Time

Power Down Start Time

Power Down End Time

Control Pin Setup Time (

INT)

Control Pin Hold Time (

INT)

Control Pin Setup Time (

RST)

Control Pin Hold Time (

RST)

Parallel Data Output Signal Width

Flag Signal Output Time

Flag Signal Output Width

Flag Signal Input Width

Data Read Setup Time

Data Read Hold Time

¡ Semiconductor

MSM7620

15/28

Serial Output Timing

SCK

SYNC

SOUT

ROUT

MSB

CYC

fsck. t

SCK

WSY

DSC

LSB

High-Z

Operation Timing After Reset

RST

Internal operation

DRS

*Reset timing can be asynchronous

Processing Start

DIT

Reset

Initialization

DRE

Note:

INT is invalid in the diagonally shaded interval.

Power Down Timing

PWDWN

Internal Operation

DPS

Processing Start

Power Down

DPE

*Input MCK in the t

DPS

interval.

¡ Semiconductor

MSM7620

17/28

HOW TO USE THE MSM7620

The MSM7620 cancels the echo which returns to SIN using the RIN signal.
Connect the base signal to the R-side and the echo generated signal to the S-side.

Connection Methods According to Echos

Example 1:

Canceling acoustic echo (to handle acoustic echo from line input)

Acoustic echo

CODEC

MSM7620

CODEC

m-law

ROUT

RIN

SIN

SOUT

Line input

AFF

Example 2:

Canceling line echo (to handle line echo from microphone input)

Example 3:

Canceling line echo in a cascade connection
(to handle line echo from microphone input)

CODEC

MSM7620

CODEC

m-law

ROUT

RIN

SIN

SOUT

Line echo

AFF

Microphone Input

CODEC

MSM7620

CODEC

m-law

ROUT

RIN

SIN

SOUT

Line echo

AFF

Microphone input

Master

AFF

Slave

PD0 - 15

¡ Semiconductor

MSM7620

19/28

Control Pin Connection Example

Single Chip Connection

NLP

HCL

ADP

ATT

PWDWN

RST

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1 *
SF2 *

MS *

PD 0

IRLD

OF1

OF2

PD15

+5 V

Asterisk * mark indicates a pin only for the MSM7620-011.

NLP

HCL

ADP

ATT

PWDWN

RST

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

+5 V

Master chip

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

Slave chip

+5 V

Four-stage Cascade Connection
Master + (slave ¥ 3)

NLP

HCL

ADP

ATT

PWDWN

RST

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

+5 V

Master chip

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

Slave chip 1

+5 V

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

Slave chip 2

+5 V

NLP

HCL

ADP

ATT

PWDWN
RST
INT
SF1
SF2

PD 0

IRLD

OF1
OF2

PD15

Slave chip 3

+5 V

Two-stage Cascade Connection
Master + (slave ¥ 1)

¡ Semiconductor

MSM7620

21/28

ECHO CANCELER CHARACTERISTICS DIAGRAM

ERL vs. echo attenuation

Echo attenuation [dB]

ERL. [dB]

Measurement Conditions
RIN input = 10 dBm 5 kHz band white noise
(0 dBm = 2.2 dBm0)
Echo delay time T

= 20 ms

ATT, GC, NLP = OFF

50 40 30 20 10

RIN input level vs. echo attenuation

Echo attenuation [dB]

RIN input level [dBm]

0 dBm = 2.2 dBm0

Measurement Conditions
RIN input: 5 kHz band white noise
Echo delay time T

= 20 ms

ERL = 6 dB
ATT, GC, NLP = OFF

Echo delay time vs. echo attenuation

Echo attenuation [dB]

Echo delay time [ms]

200

150

100

Measurement Conditions
RIN input = 10 dBm
5 kHz band white noise
(0 dBm = 2.2 dBm0)

7chip

ERL = 6 dB
ATT, GC, NLP = OFF
The second through seventh chips
are connected in a cascade.

¡ Semiconductor

MSM7620

23/28

APPLICATION CIRCUIT

Bidirectional Connection Example

SOUT

RIN

NLP

HCL

ADP

ATT

SIN

ROUT

SCK

SYNC

INT
IRLD

PWDWN
RST

WDT

MSM7543GS-VK

PCMOUT

PCMIN

AIN+

VFRO

GSX

SGC

SIN

AIN

BCLOCK

RSYNC

PDN

TMC

ROUT

CLK

EXT.

SCK

EXT.

SYNC

RST

PWDWN

Mike input

Speaker output

XSYNC

SYNCO

SCKO

+ +

SOUT

RIN

NLP

HCL

ADP

ATT

MSM7620-001GS-K

R12

SIN

ROUT

SCK

SYNC

INT

IRLD

PWDWN

RST

WDT

SYNCO

SCKO

PCMOUT

PCMIN

BCLOCK

RSYNC

PDN

TMC

XSYNC

AIN+

VFRO

GSX

SGC

AIN

MSM7543GS-VK

R10

R11

RIN

SOUT

Circuit input

Circuit output

R8 > 20 kW

R9 > 20 kW

R10 = 2.2 kW

R11 = 10 kW

R12 = 10 kW

R13 = 0-22 W

R14 = 0-22 W

C6 = 10 mF

C7 = 0.1 mF

C8 = 10 mF

C9 = 1.0 mF

C10 = 1.0 mF

R1 > 50 kW

R2 > 20 kW

R3 > 20 kW

R4 = 2.2 kW

R5 = 10 kW

R6 = 10 kW

R7 > 50 kW

C1 = 0.1 mF

C2 = 10 mF

C3 = 0.1 mF

C4 = 10 mF

C5 = 0.1 mF

For cancellation of line echo

32-Pin SSOP

For cancellation of acoustic echo

32-Pin SSOP

MSM7620-001GS-K

3
5

AOUT

PWI

3
5

AOUT
PWI

C10

R13

R14

¡ Semiconductor

MSM7620

24/28

Cascade Connection Example

SIN

ROUT

SCK

SYNC

RST

PWDWN

NLP

HCL

ADP

ATT

SCKO

SYNCO

SOUT

RIN

PD15

PD14

PD13

PD12

PD11

PD10

PD 9

PD 8

PD 7

PD 6

PD 5

PD 4

PD 3

PD 2

PD 1

PD 0

OF2

SF2

OF1

SF1

INT

IRLD

WDT

SIN

ROUT

SCK

SYNC

RST

PWDWN

NLP

HCL

ADP

ATT

SCKO

SYNCO

SOUT

RIN

PD15

PD14

PD13

PD12

PD11

PD10

PD 9

PD 8

PD 7

PD 6

PD 5

PD 4

PD 3

PD 2

PD 1

PD 0

OF2

SF2

OF1

SF1

INT

IRLD

WDT

PCMOUT

PCMIN

BCLOCK

RSYNC

XSYNC

PDM

TMC

PCMOUT

PCMIN

BCLOCK

RSYNC

XSYNC

PDM

TMC

AIN +

MSM7543GS-VK

Master

Slave

SIN

ROUT

64-Pin QFP

RST

PWDWN

RIN

SOUT

R7 > 20 k

R8 > 20 k

R9 = 2.2 k

R10 = 10 k

R11 = 0-22

R12 = 0-22

C6 = 10

C7 = 0.1

C8 = 10

C9 = 1.0

C10 = 1.0

R1 > 50 k

R2 > 20 k

R3 > 20 k

R4 = 2.2 k

R5 = 10 k

R6 > 50 k

C1 = 0.1

C2 = 10

C3 = 0.1

C4 = 10

C5 = 0.1

R10

MSM7620-011GS-BK

CLK

VFRO

GSX

AIN

SGC

AOUT

PWI

AIN +

VFRO

GSX

AIN

SGC

AOUT

PWI

C10

R12

¡ Semiconductor

MSM7620

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NOTES ON USE

1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be

amplified, the echo can not be eliminated.
Refer to the characteristics diagram for ERL vs. echo attenuation quantity.

2. Set the level of the analog input so that the PCM CODEC does not overflow.

3. The recommended input level is 10 to 20 dBm0. Refer to the characteristics

diagram for the RIN input level vs. echo attenuation quantity.

4. Applying the tone signal to this echo canceler will decrease echo attenuation. If the

tone signal is input to the SIN pin during the time that a signal is input to the RIN
pin, this echo cancceler operates faultily.
A signal must be input to either the RIN pin or the SIN pin. The ADP or HCL pin
must be driven at "H" if the tone signal is input to the SIN pin during the time that
a signal is input to the RIN pin.

5. For changes in the echo path (retransmit, circuit switching during transmission, and

so on), convergence may be difficult.
Perform a reset to make it converge.
If the state of the echo path changes after a reset, convergence may again be difficult.
In cases such as a change in the echo path, perform a reset when possible.

6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock

simultaneouly with power ON.
If powering down immediately after power ON, be sure first input 10 or more clocks
of the basic clock.

7. After powering ON, be sure to reset.

8. After the power down pin is changed to a "1" from a "0", be sure to reset.

9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less

than 30 dB.

¡ Semiconductor

MSM7620

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EXPLANATION OF TERMS

Attenuating Function :

This function prevents howling and controls the noise level with an
attenuator for the RIN input and SOUT output. Refer to the
explanation of pins (ATT pin).

Echo Attenuation :

If there is talking (input only to RIN) in the path of a rising echo
arises, the echo attenuation refers to the difference in the echo
return loss (canceled amount) when the echo canceler is not used
and when it is used.
Echo attenuation = (SOUT level during through mode operation)
(SOUT level during echo canceler operation) [dB]

Echo Delay Time :

This is the time from when the signal is output from ROUT until it
returns to SIN as an echo or other similar device.

Acoustic Echo :

When using a hands free phone, and so on, the signal output from
the speaker echoes and is input again to the microphone. The
return signal is referred to as acoustic echo.

Telephone Line Echo :

This is a signal which is delayed midway in a telephone line and
returns as an echo, due to reasons such as a hybrid impedance
mismatch.

Gain Control Function :

This function prevents howling and controls the sound level by
with a gain controller for the RIN input. Refer to the explanation
of pins (GC pin).

Center Clipping Function : This function forces the SOUT output to a minimum value when

the signal is below 57 dBm0. Refer to the explanation of pins (NLP
pin).

Double Talk Detection :

Double talk refers to a state in which the SIN and RIN signals are
input simultaneously. In a double talk state, a signal outside the
echo signal which is to be canceled can be input to the SIN input,
resulting in misoperation.
The double talk detector prevents such misoperations of the canceler.

Howling Detection :

This is the oscillating state caused by the acoustic coupling between
the loud speaker and the microphone during hands free talking.
Howling not only interferes with talking, but can also cause
misoperation of the echo canceler.
The howling detector prevents such misoperation and prevents
howling.

Echo Return Loss (ERL) :

When the signal output from ROUT returns to SIN as an echo, ERL
refers to how much loss there is in the signal level during ROUT.
ERL = (ROUT level) (SIN level of the ROUT signal which returns
as an echo) [dB]
If ERL is positive (ROUT > SIN), the system is an attenuator system.
If ERL is negative (ROUT < SIN), the system is an amplifier system.

¡ Semiconductor

MSM7620

27/28

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more
0.83 TYP.

SSOP32-P-640-0.80-K

Mirror finish

¡ Semiconductor

MSM7620

28/28

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

QFP64-P-1414-0.80-BK

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more
0.87 TYP.

Mirror finish

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