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Semiconductor
MSM7704-01/02/03
2ch Single Rail CODEC
GENERAL DESCRIPTION
The MSM7704-01/7704-02/7704-03 are two-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a
reduced number of external components.
The MSM7704-01/7704-02/7704-03 are best suited for an analog interface to an echo canceller
DSP used in digital telephone terminals, digital PABXs, and hands free terminals.
FEATURES
Single power supply: +2.7 V to +3.8 V
Power consumption
Operating mode:
30 mW Typ.
50 mW Max.
Power-saving mode:
3 mW Typ.
6 mW Max.
Power-down mode:
0.03 mW Typ.
0.3 mW Max.
ITU-T Companding law
MSM7704-01:
m/A-law pin-selectable
MSM7704-02:
m-law
MSM7704-03:
A-law
Built-in PLL eliminates a master clock
The PCM interface can be switched between 2 channel serial/parallel
Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
(During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)
Adjustable transmit gain
Built-in reference voltage supply
Analog output can directly drive a 1.2 kW load
Package:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7704-01GS-K)
(Product name : MSM7704-02GS-K)
(Product name : MSM7704-03GS-K)
E2U0021-28-81
This version: Aug. 1998
Previous version: Nov. 1996
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BLOCK DIAGRAM
AIN1
GSX1
AIN2
GSX2
AOUT1
AOUT2
SGC
XSYNC
DOUT1
DOUT2
BCLK
RSYNC
(ALAW)
CHPS
DIN1
DIN2
PDN
V
DD
AG
DG
+
RC
LPF
8th
BPF
RC
LPF
8th
BPF
5th
LPF
S&H
5th
LPF
S&H
SG
GEN
VR
GEN
AD
CONV.
TCONT
AUTO
ZERO
DA
CONV.
PLL
RTIM
RCONT
PWD
Logic
+
+
+
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PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SGC
AOUT2
NC
PDN
CHPS
V
DD
DG
RSYNC
AIN2
GSX2
GSX1
AIN1
BCLK
XSYNC
NC : No connect pin
DIN2
DIN1
DOUT2
DOUT1
AOUT1
NC
AG
NC
NC
(ALAW)*
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7704-01GS-K.
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PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2
AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amps. GSX1 and GSX2 are connected to the
outputs of the op-amps and are used to adjust the level, as shown below.
When AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power
saving mode and power down mode, the GSX1 and GSX2 outputs are in high impedance state.
AOUT1, AOUT2
AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2.
The output signal has an amplitude of 2.0 V
PP
above and below the signal ground voltage (SG
: 1/2 V
DD
). When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load
of 1.2 kW or more.
During power saving mode, or power down mode, these outputs are at the voltage level of SG
with a high impedance.
V
DD
Power supply for +3 V.
A power supply for an analog circuit in the system to which the device is applied should be used.
A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor
of 10 mF to 20 mF should be connected between this pin and the AG pin if needed.
CH1
Analog Input
+
CH2
Analog Input
AIN1
C1
R1
R2
GSX1
AIN2
C2
R3
R4
GSX2
CH1 Gain
Gain = R2/R1 10
R1: Variable
R2 > 20 kW
C1 > 1/(2 3.14 30 R1)
+
CH2 Gain
Gain = R4/R3 10
R3: Variable
R4 > 20 kW
C2 > 1/(2 3.14 30 R3)
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DIN1
PCM signal input for channel 1 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT1 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).
DIN2
PCM signal input for channel 2 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT2 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.
BCLK
Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
RSYNC
Receive synchronizing signal input.
Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins
by the receive synchronizing signal.
All timing signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same clock source as
BCLK). The frequency should be 8 kHz
50 ppm to guarantee the AC characteristics which are
mainly the frequency characteristics of the receive section.
However, unless the frequency characteristics of the system used are strictly specified, this
device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in
the data sheet are not guaranteed.
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