¡ Semiconductor

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¡ Semiconductor

MSM7717-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.

FEATURES

· Single power supply: 2.7 V to 3.8 V
· Low power consumption

Operating mode:

20 mW Typ. V

= 3 V

Power-down mode:

0.03 mW Typ. V

= 3 V

· Conforms to ITU-T Companding law

MSM7717-01:

m/A-law pin selectable

MSM7717-02:

m-law

MSM7717-03:

A-law

· Built-in PLL eliminates a master clock
· Serial data rate: 64/128/256/512/1024 kHz

96/192/384/768/1536/1544/2048/200 kHz

· Adjustable transmit gain
· Adjustable receive gain
· Built-in reference voltage supply
· Package options:

24-pin plastic SOP (SOP24-P-430-1.27-K)

(Product name: MSM7717-01GS-K)
(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)

(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)

E2U0041-28-81

This version: Aug. 1998

Previous version: Nov. 1996

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PIN CONFIGURATION (TOP VIEW)

AOUT+

AOUT

PWI

VFRO

PDN

SGC

AIN+

AIN

GSX

BCLK

NC : No connect pin

RSYNC

PCMIN

XSYNC

PCMOUT

AOUT+

AOUT

PWI

VFRO

PDN

SGC

AIN+

AIN

GSX

NC : No connect pin

RSYNC

PCMIN

XSYNC

PCMOUT

BCLK

(ALAW)*

20-Pin Plastic SSOP

24-Pin Plastic SOP

* The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.

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PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed in any method shown below. When not using AIN
and AIN+, connect AIN to GSX and AIN+ to SG. During power-saving and power-down
modes, the GSX output is at AG voltage.

Analog signal ground.

VFRO

Receive filter output.
The output signal has an amplitude of 2.0 V

above and below the signal ground voltage (SG)

when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving mode this output is in a high impedance state, and during power-down
mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.

AIN
AIN+

Analog input

1) Inverting input type

R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)

Gain = R2/R1 < 10

GSX

AIN+
AIN

2) Noninverting input type

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F)

Gain = 1 + R4 / R3 £ 10

GSX

Analog input

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PWI, AOUT+, AOUT

PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT. When the PWI pin is not used, the PWI pin to
the AOUT pin, and leave the pins AOUT and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT pins. AOUT+ and AOUT outputs are in a high impedance state during
the power-down mode.

Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)

PCMIN

PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.

R6 > 20 kW

Gain = VO/VI = R7/R6 £ 1

VFRO

PWI

AOUT

AOUT+

Analog output

Analog inverted output

ZL > 1.2 kW

External Signal Input

Receive filter

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RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz

50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz

2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
operates in the range of 8 kHz

2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7717-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

Full scale

PCMIN/PCMOUT

MSM7717-02 (

m-law)

MSD

MSM7717-03 (A-law)

MSD

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Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is

200 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when
this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the
pin is internally pulled down.

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Unit

Max.

Typ.

Min.

Condition

Symbol

Parameter

3.8

3.0

2.7

Voltage must be fixed

Power Supply Voltage

°C

+85

+25

Operating Temperature

1.4

Connect AIN and GSX

AIN

Analog Input Voltage

0.45¥V

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

High Level Input Voltage

0.16¥V

Low Level Input Voltage

64, 128, 256, 512, 1024,

2048, 96, 192, 384, 768,

1536, 1544, 200

BCLK

Clock Frequency

kHz

8.0

6.0

XSYNC, RSYNC

Sync Pulse Frequency

BCLK

Clock Duty Ratio

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

100

BCLKÆXSYNC, See Fig. 1

100

XSYNCÆBCLK, See Fig. 1

Receive Sync Pulse Setting Time

100

BCLKÆRSYNC, See Fig. 1

100

RSYNCÆBCLK, See Fig. 1

1 BCLK

XSYNC, RSYNC, See Fig. 1

WSH

High Level Sync Pulse Width

1 BCLK

XSYNC, RSYNC, See Fig. 1

WSL

Low Level Sync Pulse Width

100

See Timing Diagram

PCMIN Setup Time

100

See Timing Diagram

PCMIN Hold Time

0.5

Pull-up resistor

100

Digital Output Load

+100

100

Transmit gain stage, Gain = 1

off

+10

Transmit gain stage, Gain = 10

Analog Input Allowable DC Offset

1000

XSYNC, RSYNC, BCLK

Allowable Jitter Width

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

AIN

DIN

STG

Condition

Rating

0.3 to +7

0.3 to VDD + 0.3
0.3 to VDD + 0.3

55 to +150

Unit

°C

¡ Semiconductor

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ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

High Level Input Voltage

Low Level Input Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Symbol

DD1

DD3

DD2

Condition

Operating mode

Power-saving mode, PDN = 1,

BCLK or XSYNC Æ OFF

Power-down mode, PDN = 0,

BCLK OFF

Pull-up resistor > 500 W

Min.

0.45¥V

0.0

Typ.

2.0

0.005

0.2

Max.

8.0

0.05

0.16¥V

2.0

0.5

0.4

Unit

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

No signal

6.5

10.0

= 3.8 V

= 3.0 V

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

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Transmit Analog Interface Characteristics

Receive Analog Interface Characteristics

Input Resistance

Output Load Resistance

Output Load Capacitance

INPW

LVF

LAO

LVF

LAO

PWI

0.6

VFRO with respect to SG

Output Amplitude

Offset Voltage

OVF

OAO

OSVF

OSAO

1.0

100

+1.0

+100

VFRO, R

= 20 kW with

respect to SG

AOUT+, AOUT (each) with

respect to SG

VFRO

AOUT+, AOUT

AOUT+, AOUT, R

= 0.6 kW

with respect to SG

VFRO with respect to SG

AOUT+, AOUT, Gain = 1 with

respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

INX

LGX

OGX

OSGX

AIN+, AIN

Gain = 1

0.7

+0.7

+20

GSX with respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

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AC Characteristics

Condition

= 8 kHz, V

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Transmit Frequency Response

Loss T1

Level

(dBm0)

Freq.

(Hz)

Loss T2

300

0.15

+0.07

+0.2

Loss T3

1020

Reference

Loss T4

2020

0.15

0.01

+0.2

Loss T5

3000

0.15

+0.15

+0.2

Loss T6

3400

0.4

0.8

Receive Frequency Response

Loss R1

300

0.15

0.03

+0.2

Loss R2

1020

Reference

Loss R3

2020

0.15

0.02

+0.2

Loss R4

3000

0.15

+0.15

+0.25

Loss R5

3400

0.56

0.8

SD T1

SD T2

SD T3

Transmit Signal to Distortion Ratio

1020

SD T4

SD T5

SD R1

SD R2

SD R3

Receive Signal to Distortion Ratio

1020

SD R4

33.5

SD R5

Transmit Gain Tracking

GT T1

0.3

+0.01

+0.3

GT T2

Reference

GT T3

1020

0.3

+0.3

GT T4

0.6

0.03

+0.6

GT T5

1.2

+0.15

+1.2

Receive Gain Tracking

GT R1

0.3

0.06

+0.3

GT R2

Reference

GT R3

1020

0.3

0.02

+0.3

GT R4

0.6

0.02

+0.6

GT R5

1.2

0.27

+1.2

*1 Psophometric filter is used.
*2 Upper columns are specified for the m-law, lower for the A-law.

¡ Semiconductor

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AC Characteristics (Continued)

Absolute Level (Initial Difference)

Nidle T

72.5

70.5

dBm0p

Nidle R

76.5

AV T

0.338

0.35

0.362

AV R

0.483

0.5

0.518

Vrms

1020

Absolute Delay

AV Tt

0.2

+0.2

AV Rt

0.2

+0.2

1020

0.6

A to A

BCLK

= 64 kHz

Transmit Group Delay

0.19

0.75

0.11

0.35

0.02

0.125

0.05

0.125

0.07

0.75

Receive Group Delay

0.00

0.75

0.00

0.125

0.09

0.125

0.12

0.75

Idle Channel Noise

AIN = SG

*1 *3

= 3.0 V

Ta = 25°C

= 2.7 V

to 3.8 V

Ta = 30

to 85°C

Absolute Level

(Deviation of Temperature and Power)

500

600

1000

2600

2800

Crosstalk Attenuation

CR T

CR R

1020

TRANS Æ RECV

RECV Æ TRANS

500

600

1000

2600

2800

0.35

Condition

= 8 kHz, V

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

*1 Psophometric filter is used.
*2 Upper column is specified for the m-law, lower for the A-law.
*3 Input "0" code to PCMIN.
*4 AVR is defined at VFRO output.
*5 With respect to minimum value of the group delay distortion

¡ Semiconductor

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AC Characteristics (Continued)

*6 Measured under idle channel noise.

DIS

4.6 kHz to

Digital Output Delay Time

200

XD1

200

XD2

200

XD3

200

Discrimination

0 to

4000 Hz

= 100 pF + 1 LSTTL

300 to

37.5

dBm0

Out-of-band Spurious

4.6 kHz to

IMD

fa = 470

dBm0

Intermodulation Distortion

2fa fd

PSR T

0 to

Power Supply Noise Rejection Ratio

50 mV

PSR R

72 kHz

3400

fd = 320

50 kHz

100 kHz

Condition

= 8 kHz, V

= 2.7 V to 3.8 V, Ta = 30°C to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

¡ Semiconductor

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TIMING DIAGRAM

PCM Data Input/Output Timing

BCLK

XSYNC

PCMOUT

MSD

WSL

WSH

XD1

XD2

XD3

BCLK

RSYNC

PCMIN

MSD

Transmit Timing

Receive Timing

When t

£ 1/2 · Fc, the Delay of the MSD bit is defined as t

XD1

When t

£ 1/2 · Fc, the Delay of the MSD bit is defined as t

WSL

WSH

Figure 1 Basic Timing

¡ Semiconductor

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APPLICATION CIRCUIT

These output signals have amplitudes above and below the offset level of V

/2.

FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT

AIN

Transmit frequency
characteristic
Adjustment determined by
C1, C2, R1 and R2

Receive frequency
characteristic
Adjustment determined by
C3, C4, R3 and R4

GSX

AIN+

AOUT+

AOUT

PWI

VFRO

Microphone amp

MSM7717-XX

PCMOUT

XSYNC

AIN

GSX

AIN+

1 mF

0.1 mF

PCM signal output

8 kHz SYNC signal input

PCM shift clock input

PCM data

Control of companding law
1: A-law
0: m-law

0.1 mF

51 kW

Analog input

AOUT+

RSYNC

BCLK

PCMIN

ALAW

AOUT

PWI

VFRO

SGC

0 V

+3 V

Analog inverted output*

51 kW

10 mF

MSM7717-01

PDN

0 to 10 W

Analog output*

+3 V

Power down control input
1: Normal operation
0: Power down

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NOTES ON USE

· To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

· Connect the AG pin and the DG pin as close as possible. Connect to the system ground with

low impedance.

· Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the

use of IC socket is unavoidable, use the short lead type socket.

· When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave

sources such as power supply transformers surround the device.

· Keep the voltage on the V

pin not lower than 0.3 V even instantaneously to avoid latch-

up that may otherwise occur when power is turned on.

· Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

¡ Semiconductor

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(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SOP24-P-430-1.27-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.

Mirror finish

¡ Semiconductor

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(Unit : mm)

Notes for Mounting the Surface Mount Type Package

SSOP20-P-250-0.95-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.

Mirror finish

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