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MSM9000B-xx

¡ Semiconductor

MSM9000B-xx

DOT MATRIX LCD CONTROLLER

GENERAL DESCRIPTION

The MSM9000B-xx is a dot-matrix LCD control driver which has functions of displaying 12 (5
x 7 dots) characters (2 lines) and 120-dot arbitrators.
The MSM9000B-xx is provided with a 16-dot common driver, 60-dot segment driver, Display
Data RAM (DDRAM), and Character Generator ROM (CGROM).
This device can be controlled with commands entered through the serial interface or parallel
interface.
The font data in the CGROM can be changed by mask option.
Since the MSM9000B-xx has an LCD driving bias generator circuit, LCD bias voltages can be
obtained by merely providing a required capacitance externally.
The MSM9000B-xx is applicable to a variety of LCD panels by controlling the contrast.

FEATURES

· Logic voltage(V

): 2.5 to 3.3 V

· LCD driving voltage(V

) : 3.0 to 5.5 V

· Low current consumption: 35 mA max.(operating)
· Switchable between 8-bit serial interface and 8-bit parallel interface
· Contains a 16-dot common driver and a 60-dot segment driver
· Contains CGROM with character fonts of (5 x 7 dots) x 256
· Built-in bias voltage generator circuit
· Built-in contrast adjusting circuit
· Built-in 32.768 kHz crystal oscillator circuit
· Provided with 120 dot arbitrators
· 1/9 duty mode (1 line : characters, 2 lines : arbitrators)

1/16 duty mode (2 lines : characters, 2 lines : arbitrators)

· Character blink operation can be switched between all-character lighting-on mode and all-

character lighting-off mode.

· Package:

TCP mounting with 35 mm wide film ; Tin-plated (Product name : MSM9000B-xx AV-Z-xx)
Chip

(Product name : MSM9000B-xx)
xx indicates code number.

E2B0041-27-Y3

This version: Nov. 1997

Previous version: Mar. 1996

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MSM9000B-xx

BLOCK DIAGRAM

Segment Driver

Latch

Common

Driver

Shift Register

Regulator

Halver & Voltage

Multiplier(4-fold)

Display Data RAM

(DDRAM) (456 Bits)

Character Generator

ROM (CGROM)

(256 ¥ 5 ¥ 7 Dots)

F/F

Gate

Registers

I/O Interface

Crystal OSC

Circuit

Timing

Circuit

S1-S60

C1-C16

P/S CS C/D SHT SO SI WR RD DB7-0

TEST

RESET

9D/16D

32K/EXT

CC1

SS6

CC2

SS5

SS4

SS2, 3

SS1

LCD bias

Voltage Multiplier

(3/2-fold)

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MSM9000B-xx

PIN DESCRIPTIONS

Function

Type

Description

CPU Interface

Chip select input signal

Write enable signal, latch for serial interface

Read enable signal

Command/Data select input signal

I/O

8-bit parallel data inputs/outputs

Serial data input

Serial data output

Shift clock input for data input in serial interface mode

Oscillation

Crystal oscillation input, clock input

Crystal oscillation output

Control Signal

Parallel/Serial interface switching signal input

Duty select signal input

Clock select signal input

Reset is performed by setting the RESET input to "L"

level

Contrast control signal input

Test signal input. Fix to "L" Level or leave open

LCD Driving

Output

Segment outputs for LCD driving

Common outputs for LCD driving

Power Supply

Positive + power supply pin for LOGIC

GND pin

Boosted voltage output pins & bias power supply pins

Voltage multiplier output pin (3-/2-fold)

Haver output pin

Voltage multiplier (3-/2-fold)

Voltage multiplier (4-fold)

Symbol

C/D

DB0-7

SHT

XT
XT

P/S

9D/16D

32K/EXT

RESET

N1, N2

TEST

SEG1-SEG60

COM1-COM16

SS1

, V

SS2

SS4

, V

SS5

SS6

, V

CC1

, V

CC2

Number

of Pins

112

Total

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MSM9000B-xx

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Power supply voltage

Ta=25°C, V

SS5

0.3 to +4.6

Bias voltage

0.3 to +7

Input voltage

0.3 to V

+ 0.3

Storage temperature

Chip

55 to +150

STG

°C

Ta=25°C

Ta=25°C, V

Applicable pin

, V

SS5

All input pins

, V

TCP

30 to +85

Ta: Ambient temperature

RECOMMENDED OPERATING CONDITIONS

*1 V

is the highest pin and V

SS5

the lowest for the bias voltage.

*2 Connect the specified capacitors to the voltage doubler and LCD bias generator.
*3 Make sure that the crystal oscillation frequency or the divided clock frequency falls within

this range.

Note 1: Ensure the chip is not exposed to any light.
Note 2: The bias voltage may exceed 5.5 V at some contrast stages. Adjust the stage with

software so that the bias voltage does not exceed 5.5 V.

Parameter

Symbol

Condition

Range

Unit

Power supply voltage

*1, V

SS5

2.5 to 3.3

Bias voltage

3 to 5.5

IC source oscillation

int

26 to 47

Operating temperature

30 to +85

°C

kHz

Applicable pin

DD,

SS5

, V

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MSM9000B-xx

ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

*1 No output load
Note : The values in this table are assured when the chip is not exposed to light.

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Input high voltage 1

IH1

0.25

Input low voltage 1

IL1

0.55

IH1

IH2

IL1

=0 V

/0 V

=500 mA

= 2.5 to 3.3 V, V

= 3 to 5.5 V, Ta = 30 to +85°C)

Input high current 1

Input high current 2

Off leakage current

Drain current 1

off

0.9V

Input low current 1

Output high voltage 1

During operation *1

Crystal oscillation

f = 32.768 kHz

During operation *1

External clock

f = 32 kHz

DD1

DD2

Applicable pin

Input pins other

than XT and TEST

TEST (pull-down

resistor)

SO and DB0 to

DB7

Input pins other

than XT and TEST

SO and DB0 to

DB7

Input high voltage 2

IH2

0.8V

Other inputs

Input low voltage 2

IL2

0.2V

Other input pins

=500 mA

OL1

0.1V

Output low voltage 1

SO and DB0 to

DB7

=±50 mA

COM output resistance

COM1 to COM16

=±20 mA

SEG output resistance

SEG1 to SEG60

During standby

DD3

Drain current 3

Drain current 2

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MSM9000B-xx

DC Characteristics (2)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Bias voltage 1

SS1

SS2, 3

= "A"V

1/2A0.1

1/2A

1/2A+0.1

SS5

SS2, 3

= "A"V

2A0.2

2A+0.2

con

for each stage

0.18

0.21

0.26

=0 V, V

=3 V, Ta=30 to +85°C)

Bias voltage 5

Contrast pitch

Applicable pin

SS1

SS5

Bias voltages 2 and 3

SS2, 3

N1 = "L", N2 = "L"

Contrast = "5"

1.9

2.2

2.5

SS2, 3

Bias voltage 4

SS4

SS2, 3

= "A"V

3/2A0.1

3/2A

3/2A+0.1

SS4

Note 1: Connect a 0.1

F capacitor to the LCD bias generator.

Note 2: The values in this table are assured when the chip is not exposed to light.

AC Characteristics

Parallel interface

Note: The values in this table are assured when the chip is not exposed to light.

Parameter

Symbol

Condition

Min.

RD high-level width

WRH

RD low-level width

WRL

200

WR high-level width

WWH

WR low-level width

WWL

200

Max.

Unit

WR-RD high-level width

WWRH

200

CS or C/D setup time

CS or C/D hold time

Write data setup time

DSW

Write data hold time

DHW

Read data output delay time

=50 pF

DDR

200

Read data hold time

DHR

External clock high-level width

WCH

External clock low-level width

WCL

RESET pulse width

WRE

2.0

Rise and fall time of external

clock

, t

100

=2.5 to 3.3 V, V

=3 to 5.5 V, Ta=30 to +85°C)

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MSM9000B-xx

Serial interface

Note: The values in this table are assured when the chip is not exposed to light.

Parameter

Symbol

Condition

Min.

CS or C/D setup time

SAS

CS or C/D hold time

SAH

SI setup time

SI hold time

100

Max.

Unit

SHT high-level pulse width

WSHH

100

SHT low-level pulse width

WSHL

100

SHT clock cycle time

SYS

400

SO ON delay time

= 50 pF

200

SO output delay time

= 50 pF

200

SO OFF delay time

OFF

100

BUSY delay time

= 50 pF

BUSY

200

WR setup time

SHS

200

WR low-level pulse width

WWL

120

RESET pulse width

WRE

2.0

Rise and fall time of external

clock

, t

100

= 2.5 to 3.3 V, V

= 3 to 5.5 V, Ta = 30 to +85°C)

¡ Semiconductor

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MSM9000B-xx

FUNCTIONAL DESCRIPTION

Pin Functional Description

· CS (Chip Select)

Chip select input pin. A logic low on the CS input selects the chip and a logic high on the CS
input does not select the chip. Command and display data inputs can be enabled only when
the chip is selected.
When the input is high, the SO pin and DB0 to DB7 pins are in the high impedance state,
causing SHT, WR and RD pins high level internally.

· WR (Write Enable)

When the parallel interface is used, this pin is the write signal input. Data is written into the
register at the rising edge of WR pulse. When the serial interface is used, this pin is the latch
signal input. This pin is normally high.

· RD (Read Enable)

When the parallel interface is used, this pin is the read signal input. While the pulse is low,
data can be read. The pin is normally high. When this pin is made low with C/D set low, the
display data pointed to by the address pointer is output from DB0 to DB7. When the pin is
made low with C/D set high, busy data is output from DB0 and low signals are output from
DB1 to DB7. After the rising edge of WR, busy data (H) is output. The data automatically
changes to non-busy (L) after the specified time elapses.
When the serial interface is used, fix this pin to "H" or "L".

· C/D (Command/Data Select)

This input pin selects whether the data to be input to the SI pin and the DB7 to DB0 pins is
handled as a command or display data, depending on the state of the pin at the rising edge
of WR. When the pin is H, the input data is handled as a command. When the pin is L, display
data is input.

· DB0 to DB7 (Data Buses 0 to 7)

Data input and output pins for the parallel interface. Normally data buses 0 to 7 are in high
impedance, when RD is driven low, display data and the busy signal are output.
When the serial interface is used, leave this pin open.

· SI (Serial Data Input)

Data input pin for the serial interface. Commands and display data are read at the rising edge
of SHT and written to registers at the rising edge of WR. The eight-bit data immediately before
the rising edge of WR is valid.
When the parallel interface is used, fix this pin to "H" or "L".

· SO (Serial Data Output)

Data output pin for the serial interface. The display data pointed to by the address pointer is
output at the rising edge of SHT. After the rising edge of WR, busy data (H) is output.
The data automatically changes to non-busy (L) after the specified time elapses.
When the parallel interface is used, this pin remains in the high impedance state.

· SHT (Shift Clock)

Clock input pin to input and output serial interface data. Data input is synchronous with the
rising edge of the clock, and the data output is synchronous with the falling edge of the clock.
This pin is normally high.
When the parallel interface is used, fix this pin to "H" or "L".

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MSM9000B-xx

· XT (Crystal)

Input pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this pin
and the XT pin, a crystal oscillation circuit is formed. When an external clock is used, input
the clock to the XT pin.

· XT (Crystal)

Output pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this
pin and the XT pin, a crystal oscillation circuit is formed. When the external clock is used,
leave this pin open.

18 pF

32.768 kHz

OPEN

External
clocks

When forming a crystal oscillation circuit

When inputting an external clock

Oscillation circuit diagram

· P/S (Parallel/Serial Select)

Input pin to choose between the parallel interface and serial interface. To select the parallel
interface, make this pin low. To select the serial interface, make this pin high. After power
is turned on, do not change the setting of this pin.

· 9D/16D (Duty Select)

Input pin to set a duty cycle. When this pin is set to "H", a duty cycle of 1/9 is selected.
When the pin is set to "L", a duty cycle of 1/16 is selected. Choose either according to the panel
to be used. When a duty cycle of 1/9 is chosen, leave common output pins COM10 to COM16
open.

· 32K/EXT (Clock Select)

Input pin to choose crystal oscillation mode or external clock input mode. Leave this pin at
a "L" level.

· RESET (Reset)

Reset signal input pin. Setting this pin to L results in the initial state. For modes and the
display after a reset input, see "Mode Settings after a Reset Input".

· N1, N2 (Contrast Change)

Input pins that determine the voltages of V

SS2

and V

SS3

together with contrast adjustment by

a command. The table below shows the relationships between pin states and contrast
adjustment ranges.

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MSM9000B-xx

Contrast adjustment range by command

0 to 7

1 to 8

2 to 9

3 to A

· TEST (Test Signal)

Test signal input pin provided for test by the manufacturer. Fix this pin to L or leave it open.

· SEG1 to SEG60 (Segment 1 to Segment 60)

Segment signal output pins to drive the LCD. Leave the unused pins open.

· COM1 to COM16 (Common 1 to Common 16)

Common signal output pins to drive the LCD. When the duty cycle is 1/9, use COM1 to COM9
and leave COM10 to COM16 open.

· V

Power supply pin to the logic section. Connect this pin to the positive terminal on the power
supply.

· V

Pin to be connected to the GND power supply.

· V

SS1

, V

SS4

, V

SS5

Pins for voltage multiplier outputs and LCD power supply. Connect capacitors of 0.1

between these pins and V

for the charge distribution with V

SS2

capacitor and for voltage

stabilization during generation of LCD bias voltages. The logical values of the LCD bias
voltage are as follows:

Highest voltage: V

SS1

SS2

SS4

SS2

Lowest voltage: V

SS5

SS2

/2+V

SS2

For both the 1/9 and 1/16 duty, 1/4 bias is used.

· V

SS2

Voltage regulator output pin & LCD bias generator input used as a reference voltage for the
LCD bias generator.
Connect a capacitor of 0.1

F between this pin and V

for charge distribution among

capacitors and voltage stabilization during generation of various LCD bias voltages.

· V

SS6

Pin to connect the capacitor to store the 3-/2-fold voltage. Connect a capacitor of 0.1

F or more

between this pin and V

· V

Halves output pin for the voltage multiplier(3-/2-fold). Connect a 0.1

F capacitor between

this pin and V

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MSM9000B-xx

LIST OF COMMANDS

No Mnemonics

Operation

Comments

LPA

Load Pointer

Address

Addresses 0-11, 16-27 for characters and

addresses 32-43, 48-59 for arbitrators

LOT

Load Option

Sets additional functions during execution of AINC.

Set Frequency

Sets conditions on master frequency.

BKCG 1/0

Bank Change 1/0

1/0 Valid only in 1/9 duty.

Changes display addresses 0-11, 16-27.

CONT U/D

Contrast

Up/Down

1/0 Adjusts VLCD to 8 stages.

Adjustment range is changed by setting N1 and

N2 pins.

Contrast level is up if D0="1".

Contrast level is down if D0="0".

STOP

Set

Stop Mode

This mode is cancelled if D0="1" irrespective of

either "H" or "L" on C/D.

Stops oscillation and performs operation

equivalent to that of the DISP OFF command.

SOE/D

Serial Out

Enable/Disable

1/0 Switches between output and high impedance

of SO.

DISP

Display On/Off

1/0

1/0 Display is ON if D0="1". Display is OFF if D0=0.

All commons and segments are at V

level if

display is OFF.

Arbitrators alone are displayed if D4="1".

AINC

Address

Increment

Pointer address is incremented by 1.

But, this command is invalid to operations that

are added by setting (I1, I0).

ABB

Arbitrator Blink

1/0 Data that is input after setting D0="1", is set as data

for arbitrator blink (1-dot unit).

This is cancelled by D0="0".

CHB

Character Blink

1/0

Controls blinking of character.

BPC

Blink Pattern

Control

1/0 Sets blink patterns of characters.

( : chara) if D0="1", ( : chara) if D0="0".

ABLC

Arbitrator Line

Change

Sets arbitrator display lines.

*: Don't Care

Notes :1 Pointer address is not changed even if commands numbers 1 to 8, 10, 12, 13 are enterd.

:2 Pointer address is automatically incremented by 1 when commands numbers 9, 11,

display code data, and arbitrator data are enterd.

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MSM9000B-xx

· LOT

A blank code is written for each subsequent AINC.

Remarks

Additional function

No additional function

Blinking is canceled for each subsequent AINC.

The above two functions are ORed.

Used to automatically clear RAM at power-on.

· SF

· DISP

· ABLC (when the duty is 1/16)

Arbitrator 1

Arbitrator 2

Remarks

COM1

COM2

COM15

COM16

COM1

Arbitrator 1 indicates display data at addresses

32 to 43, while arbitrator 2 indicates display data

at addresses 48 to 59.

· ABLC (when the duty is 1/9)

Arbitrator 1

Arbitrator 2

Remarks

COM1

COM2

COM8

COM9

COM1

Arbitrator 1 indicates display data at addresses

32 to 43, while arbitrator 2 indicates display data

at addresses 48 to 59.

XT 2

Remarks

Frequency of source oscillation in the IC

XT 4

XT 8

Used to generate the optimum frequency when external

clocks are input.

* : Don't care

Character

Arbitrator

Remarks

OFF

Used to turn on and off the display.

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MSM9000B-xx

· SF (Set Frequency)

[1, 0, 1, 0, X, X, F1, F0]
This command sets the number by which the external clock input from the XT pin is divided
in order to get the source frequency inside the IC. This command is valid when 32K/EXT pin
is "L". The dividing ratio is specified by F1 and F0 in the command. The table below lists the
source oscillation frequencies in the IC.
After RESET = "L", both F1 and F0 are set to "0".

Explanation of Commands

[D7, D6, D5, D4, D3, D2, D1, D0], X = Don't care

· LPA (Load Pointer Address)

[1, 1, A5, A4, A3, A2, A1, A0]
This command sets in the address pointer the address of the command to be executed or the
address of the display data to be input. The settable addresses are inconsecutive addresses
00H to 0BH, 10H to 1BH, 20H to 2BH, 30H to 3BH represented by A5 to A0. When addresses
0CH to 0FH, 1CH to 1FH, 2CH to 2FH, or 3CH to 3FH are set, 00H is assumed.
After RESET = "L", the address is set to 00H.

· LOT (Load Option)

[1, 0, 1, 1, X, X, I1, I0]
This command executes the additional function specified by I1 and I0 to the display of the
current address when the AINC command is executed. Additional functions are shown
below.
After RESET = "L",, both I1 and I0 are set to "0".

After this command is executed, the blank code is writtern each time AINC is executed.

Additional function

None

After this command is executed, blinking is canceled each time AINC is executed.

The above two additional functions are ORed.

XT 2

Frequency of source oscillation in the IC

XT 4

XT 8

· BKCG1/0 (Bank Change 1/0)

[1, 0, 0, X, 0, 0, 0, 1/0]
This command changes addresses (banks) to be displayed. The command is valid only when
the duty is 1/9. When D0 is 0, addresses 0 to 11 (character 1), 32 to 43, and 48 to 59 (arbitrators
1 and 2) are displayed. When D0 is "1", addresses 16 to 27 (character 2), 32 to 43, and 48 to 59
(arbitrators 1 and 2) are displayed. The command and display data can be set regardless of
the bank setting.
After RESET = "L", D1 is set to "0".

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MSM9000B-xx

· CONT U/D (Contrast Up Down)

[1, 0, 0, X, 0, 0, 1, 1/0]
This command selects the voltage of V

SS2

that is used as the reference voltage for the LCD

bias. When the value of V

SS2

is changed, the contrast is changed accordingly.

The contrast is controlled by the value of the 3-bit up/down counter so that eight stages are
supported. The value of the up/down counter is incremented when "1" is entered by this
command and decremented when "0" is entered. The counter changes within the range of 0
to 7.
When the counter reaches 7, it goes back to "0".
According to the settings of N1 and N2, the contrast stages can be changed to 1 to 8, 2 to 9, or
3 to A.
At stage 0, the bias voltage is minimized. The larger the contrast stage, the higher the bias
voltage. At stage A, the bias voltage is maximized.
After a low RESET is input, the counter is set to the minimum value specified by N1 and N2.

Example: · · · 6´7´0´1´2´3´4´5´6´7´0 · · ·

Note: At some contrast stages, the bias voltage may be increased to 5.5 V or higher. Adjust

the stage so that the bias voltage does not exceed 5.5 V.

· STOP (Set Stop Mode)

[1, 0, 0, X, 0, 0, 1, 0]
This command sets standby mode. Specifically, the command stops the oscillation block to
prevent current form flowing through the oscillation block and outputs the V

level to all

LCD output pins. Standby mode is canceled when D0 is set to "1" regardless of the setting of
the C/D pin. When a command or data with D0 set to "1" is entered, the command is executed
or the data is input. At the same time, standby mode is canceled.
After RESET = "L", standby mode is disabled.

· SOE/D (Serial Out Enable/Disable)

[1, 0, 0, X, 0, 1, 1, 1/0]
This command controls the impedance of the SO output pin. The command is valid only when
the serial interface is used. When D0 is set to "0", the SO pin is set in the high impedance state.
After RESET = "L", D0 is set to "0".

· DISP (Display On/Off)

[1, 0, 0, 1/0, 1, 0, 0, 1/0]
This command sets LCD display mode. When D0 is set to "1", the LCD is turned on. When
D0 is set to "0", the LCD is turned off, in which case, the V

level is output to all segment and

common pins. When the LCD is turned ON (D0="1"), and D4 is set to "1", only arbitrators are
displayed and when D4 is set to "0", both characters and arbitrators are displayed. The table
below lists display modes.
After RESET = "L", both D4 and D0 are set to "0".

Characters

Arbitrators

OFF

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MSM9000B-xx

· AINC (Address Increment)

[1, 0, 0, X, 1, 0, 1, X]
This command increments the value of the address pointer by one. Each time this command
is input, the value is incremented by one. Addresses are increased as follows: 00 to 11 Æ 16
to 27 Æ 32 to 43 Æ 48 to 59 Æ 00 ···. This cycle is repeated. The function specified by the LOT
command is performed for the previous address before the address incremented by one every
time this command is input.

· ABB (Arbitrator Blink)

[1, 0, 0, X, 1, 1, 0, 1/0]
This command turns arbitrator blinking on or off. Display data input after D0 is set to "1" is
handled as arbitrator blink data. Input blink data corresponds to dots of the arbitrator at the
same address on a one-to-one basis. When the dot is "1", blinking is enabled. When the dot
is "0", blinking is disabled. While the dot is blinking, it is turned on and off repeatedly.
Blinking can be specified for a dot for which enabling the arbitrator is not specified, but the
dot does not blink.
Dummy data must be set for arbitrator data D5 to D7. Data cannot be written to addresses 00
to 31 and 44 to 47.
After RESET = "L", D0 is set to "0".

· CHB (Character Blink)

[0, 0, 0, X, 0, 1, 1/0, X]
This command enables or disables character blinking. The command is executed for the
address pointed to by the address pointer. When D1 is set to "1", blinking is enabled. When
D1 is set to "0", blinking is disabled. During blinking, the turning on of all dots (5 ¥ 7 dots) and
character display are repeated. In another blinking pattern, the turning off of all dots and
character display are repeated. Either pattern is selected by the BPC command.
After RESET = "L", the value of the address pointer is automatically incremented by one.

· BPC (Blink Pattern Control)

[1, 0, 0, X, 1, 1, 1, 1/0]
This command selects a character blinking pattern. When D0 is set to "1", the turning on of
all dots (5 ¥ 7 dots) and character display are repeated. When D0 is set to "0", the turning off
of all dots and character display are repeated.
When D0 is "1" but the character is a blank, the character does not blink visibly. When D0 is
"0", the character does not blink visibly while all its dots are turned on.
After RESET = "L", D0 is set to "0".

[D0 = "1"]

[D0 = "0"]

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MSM9000B-xx

· ABLC (Arbitrator Line Change)

[0, 1, 1, X, X, X, L1, L0]
This command selects a common line for arbitrator display, according to the settings of L1 and
L0. The table below shows the relationships between L1 and L0 and displayed common lines,
assuming that the display data at addresses 00 to 11 is character 1, the display data at
addresses 16 to 27 is character 2, the display data at addresses 32 to 43 is arbitrator 1, and the
display data at addresses 48 to 59 is arbitrator 2. Different common lines are displayed for 1/
16 duty and 1/9 duty.
After a low RESET is input, both L1 and L0 are set to "0".
Common lines displayed by the ABLC command are as follows:

When 1/16 duty is chosen

Character 1

Character 2

Arbitrator 1

COM3 to 9

COM10 to 16

COM1 to 7

COM8 to 14

COM2 to 8

COM9 to 15

COM1

COM15

COM16

Arbitrator 2

COM2

COM16

COM1

When 1/9 duty is chosen

Character 1

Character 2

Arbitrator 1

COM3 to 9

COM1 to 7

COM2 to 8

COM1

COM8

COM9

Arbitrator 2

COM2

COM9

COM1

Note: When 1/9 duty is chosen, characters 1 and 2 can be switched by changing the bank.

· Increment of the address pointer by one

When display data or arbitrator blink data is input or the AINC or CHB command is executed,
the address pointer is incremented by one.

¡ Semiconductor

23/38

MSM9000B-xx

Mode Setting after a Reset Input

The table below lists the settings of individual modes during a RESET =L input.

· Even when a reset is input, display RAM is not initialized. To clear the display data, a blank

code must be written. (This can be done with an additional function of the AINC command.)

Mode Settings during Standby

The table below lists the settings of individual modes during standby.

· Data before standby mode is retained in display RAM.

Command

Mode setting

Remarks

LPA

LOT

The address pointer is set to "00".

Load Option command with no additional function.

The dividing ratio is set to 1.

A5 to A0 = "0"

I1 = "0", I0 = "0"

F1= "0", F0 = "0"

BKCG 1/0

Display addresses 00 to 11 are set.

D0 = "0"

CONT U/D

The control counter is set to 0 (Stage 0).

STOP

Standby mode is disabled.

SOE/D

The SO pin is set to the high impedance state.

D0 = "0"

DISP

Both characters and arbitrators display mode is set, but the dispaly is

turned off.

D4 = "0", D0 = "0"

ABB

Display data input mode is enabled.

D0 = "0"

BPC

Blink mode is such that the turning on of all dots and character display

are repeated.

D0 = "0"

ABLC

Arbitrator 1 corresponds to COM1, and arbitrator 2 corresponds to

COM2.

L1 = "0", L0 = "0"

Command

Mode setting

Remarks

LPA

LOT

The address pointer is set to "00".

The setting before standby mode is retained.

A5 to A0 = "0"

No change

BKCG 1/0

CONT U/D

The count before standby mode is retained.

STOP

Standby state 10. No change.

SOE/D

The setting before standby mode is retained.

D0 = "0"

DISP

Both character and arbitrator display mode is set, but the display is

turned off.

D4 = "0", D0 = "0"

ABB

BPC

The setting before standby mode is retained.

No change

ABLC

¡ Semiconductor

25/38

MSM9000B-xx

Calculation Method of Various Kinds of Frequencies

· Frame frequency

For 1/16 duty
(Source clock cycle) ¥ (1/Dividing ratio) ¥ 448 = Frame cycle · · · · · (1)
For 1/9 duty
(Source clock cycle) ¥ (1/Dividing ratio) ¥ 468 = Frame cycle · · · · · (2)

Example
Source oscillation frequency = 32.768 kHz
Dividing ratio = 1/1
Specification: 1/16 Duty
Clock cycle Ts = 30.5

Under these conditions, the frame frequency can be calculated from expression (1) as follows:
Frame cycle Tf = 30.5 ¥ 10

¥ 1 ¥ 448 = 13.66 ms

Therefore
Frame frequency = 73.2 Hz

· Calculating the blinking frequency

The blinking frequency can be calculated from the following expression:

Blinking frequency = (Source clock cycle) ¥ (1/Dividing ratio) ¥ 2

· · · · · (3)

Example
Source oscillation frequency = 32.768 kHz
Dividing ratio = 1/1
Clock cycle T

= 30.5

Under these conditions, the blinking frequency can be calculated from expression (3) as
follows:
Blinking cycle Tf = 30.5 ¥ 10

¥ 1 ¥ 2

= 1 s

Therefore
Blinking frequency = 1 Hz

· Source oscillation frequency and busy time

When data is written to or read from RAM or a command is input, data processing time (busy
time) is taken. The maximum busy time is the source clock cycle multiplied by 10. The busy
signal (not-busy = "L", busy = "H" ) is detected at the SO pin when the serial interface is used
or at the DB0 pin when the parallel interface is used. When display data or commands are
input consecutively, a wait must be inserted for the source clock cycle multiplied by 10.
Another way is to detect busy signals and input data or commands during not-busy time only.

¡ Semiconductor

26/38

MSM9000B-xx

Flowchart at Power-on (parallel interface)

Turn on the power

Input a reset

CS="L"

Set modes for SF, BKCG1/0,

BPC, and ABLC

LOT, I1="1", I0="1"

AINC ¥ 48 times

LOT, I1="0", I0="0"

DISP, D4="X", D0="1"

Perform ordinary operation

Has data to be displayed

on the initial screen been

input?

5ms, external, or power-on reset

Chip enable.

Set a mode by the reset input according to specifications.

Set the load option. The blank code is written and
blinking is released each time AINC is executed.

RAM data is cleared.

The load option is cleared.

The display is turned on. The initial screen is displayed.
Set D4 according to the display.

YES

Input data to be displayed

on the initial screen

Input a reset after the V

level exceeds 2.5V.

· When the stage to be selected is already determined, contrast can be adjusted before the

display is turned on (for example, at the same time as when mode is set).

· After a command or display data is input, check for busy data. Make sure that the busy data

("H") has changed to not-busy data ("L") before making the next input.

¡ Semiconductor

27/38

MSM9000B-xx

Flowchart at Power-on (serial interface)

· When the stage to be selected is already determined, contrast can be adjusted before the

display is turned on (for example, at the same time as when mode is set).

· After a command or display data is input, check for busy data. Make sure that the busy data

("H") has changed to not-busy data ("L") before making the next input.

Turn on the power

Input a reset

CS="L"

SOE/D, D0="1"

Wait for 10 clocks

Set modes for SF, BKCG1/0,

BPC, and ABLC

LOT, I1="1", I0="1"

AINC ¥ 48 times

LOT, I1="0", I0="0"

DISP, D4="X", D0="1"

Perform ordinary operation

Has data to be displayed

on the initial screen been

input?

5ms, external, or power-on reset

Chip enable.

SO output is enabled to detect busy signal.

Insert a wait only in processing the SOE/D command.
(By busy signal detection for subsequent inputs).

Change the settings after a reset, if necessary.

Set the load option. The blank code is written and
blinking is disabled each time AINC is executed.

RAM data is cleared.

The load option is cleared.

The display is turned on. The initial screen is displayed.
Set D4 according to the display.

YES

Input data to be displayed

on the initial screen

Input a reset after the V

level exceeds 2.5V.

¡ Semiconductor

31/38

MSM9000B-xx

Codes and Character Fonts of Code -01

00H :

08H :

10H :

18H :

20H : SP

28H : (

30H : 0

38H : 8

01H :

09H :

11H :

19H :

21H : !

29H : )

31H : 1

00H : 9

02H :

0AH :

12H :

1AH :

22H : "

2AH :

32H : 2

3AH : :

03H :

0BH :

13H :

1BH :

23H : #

2BH : +

33H : 3

3BH : ;

04H :

0CH :

14H :

1CH :

24H : $

2CH : ,

34H : 4

3CH : <

05H :

0DH :

15H :

1DH :

25H : %

2DH :

35H : 5

3DH : =

06H :

0EH :

16H :

1EH :

26H : &

2EH : .

36H : 6

3EH : >

07H :

0FH :

17H :

1FH :

27H : '

2FH : /

37H : 7

3FH : ?

¡ Semiconductor

32/38

MSM9000B-xx

40H : @

48H : H

50H : P

58H : X

60H : `

68H : h

70H : p

78H : x

41H : A

49H : I

51H : Q

59H : Y

61H : a

69H : i

71H : q

79H : y

42H : B

4AH : J

52H : R

5AH : Z

62H : b

64H : j

72H : r

7AH : z

43H : C

4BH : K

53H : S

5BH : [

63H : c

6BH : k

73H : s

7BH : {

44H : D

4CH : L

54H : T

5CH :

64H : d

6CH : I

74H : t

7CH :

45H : E

4DH : M

55H : U

5DH : ]

65H : e

6DH : m

75H : u

70H : }

46H : F

4EH : N

56H : V

5EH : ^

66H : f

6EH : n

76H : v

7EH : ~

47H : G

4FH : O

57H : W

5FH : _

67H : g

6FH : o

77H : w

7FH : £

¡ Semiconductor

33/38

MSM9000B-xx

8ØH : Ä

88H : ä

9ØH : n

98H :

A0H : ¥

A8H :

B0H : --

B8H :

81H : A

89H : a

91H : ö

99H : i

A1H :

49H :

B1H :

B9H :

82H : Æ

8AH : à

92H : Ù

9AH : ¿

A2H :

AAH :

B2H :

BAH :

83H : Ç

93H : ü

9BH : §

A3H :

ABH :

B3H :

BBH :

84H : É

8CH : æ

94H : a

9CH : °

A4H :

aCH :

B4H :

BCH :

85H : N

8DH : ç

95H : b

9DH : ¨

A5H :

ADH :

B5H :

BDH :

86H : Ö

8EH : é

96H : Ø

9EH : º

A6H :

AEH :

B6H :

BEH :

87H : Ü

8FH : è

97H : ø

9FH : ¢

27H :

2FH :

37H :

3FH :

8BH : a

¡ Semiconductor

35/38

MSM9000B-xx

APPLICATION CIRCUITS

Example 1
[1/16 duty, parallel interface, crystal oscillation circuit and bias voltage generator used]

common

drivers

Segment

drivers

C1 to C16

S1 to S60

LCD Panel

MSM9000B-xx

PORT

SS1

SS2

SS4

SS5

CC1

CC2

SS6

32K/EXT

9D/16D

RESET

DB7-0

C=0.1 mF

or V

OPEN

18 pF

5 x 7 dot characters x 12
characters x 2 lines
60 symbols x 2 lines

TEST

SHT

P/S

18 pF

32.768 kHz

100 kW

1 mF

¡ Semiconductor

36/38

MSM9000B-xx

Example 2
[1/9 duty, serial interface, 32kHz external clock input and bias voltage generator used]

common

drivers

Segment

drivers

C1 to C9

S1 to S60

LCD Panel

MSM9000B-xx

PORT

SS1

SS2

SS4

SS5

CC1

CC2

SS6

32K/EXT

9D/16D

RESET

DB7-0

C=0.1 mF

or V

5 x 7 dot characters x 12
characters x 1 line
60 symbols x 2 lines

TEST

SHT

P/S

100 kW

1 mF

OPEN

C10 to C16

32 kHz External Clock

¡ Semiconductor

37/38

MSM9000B-xx

PAD CONFIGURATION

Pad Layout

Chip size: 4.76 ¥ 3.29 mm
Bump size: 78 ¥ 100 mm

112

Pad No.

Pad Name

Y (µm)

X (µm)

Pad No.

Pad Name

Y (µm)

X (µm)

1508

2012

CC1

1508

1487

1508

1837

1508

1662

C/D

1508

1662

1508

1837

1508

1487

SS6

1508

2012

1508

1312

CC2

1375

2194

1508

1137

1255

2194

SHT

1508

962

SS1

1135

2194

1508

787

SS2

1015

DB7

1508

612

SS4

895

DB6

1508

437

SS5

775

DB5

1508

262

COM9

605

DB4

1508

COM10

495

DB3

1508

COM11

385

DB2

1508

262

COM12

275

DB1

1508

437

COM13

165

DB0

1508

612

COM14

1508

787

COM15

TEST

1508

962

COM16

165

1508

1137

SEG60

275

1508

1312

SEG59

385

2194

Pad Coordinates

¡ Semiconductor

38/38

MSM9000B-xx

Pad No.

Pad Name

Y (µm)

X (µm)

Pad No.

Pad Name

Y (µm)

X (µm)

SEG58

495

2194

SEG18

1508

1337

605

2194

1508

1444

715

2194

1508

1552

825

2194

1508

1659

935

2194

1508

1765

1045

2194

1508

1872

1155

2194

1508

1980

1265

2194

1375

2194

1265

1508

1980

1155

1508

1872

1045

1508

1765

935

1508

1659

825

1508

1552

715

1508

1444

605

1508

1337

495

1508

1231

385

1508

1123

275

1508

1016

165

1508

910

100

2194

1508

803

101

1508

695

102

165

1508

588

103

275

1508

482

104

385

1508

374

105

495

1508

267

106

605

1508

161

107

775

1508

108

895

1508

109

1015

1508

161

110

1135

1508

267

111

1255

1508

374

112

1375

1508

482

1508

588

1508

695

1508

803

1508

910

1508

1016

1508

1123

1508

1231

SEG57

SEG17

SEG56

SEG16

SEG55

SEG15

SEG54

SEG14

SEG53

SEG13

SEG52

SEG12

SEG51

SEG11

SEG50

SEG10

SEG49

SEG9

SEG48

SEG8

SEG47

SEG7

SEG46

SEG6

SEG45

SEG5

SEG44

SEG4

SEG43

SEG3

SEG42

SEG2

SEG41

SEG1

SEG40

COM8

SEG39

COM7

SEG38

COM6

SEG37

COM5

SEG36

COM4

SEG35

COM3

SEG34

COM2

SEG33

COM1

SEG32

RESET

SEG31

32K/EXT

SEG30

9D/16D

SEG29

P/S

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

2194

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM9000B-xx

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM9000B-xx