¡ Semiconductor

MSM9223

1/24

GENERAL DESCRIPTION

The MSM9223 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent
display tube. It conststs of 27-segment driver outputs and 3-grid pre-driver outputs, so that it
can drive directly up to 81-segment VFD.
MSM9223 features a digital dimming function, a 6-ch ADC, a 5 ¥ 5 keyscan circuit and an encoder
type switch interface.
MSM9223 provides an interface with a microcontroller only by three signal lines: DATA I/O,
CLOCK and CS.

FEATURES

· Supply voltage (V

)

: 8 to 18.5V (Built-in 5V regulator for logic)

· Duplex/Triplex selectable
· Applicable VFD tube

: 2 Grids ¥ 27 Anodes VFD tube
: 3 Grids ¥ 27 Anodes VFD tube

· 27-segment driver outputs

: I

=5mA at V

0.8V (SEG1 to 19)

=10mA at V

0.8V (SEG20 to 27)

· 3-grid pre-driver outputs

: I

=10mA at V

=2V

· Built-in digital dimming circuit (10-bit resolution)
· Built-in 6-ch A/D converter
· Built-in 5 ¥ 5 keyscan circuit
· Interface circuit for an encoder type rotary switch
· Built-in oscillation circuit (external R and C)
· Built-in Power-On-Reset circuit
· Package:

64-pin plastic QFP (QFP64-P-1420-1.00-BK)

Product name: MSM9223GS-BK

¡ Semiconductor
MSM9223

27-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan

E2C0044-19-96

This version: Sep. 1999

Previous version: Aug. 1999

¡ Semiconductor

MSM9223

2/24

BLOCK DIAGRAM

Timing Generator

DIM OUT

SYNC OUT1

SYNC OUT2

DUP/TRI

OSC

Control

Out1-27

27bit Shift Register

in1-10

Dimming Latch

Out1-10

10bit Digital

Dimming

POR

CLOCK

DATA I/O

Out1-3

3bit Shift Register

POR

Out1-27

Segment Latch

in1-27

POR

Out1-27

Segment Latch

in1-27

POR

Out1-27

Segment Latch

in1-27

POR

Mode Select

in1-3

POR

Regulator

Power On

Reset

(5V)

L-GND

POR

Out1-27

81 to 27 Segment Control

in1-27

27 Segment Driver

D-GND

3 Grid pre Driver

GRID2 GRID3

GRID1

SEG27

SEG1

VREG

(5V)

5 ¥ 5 Key Scan and Encoder Switch Interface

INT

6ch, 8bit

A/D Converter

OSCO

CH1

CH6

COL1

COL5

ROW1

ROW5

5H
6H

¡ Semiconductor

MSM9223

3/24

PIN CONFIGURATION (TOP VIEW)

SEG17

SEG22

SEG23

SEG24

L-GND

INT

DUP/

TRI

OSCO

SEG16

SEG18

SEG19

SEG21

SEG20

SEG15

SEG14

SEG13

SEG12

DATA I/O

CLOCK

SYNC OUT2

SYNC OUT1

DIM OUT

SEG10

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

CH6

CH5

SEG9

CH4

CH3

CH2

CH1

VREG

SEG11

COL2

COL3

COL4

COL5

SEG25

SEG26

SEG27

GRID1
GRID2
GRID3

D-GND

ROW1

ROW2

ROW3

ROW4

ROW5

COL1

NC: No connection

64-pin Plastic QFP

¡ Semiconductor

MSM9223

4/24

PIN DESCRIPTIONS

Pin

Type

Description

1, 51

Power supply pins.
Pin1 and pin51 should be connected externally.

40 to 50,

52 to 59

D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. Pins 8 and 26 should be connected externally.

Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube. External circuit is not required.
I

5 mA

60 to 64,

2 to 4

Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube. External circuit is not required.
I

10 mA

5, 6, 7

Inverted Grid signal output pins.
For pre-driver, the external circuit is requiend.
I

10 mA

Chip Select input pin.
Data input/output operation is valid when this pin is set at a High level.

Serial clock input pin.

Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock.

I/O

Serial data input/output pin.
Data is input to / comes out from the shift register at the rising edge of the serial clock.

Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set at a V

level.

Triplex (1/3 duty) operation is selected when this pin is set at a GND level.

Symbol

D-GND

L-GND

SEG1 to 19

SEG20 to 27

GRID1 to 3

CLOCK

DATA I/O

DUP/TRI

5V output pin for internal logic portion and external logic circuit.

REG

Reference voltage (5V) output pin for A/D converter.

Interrupt signal output to microcontroller. When any key of key matrix is pressed
or released, key scanning is started. After the completion of the one cycle, this pin
goes to high level and keeps the high level until keyscan stop mode is selected.

INT

20, 21

Input pin for the encoder type rotary switch. Each input has chattering
absorption function of 620ns typical.

A1, B1

34 to 39

CH1 to 6

Analog voltage input pin for the 8-bit A/D converter.

14 to 18

Return inputs from the key matrix.
These pins are active low. When key matrix are in the inactive sate, these
pins are at high level through the internal pull-up resistors. All the inputs do
not have the cahttering absorption function for the keyscans.

COL1 to 5

9 to 13

Key switch scanning outputs.
Normally low level is output through these pin. When any switch of key matrix
is depressed or released, key scanning is started and is continued until
keyscan stop mode is selected. When keyscan stop mode is selected, all
outputs of ROW1 to 5 go back to low level.

ROW1 to 5

¡ Semiconductor

MSM9223

5/24

Pin

Type

Description

30, 31

Synchronous signal input.
Connect these pins to the SYNC IN1 and SYNC IN2 pins
of a slave side.

Symbol

SYNC OUT 1, 2

I/O

RC oscillator connecting pins.
Connect a resistor (R2) between the V

and OSC0 pins,

and a capacitor (C2) between the OSC0 pin and the GND,
and a capacitor (C3) between the V

and the GND. C

is for V

stabilization.

OSC0

Dimming pulse output.
Connect this pin to the slave side DIM IN pin.

DIM OUT

¡ Semiconductor

MSM9223

6/24

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Driver Supply Voltage

High Level Input Voltage

Low Level Input Voltage

Clock Frequency

Operating Temperature

Condition

Min.

Typ.

Max.

Unit

8.0

13.0

18.5

All inputs except OSC0

3.8

5.5

All inputs except OSC0

0.0

0.8

1.0

MHz

+85

°C

OSC

Oscillation Frequency

= 10kW±5%, C

= 27pF±5%

2.6

3.3

4.0

MHz

Frame Frequency

1/3 Duty

211

269

325

1/2 Duty

317

403

488

= 10kW±5%

= 27pF±5%

Parameter

Symbol

Condition

Rating

Unit

Supply Voltage

Input Voltage

Ta = 85°C

Power Dissipation

STG

°C

Storage Temperature

SEG1 to 19

SEG20 to 27

Output Current

GRID1 to 3

DIM OUT, SYNC OUT1, SYNC OUT2

0.3 to +20

0.3 to +6.0

590

55 to +150

10.0 to +2.0

20.0 to +2.0

7.0 to +20.0

2.0 to +2.0

¡ Semiconductor

MSM9223

7/24

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

Symbol

High Level Input Voltage

Low Level Input Voltage

IH1

High Level Input Current

IL1

Low Level Input Current

OH1

OH2

OH3

High Level Output Voltage

Condition

Min.

Max.

Unit

3.8

5.5

0.0

0.8

=3.8V

5.0

+5.0

=0.0V

5.0

+5.0

0.8

4.0

5.5

=9.5V

Applied pin

*1)

*2)

SEG1 to 19

SEG20 to 27

GRID1 to 3

OH4

*4)

OH1

=5mA

OH2

=10mA

OH3

=5mA

OH4

=200mA

OL1

OL2

OL3

Low Level Output Voltage

2.0

0.8

=9.5V

SEG1 to 19

SEG20 to 27

GRID1 to 3

OL4

*5)

OL1

=500mA

OL2

=500mA

OL3

=10mA

OL4

=300mA

Supply Current

OSC

=3.3MHz, no load

(Ta=40 to +85°C, V

=8.0 to 18.5V)

4.5

5.5

Supply Voltage for Logic

=0.01mF±10%, I

=0 to 10mA

4.5

5.5

Output Open

IH2

IL2

=3.8V

100

5.0

=0.0V

300

*3)

*1) CS, CLOCK, DATA I/O DUP/TRI, A1, B1, COL1 to 5
*2) CS, CLOCK, DATA I/O DUP/TRI, A1, B1
*3) COL1 to 5
*4) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2
*5) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5

¡ Semiconductor

MSM9223

8/24

AC Characteristics

Parameter

Symbol

Clock Frequency

Clock Pulse Width

Data Setup Time

Data Hold Time

CSL

CS Off Time

CSS

PRZ

CS Setup Time
(CS-Clock)

Output Slew Rate Time

Rise Time

Condition

Min.

Max.

Unit

1.0

MHz

400

R2=10kW±5%, C2=27pF±5%

400

=20% to 80%

4.0

=80% to 20%

4.0

Mounted in a unit

100

=100pF

CSH

CS Hold Time
(Clock-CS)

400

POF

Off Time

Mounted in a unit, V

=0.0V

5.0

DATA Output Delay Time
(Clock-DATA I/O)

1.0

(Ta=40 to +85°C, V

=8.0 to 18.5V)

RSOFF

CS Wait Time

400

¡ Semiconductor

MSM9223

10/24

A/D Converter Characteristics

Keyscan Characteristics

Keyscan Timing

Parameter

A/D Conversion Accuracy

Condition

Typ.

Max.

Unit

±1

LSB

Reference Voltage (V

REG

)

5.0

5.5

Output Current

Input Voltage Range

REG

Conversion Time/Channel

R2 = 10kW±5%, C2 = 27pF±5%

310

Min.

4.5

GND

256

394

(Ta = 40 to +85°C, V

= 8.0 to 18.0 V)

Parameter

Keyscan Cycle Time

Condition

Typ.

Max.

Unit

R2 = 10kW±5%, C2 = 27pF±5%

194

246

Keyscan Pulse Width

R2 = 10kW±5%, C2 = 27pF±5%

Min.

160

(Ta = 40 to +85°C, V

= 8.0 to 18.0 V)

ROW1

ROW5

ROW2

ROW3

ROW4

Keyscan Cycle Time

Keyscan Pulse

Width

¡ Semiconductor

MSM9223

11/24

Output Timing (Duplex Operation)

*1bit time=4/f

OSC

(The dimming data is 1016/1024)

GRID1

D-GND

GRID2

D-GND

GRID3

SEG1-27

D-GND

DIM OUT

5 V

L-GND

SYNC OUT1

5 V

L-GND

SYNC OUT2

5 V

L-GND

D-GND

2048bit times (1 display cycle)

1016bit times

1019bit times

1029bit times

1019bit times

1029bit times

5bit times

3bit times

8bit times

5bit times

Output Timing (Triplex Operation)

*1bit time=4/f

OSC

(The dimming data is 1016/1024)

GRID1

D-GND

GRID2

D-GND

GRID3

SEG1-27

D-GND

DIM OUT

5 V

L-GND

SYNC OUT1

5 V

L-GND

SYNC OUT2

5 V

L-GND

D-GND

3072bit times (1 display cycle)

1016bit times

1019bit times

1029bit times

1019bit times

1029bit times

5bit times

3bit times

8bit times

5bit times

1019bit times

1016bit times

8bit times

¡ Semiconductor

MSM9223

12/24

Output Timing (Duplex Operation)

*1bit time=4/f

OSC

(The dimming data is 64/1024)

GRID1

D-GND

GRID2

D-GND

GRID3

SEG1-27

D-GND

DIM OUT

5 V

L-GND

SYNC OUT1

5 V

L-GND

SYNC OUT2

5 V

L-GND

D-GND

2048bit times (1 display cycle)

64bit times

960bit times

64bit times

957bit times

67bit times

957bit times

67bit times

957bit times

67bit times

3bit times

957bit times

67bit times

957bit times

67bit times

957bit times

67bit times

957bit times

1981bit times

957bit times

67bit times

957bit times

67bit times

957bit times

1981bit times

957bit times

67bit times

Output Timing (Triplex Operation)

*1bit time=4/f

OSC

(The dimming data is 64/1024)

GRID1

D-GND

GRID2

D-GND

GRID3

SEG1-27

D-GND

DIM OUT

5 V

L-GND

SYNC OUT1

5 V

L-GND

SYNC OUT2

5 V

L-GND

D-GND

3072bit times (1 display cycle)

64bit times

960bit times

64bit times

957bit times

67bit times

957bit times

67bit times

957bit times

67bit times

3bit times

960bit times

64bit times

957bit times

67bit times

957bit times

67bit times

957bit times

67bit times

957bit times

1981bit times

957bit times

67bit times

957bit times

67bit times

957bit times

1981bit times

957bit times

67bit times

¡ Semiconductor

MSM9223

13/24

FUNCTIONAL DESCRIPTION

Power-on Reset
When power is turned on, MSM9223 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
· The contents of the shift registers and latches are set to "0".
· The digital dimming duty cycle is set to "0".
· All segment outputs are set to Low level.
· All grid outputs are set to High level.
· All the ROW outputs are set to Low level.
· INT output is set to Low level.

Data Input and Output
Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High
level.
The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial
clock. The data is automatically loaded to the latches when the CS pin is set at a Low level.
10-bit dimming data (D1 to D10) and 27-bit segment data (S1 to S27) are used for inputting of
dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be
sent after each of these data succeddingly.
The output data from the DATA I/O pin is output from the shift register at the rising edge of the
serial clock.
MSM9223 outputs 48-bit (6ch ¥ 8bits) A/D data (A11 to A68) and 29-bit key data (S11 to S55, R1
and Q1 to Q3). To receive these data, the mode data (M0 to M2) mast be sent first and then CS
must be set once to Low level and set again to High level.
Then inputting serial clocks, these data are output from the DATA I/O pin.
When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin.
To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer,
the key scanning is stopped immediately.

Mode Data
MSM9223 has the seven function modes. The function mode is selected by the mode data (M0 to
M2). The relation between function mode and mode data (M0 to M2) is as follows:

FUNCTION MODE

OPERATING MODE

FUNCTION DATA

Segment Data for GRID1-3 Input

Segment Data for GRID1 Input

Segment Data for GRID2 Input

Segment Data for GRID3 Input

Digital Dimming Data Input

Keyscan Stop

Switch Data Output

A/D Data Output

¡ Semiconductor

MSM9223

14/24

Segment Data Input [Function Mode: 0 to 3]
· MSM9223 receives the segment data when function mode 0 to 3 are selected.
· The same segment data is transferred to the 3 segment data latch correspond to GRID 1 to 3 at

the same time when the function mode 0 is selected.

· The segment data is transferred to only one segment data latch that is selected by mode data,

when the function mode is 1, 2 or 3 is selected.

· Segment output (SEG1 to 27) becomes High level when the segment data (S1 to 27) is High level.

[Data Format]

Input Data

: 30 bits

Segment Data : 27 bits
Mode Data

: 3 bits

S24

S25

S26

S27

Bit

Input Data

Segment Data (27bits)

Mode Data

(3bits)

[Bit correspondence between segment output and segment data]

S17

S18

S19

S20

S21

S22

S23

S24

S25

S10

S26

S11

S27

S12

S13

S14

S15

S16

SEG n

Segment data

SEG n

Segment data

¡ Semiconductor

MSM9223

15/24

Digital Dimming Data Input [Function Mode: 4]
· MSM9223 receives the digital dimming data when function mode 4 is selected.
· The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
· The 10-bit digital dimming data is input from LSB.

[Data Format]

Input Data

: 13 bits

Digital Dimming Data: 10 bits
Mode Data

: 3 bits

D10

Bit

Input Data

Digital Dimming Data (10bits)

Mode Data

(3bits)

D10

Dimming Data

(MSB)

(LSB)

Duty Cycle

0/1024

1/1024

1015/1024

1016/1024

LSB

MSB

¡ Semiconductor

MSM9223

16/24

Keyscan Stop [Function Mode: 5]
· MSM9223 stops a key scanning when function mode 5 are selected.
· To select this mode, the only mode data (M0 to M2) is needed.
· The actual time lag range between receipt of the keyscan stop command and the ceasing of

scanning is 2.4ms to 3.6ms

[Input Data Format]

Input Data

: 3 bits

Mode Data

: 3 bits

Switch Data Output [Function Mode: 6]
· MSM9223 output the switch data when function mode 6 is selected.
· To select this mode, the only mode data (M0 to M2) is needed.
· When MSM9223 recieves this mode, the DATA I/O pin is changed to an output pin.
· 29-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the

clock.

· When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.
· R1=0, implies Right rotation of the knob (Clockwise)
· R1=1, implies Left rotation of the knob (Counter Clockwise)
· Contact Count bits are Q1 (LSB) to Q3 (MSB)

[Input Data Format]

Input Data

: 3 bits

Mode Data

: 3 bits

[Output Data Format]

Output Data

: 29 bits

5¥5 push swithc Data : 25 bits
Encoder switch Data : 4 bits

Bit

Input Data

Mode Data

(3bits)

Bit

Input Data

Mode Data

(3bits)

S11

S41

S12

S42

S13

S43

S14

S44

S15

S45

S21

S51

S22

S52

S23

S53

S24

S54

S25

S55

S31

S32

S33

S34

S35

Bit

Output Data

Bit

Output Data

Sij : i=ROW1 to 5, j=COL1 to 5

Sij=1 : Switch ON
Sij=0 : Switch OFF

¡ Semiconductor

MSM9223

17/24

A/D Data Output [Function Mode: 7]
· MSM9223 output the A/D data when function mode 7 is selected.
· To select this mode, the only mode data (M0 to M2) is needed.
· When MSM9223 recieves this mode, the DATA I/O pin is changed to an output pin.
· 48-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the

clock.

· When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.

[Input Data Format]

Input Data

: 3 bits

Mode Data

: 3 bits

[Output Data Format]

Output Data

: 48 bits

A/D Data

: 48 bits

Bit

Input Data

Mode Data

(3bits)

A11

(LSB)

A12

A13

A14

CH1

A15

A16

A17

A18

(MSB)

A21

(LSB)

A22

A23

A24

CH2

A25

A26

A27

A28

(MSB)

A31

(LSB)

A38

(MSB)

A41

(LSB)

A48

(MSB)

A51

(LSB)

A58

(MSB)

A61

(LSB)

A68

(MSB)

Bit

Output Data

A/D

17 18

A32

A33

A34

CH3

A35

A36

A37

24 25 26

A42

A43

A44

CH4

A45

A46

A47

Bit

Output Data

A/D

33 34

A52

A53

A54

CH5

A55

A56

A57

40 41 42

A62

A63

A64

CH6

A65

A66

A67

Bit

Output Data

A/D

¡ Semiconductor

MSM9223

18/24

The rotary encoder switch function.
As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt
generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.

Fig.1 The Rotary Encoder Switch Circuit

1) Phase detection
1-1) Clockwise
The input A and B have a chattering absorption circuit of 620ns (typ.). When signal A and B input
as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At
this time, the output INT also goes to high level, so this signal can be used as an interrupt. The
INT stays High level until the switch data-output mode is selected.

Fig.2 The Input and Output Timing in Case of Clockwise.

Phase Detection

DOWN

Q3 Q2 Q1

UP/DOWN Counter

P-in/S-out Shift Registor

Direction Latch

Interrupt

Generation

for INT

Output data

UP (internal)

INT

chattering absorption time

¡ Semiconductor

MSM9223

19/24

2) UP/DOWN COUNTER
When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts
down.
But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111".

Fig.4

3) Direction latch
When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and
the counts value change to plus value, the output R goes to "0".

Fig.5

Fig.3 The Input and Output Timing in Case of Counter Clockwise.

DOWN (internal)

INT

chattering absorption time

Q3, Q2, Q1

001

010

011

100

101

110

111

Q1, Q2, Q3

010

100

000

010

1-2) counter clockwise
When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the
chattering absorption period. At this time, the output INT also goes to High level. The INT stays
High level until the switch data-output mode is selected.

¡ Semiconductor

MSM9223

21/24

Keyscan
Keyscanning is started only when depression or release of any key is detected in order to
minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan
stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion
of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be
used as an interrupt signal.

[Keyscan Timing]

1 Cycle

INT

ROW 4

ROW 3

ROW 2

ROW 1

ROW 0

Depress/Release

Keyscan stop mode
is selected.

Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if:

- keyscanning is started after depression or release of any key is detected, and then
- a key is depressed or released again before the keyscan stop mode is selected.
To stop keyscanning, it is required to select the keyscan stop mode once again.

Depress

Release

Keyscan

INT

MODE5

MODE5 : Keyscan stop

¡ Semiconductor

MSM9223

22/24

APPLICATION CIRCUITS

1. Circuit for the duplex VFD tube with 118 segments (2 Grid

59 Anode)

MSM9223

L-GND

OSC0

CLOCK

DATA I/O

VREG

DUP/TRI

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG27

MSM9210

(SLAVE)

DISP

L-GND

OSC 0

OSC 1

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG32

Duplex VFD Tube

S57 S58 S59

S1 S2 S3

Microcontroller

DISP

M/S

GND

DUP/TRI

GND

CH1 to 6

ROW1 to 5
COL1 to 5

5 ¥ 5

Key matrix

¡ Semiconductor

MSM9223

23/24

2. Circuit for the triplex VFD tube with 177 segments (3 Grid

59 Anode)

MSM9223

L-GND

CLOCK

DATA I/O

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG27

MSM9210

(SLAVE)

DISP

L-GND

OSC 0

OSC 1

CLOCK

DATA IN

DIM IN

SYNC IN 1

SYNC IN 2

M/S

DUP/TRI

DIM OUT

SYNC OUT 1

SYNC OUT 2

GRID2

GRID1

GRID3

SEG1

SEG32

Triplex VFD Tube

S57 S58 S59

S1 S2 S3

G1
G2

Microcontroller

DISP

GND

OSC0

GND

CH1 to 6

ROW1 to 5
COL1 to 5

5 ¥ 5

Key matrix

VREG

DUP/TRI

¡ Semiconductor

MSM9223

24/24

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

QFP64-P-1420-1.00-BK

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
1.25 TYP.

Mirror finish

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

E2Y0002-29-62

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