1/9

MSM9842

¡ Semiconductor

FEDL9842-02

GENERAL DESCRIPTION

The MSM9842 is a mono/stereo playback LSI with a built-in 1K bit FIFO for easy interface with
external systems or non-semiconductor memory. It utilizes multiple playback modes, including
the new ADPCM2 algorithm, which allows for even higher quality sound reproduction. The
playback function of the MSM9842 is controlled by an MCU via 8/16-bit bus interface.

FEATURES

· 16/8-bit bus interface support
· FIFO capacity: User-definable (256/512/1024 bits)

(buffering time of 32 ms when using 8 kHz sampling frequency, 4-bit ADPCM2/ADPCM, and
in monaural playback)

· Supports four compression algorithms for playback:

4, 5, 6, 7, 8-bit ADPCM2; 4-bit ADPCM; 8; 16-bit PCM; and 8-bit Nonlinear PCM

· Sampling frequency: 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz (fosc=4.096 MHz)
· Sampling frequency: 22.05 kHz, 44.1 kHz (fosc=5.6448 MHz)
· DMA interface support
· Volume control (8 steps: 0 dB to 21 dB)
· Built-in 14-bit D/A converter
· Built-in low pass filter (LPF)
· Power supply voltage: 2.7 V to 5.5 V
· Package:

56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM9842GA)

¡ Semiconductor

MSM9842

Playback LSI with Built-in FIFO

This document contains minimum specifications. For full specifications, please contact your
nearest Oki office or representative.

This version: Jul. 2000

Previous version: May 1998

FEDL9842-02

3/9

MSM9842

¡ Semiconductor

FEDL9842-02

PIN CONFIGURATION (TOP VIEW)

NC : No Connection

56-pin plastic QFP

BUSY

D/C
CS
RD
WR

FUL/DREQR

MID

EMP

CH/DACKR
RESET

AOUTR

D10

D11

TEST3

IOW

DREQL

DACKL

DGND

TEST1

TEST0

VCK

TEST2

DASD

SOCK

D12

D13

D14

D15

DGND

AGND

TEST4

OUTL

4/9

MSM9842

¡ Semiconductor

FEDL9842-02

PIN DESCRIPTIONS

Symbol

Type

Description

For 8-bit bus interface, the command allows these pins to be configured to be inputs to input

data to and from an external memory. Otherwise, these pins are configured to be inputs only.

For 16-bit interface, these pins are a bidirectional data bus to input data to and from an external

microcontroller and memory.

Birirectional data bus to input data and output status to and from an external microcontroller

and memory.

Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins.

Read pulse input pin. This pin pulses "L" when status is output to D7-D0 pins.

Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read

pulse when this pin is "H".

Voice data is input to D15-D0 pins when this pin is "H". Command is input to and status is

output from D7-D0 pins when this pin is "L".

This pin outputs a "L" level during, PLAYBACK or PAUSE.

"H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L"

by command input.

"H" level indicates that more than half of the FIFO memory space is filled with data.

Voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active "L"

by command input. This pin outputs a synchro signal for voice data input when non-use of FIFO

is selected.

"H" level indicates that FIFO memory is full of data. This pin is "H" and data cannot be written in

FIFO memory. Active "H" can be changed to active "L" by command input.

When DMA transfer is selected, "H" level DREQR outputs a signal to request a DMA transfer.

Active "H" can be changed to active "L" by command input.

When stereo playback is selected and CH is "H", voice data is written in right FIFO memory, and

the EMP, MID or FUL pin outputs the status of right FIFO memory.

When CH is "L", data is written in right FIFO memory, and the EMP, MID or FUL pin outputs the

status of left FIFO memory. Set this pin to "L" during monophonic playback.

When DMA transfer and stereo playback are selected, DACKR is selected. In this case, DACKR

outputs a DMA transfer acknowledge signal. When DACKR is "L", the IOW signal is accepted.

Active "L" can be changed to active "H" by command input.

When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer.

Active "H" can be changed to active "L" by command input.

DACKL inputs a signal when DMA transfer is permitted by the DMA controller. When DACKL

is "L", IOW signal is accepted. When stereo playback is selected, DACKL is a DMA transfer

acknowledge signal for left FIFO memory. Active "L" can be changed to active "H" by command

input. If DMA transfer is not used, set this pin to "H" level.

D15-D8

I/O

D7-D0

I/O

D/C

BUSY

EMP

MID

FUL/DREQR

CH/DACKR

DREQL

DACKL

5/9

MSM9842

¡ Semiconductor

FEDL9842-02

PIN DESCRIPTIONS

Symbol

Type

Description

16-bit serial data output pin when external DAC is used.

Synchronizing clock for 16-bit serial data input when external DAC is used.

Digital power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and

DGND pin.

DASD

SOCK

XT
XT

VCK

RESET

TEST0

TEST1

TEST2

TEST4

AOUTL

AOUTR

Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT

pin open.

Outputs sampling frequency selected at playback. This sampling frequency is used as a

synchronizing signal when external DAC is used.

When this pin is "L", the LSI is initialized.

Pins for testing. Set the pins to "L".

Pin for testing. Set the pin to "OPEN".

Left side output pin for built-in LPF. This is the output pin of playback wavefroms, and is

connected to the amplifier for driving speakers.

Right side output pin for built-in LPF. This is the output pin of playback wavefroms, and is

connected to the amplifier for driving speakers.

DGND

Digital GND pin.

Analog power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and

AGND pin.

AGND

Analog GND pin.

IOW

Signal to write external memory data to MSM9842 during DMA transfer.

If DMA transfer is not used, set this pin to "H" level.

TEST3

Pin for testing. Set the pin to "H".

6/9

MSM9842

¡ Semiconductor

FEDL9842-02

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Power Supply Voltage

Ta=25°C

0.3 to + 7.0

Input Voltage

Ta=25°C

0.3 to V

+ 0.3

Storage Temperature

STG

55 to + 155

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Range

Unit

Power Supply Voltage

DGND=AGND=0V

2.7 to 5.5

Operating Temperature

40 to +85

°C

Master Clock Frequency

OSC

4.0 to 6.0

MHz

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

¥0.85

¥0.2

=40 mA

0.3

=2 mA

0.45

IH1

IH=

IH2

IH=

IL1

IL=

DGND

IL2

IL=

DGND

=AV

=4.5 to 5.5 V,

At power down, without load

Ta=40 to +70°C

DDS

At power down, without load

Ta=40 to +85°C

High-level Input Voltage

Low-level Input Voltage

High-level output Voltage

Low-level output Voltage

High-level Input Current (*1)

High-level Input Current (*2)

Low-level Input Current (*1)

Low-level Input Current (*2)

Operating Current consumption

Stanby Current consumption

=AV

=2.7 to 5.5V, DGND=AGND=0V, Ta=40 to +85°C

High-level Input Current (*3)

IH3

=AV

=4.5 to 5.5 V, V

150

300

=AV

=2.7 to 3.6 V, V

100

fosc=4.096 MHz, whithout load

=AV

=2.7 to 3.6 V,

fosc=4.096 MHz, whithout load

*1 Applicable to input excluding XT pin.
*2 Applicable to XT pin.
*3 Applicable to TEST0, TEST1.

8/9

MSM9842

¡ Semiconductor

FEDL9842-02

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

Package material
Lead frame material
Pin treatment
Package weight (g)

Oki Electric Industry Co., Ltd.

Rev. No./Last Revised

Epoxy resin
42 alloy
Solder plating (5 mm)
0.43 TYP.
4/Nov. 28, 1996

Mirror finish

QFP56-P-910-0.65-2K

9/9

MSM9842

¡ Semiconductor

FEDL9842-02

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM9842

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MSM9842