¡ Semiconductor

VOICE SYNTHESIS LSI with on-chip FIFO Memory

MSM9844

Version1.20, Jun.16, 1999

Page1

General Description

Features

MSM9844 is a Voice Synthesizer LSI with on-chip FIFO memory.

A newly developed synthesis algorithm, OKI ADPCM2, promises superb sound quality. The LSI is fully

controllable from an external CPU via 16/8-bit bus interface.

MSM9844 is an ideal choice for application systems where such non-microchip data storage as CD ROM is

used..

· 16/8-bit Bus Interface

· On-chip FIFO Memory Capacity : 1024 Bits 23 ms Buffering

When Sampling Frequency at 8.0 kHz, 4-bit ADPCM and Monaural Playback selected

· Synthesis Algorithms for User's Selection

4,5,6,7,8-bit OKI ADPCM2

4-bit OKI ADPCM

8/16-bit Straight PCM

8-bit OKI Non-Linear PCM

· Oscillation Clock Frequency: 16.9344 MHz / 24.576 MHz

· Sampling Frequency:

11.025 kHz, 22.05 kHz, 44.1 kHz at f

OSC

=16.9344 MHz

4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz, 48.0 kHz at f

OSC

=24.576 MHz

· Sound Level Control (8 levels, 0dB ~ -21dB)

· Built-in 14-bit D/A Converter

· 3 types of Serial Interface for External DAC

· Sampling Rate Conversion Function

· Packaging: 56-pin Plastic QFP (QFP56-P-910-0.65-2K)

Product Code: MSM9844GA

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¡ Semiconductor

MSM9844

Pin Description

When 8-bit bus interface selected, you can define, by using a command,
these pins as input/output to/from external memory. When no definition
made, these pins are output mode.
When 16-bit bus interface selected, they are one half of bi-directional data
bus for data input / output from/to external micro-controller and memory.

Another half of bi-directional data bus for data input/output from/to external
micro-controller and memory and for status output.

WRITE pulse input pin. Input "L" pulse before you can enter command
and data to D15 to D0 pins.

READ pulse input pin. Input "L" pulse before the LSI can output status and
data to D15 to D0 pins.

With this pin at "L" level, the LSI accepts WRITE or READ pulse input. At
"H" level the LSI would not accept WRITE or READ pulse.

While this pin being held "H", D15 to D0 pins are enabled to input/output
sound data. While this pin being held "L", D7 to D0 pins are enabled to
input a command or output status data.

Output "L" level during playback/PAUSE operation.

Output "L" level when the LSI is ready to accept a command.

"H" level output from this pin indicates FIFO memory is empty. You can
change this pin to "L" active by a command input.

"H" level output from this pin indicates FIFO memory is more than half.
During playback, voice synthesis starts when MID changes to "H" level.
You can change this pin to "L" active by a command input. This pin
outputs a synchro signal for voice data input / output when non-use of FIFO
is selected.

"H" level output from this pin indicates FIFO memory is full. During
playback operation this pin is held "H" and FIFO memory is write -disabled.
You can change this pin to "L" active by a command input.
When DMA Transfer and stereo-playback selected by the command input,
the output from this pin becomes DMA Transfer request signal. The pin
outputs "H" when the right channel FIFO memory is empty. You can
change this pin to "L" active by a command input.

When stereo-playback selected, write sound data to the right channel FIFO
at "H" level, while data to the left channel FIFO at "L" level. When monaural
playback selected, keep this pin "L". You can change this pin to "L" active by
a command input.
When DMA Transfer and stereo-playback selected by the command input,
this pin acknowledges the right channel DMA Transfer permission signal.
With this pin at "L" level the LSI enabled the /IOW pin to accept the signal.
You can change this pin to "H" active by a command input.

Output "H" level to represent DMA Transfer request signal when FIFO gets
empty. If stereo-playback selected, the pin outputs "H" level to represent
DMA Transfer request signal when the left channel FIFO gets empty.

DMA Transfer Permission Acknowledgement signal. With this pin at "L"
level the LSI enables the /IOW pin to accept the signal. When stereo-
playback selected, the pin acknowledges DMA Transfer permission signal
for the left channel FIFO. You can change this pin to "H" active by a
command input. When DMA Transfer is not in use, keep the pin "H".

Pin No.

Symbol

I / O

Description

I / O

D15 to D8

D7 to D0

D / C

BUSY

CBUSY

EMP

FUL /

DREQR

CH /

DACKR

DREQL

DACKL

11 - 14
16 - 19

1 - 4
6 - 9

MID

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¡ Semiconductor

MSM9844

When DMA Transfer selected, the signal to start writing external memory
data to the MSM9844 is entered to this pin.
When DMA Transfer is not use, keep the pin "H".

16-bit serial data output pin when the external DAC is in use.

Synchronizing clock signal for 16-bit serial data input/output when the
external DAC is in use.

Pins wired to the oscillator, When the external clock is used, input the
clock signal to the XT pin and keep the /XT pin open.

Input/Output the sampling frequency in use. The signal is used as the
synchronizing signal when the external DAC is in use.

"L" level input to this pin turns the LSI to the initial status.

Pins for testing the LSI. Keep these pins "L".

The left channel output from the built-in LPF. Analog waveform output can
be directly connected to an amplifirer to drive a speaker.

The right channel output from the built-in LPF. Analog waveform output can
be directly connected to an amplifirer to drive a speaker.

Digital power supply pin. Insert a 0.1µF or larger bypass capacitor
between this pin and the DGND pin.

Digital GND pin.

Analog power supply pin. Insert a 0.1µF or larger bypass capacitor
between this pin and the AGND pin.

Analog GND pin.

Pin No.

Symbol

I / O

Description

I / O

IOW

SIOCK

DASD

XT
XT

VCK

RESET

TEST0,1
TEST2,3

AOUTL

AOUTR

AGND

DGND

54
55

47,48
45,26

21,49

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¡ Semiconductor

Absolute Maximum Ratings

Recommended Operating Ranges

DC Characteristics

MSM9844

Parameter

Power Supply Voltage

Conditions

STG

Symbol

Storage Temperature

- 0.3 to V

+ 0.3

- 0.3 to + 7.0

Unit

Rating

Ta = 25°C

- 55 to + 150

°C

Input Voltage

(GND = 0 V)

Parameter

Power Supply Voltage

Conditions

OSC

Symbol

Master Clock Frequency

- 40 to + 85

+ 4.5 to + 5.5

Unit

Rating

24.576

°C

MHz

Operating Temperature

(GND = 0 V)

DGND = AGND = 0V

Parameter

"H" Input Voltage

Conditions

Symbol

Unit

Min.

"H" Output Voltage note 1

= AV

= + 4.5 V to + 5.5 V

DGND = AGND = 0 VTa = - 40 to + 85 °C

Max.

Typ.

x 0.85

note 1) Applies to output pins excluding XT pin.
note 2) Applies to XT pin.
note 3) Applies to input pins excluding XT pin.
note 4) Applies to XT pins .
note 5) Applies to input pins without pull-up-register excluding XT pin.
note 6) Applies to input pins within pull-up-register excluding XT pin.

"L" Input Voltage

"L" Output Voltage note 1

"H" Input Current note 3

"H" Input Current note 4

"L" Input Current note 5

"L" Input Current note 4

"L" Input Current note 6

Operating Current Consumption

Standby Current Consumption

IH2

OL1

IIH1

OH1

IIL1

IIL2

IIL3

IDD

IDDS

OH = - 40 µA

OL = 2 mA

IH =

IL =

GND

IL =

GND

IL =

GND

OSC =

24.576 MHz

without load

At power down

without load

Ta = - 40 to + 70 °C

At power down

without load

Ta = - 40 to + 85 °C

x 0.15

- 0.3

0.45

- 10

- 20

- 400

- 20

2 mA

µA

"H" Output Voltage note 2

"L" Output Voltage note 2

OL2

OH2

OH = - 40 µA

OL = 2 mA

- 0.3

0.8

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¡ Semiconductor

AC Characteristics

MSM9844

Parameter

RESET Pulse Width

RSTW

Symbol

Unit

Min.

µs

= AV

= + 4.5 V to + 5.5 V

DGND = AGND = 0 VTa = - 40 to + 85 °C

Max.

Typ.

RSTD

Setup Time after Rise of Power Supply for Fall of RESET

DRE

RSTS

DRF

CRC

120

500

160

Time to Active First RD, WR after Fall of RESET

RD Pulse Width

CS, D/C, CH Setup and Hold Time for RD

Time from Fall of RD till Data and Status Definition

Time from Fall of RD till Data Float

Time from Rise of RD till Fall of Next RD

IOW Pulse Width

WR Pulse Width

CS, D/C, CH Setup and Hold Time for WR

Setup Time of Data, and Command for Rise of WR

Hold Time of Data, and Command for Rise of WR

Time from Rise of WR till Fall of Next WR

Setup and Hold Time of DACK for IOW

Setup Time of Data for Rise of IOW

Hold Time of Data for Rise of IOW

Time from Rise of IOW till Fall of Next IOW

DWS

DWH

CWC

IOWW

IOWS

IOWH

IOWC

160

300

500

200

100

500

160

100

200

Analog Characteristics

Parameter

D/A Output Relative Error

Conditions

DAE

Symbol

Unit

Min.

= AV

= + 4.5 V to + 5.5 V

DGND = AGND = 0 VTa = - 40 to + 85 °C

Max.

Typ.

AOUT

AOUT Output Load Resistance

No Load

Functional Description

· Voice Synthesis Algorithms

To meet user's varying sound quality requirements, 4 different types of voice synthesis algorithms are

available for user's selection as follows:

1. OKI 4-bit ADPCM

2. OKI 4/5/6/7/8-bit ADPCM2

3. 8/16-bit Straight PCM

4. 8-bit Non-linear PCM

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MSM9844

· Data Formats When 8-bit Bus Selected
1. Oki 4-bit ADPCM, Oki 4-bit ADPCM2

2. Oki 5-bit ADPCM2

3. Oki 6-bit ADPCM2

4. Oki 7-bit ADPCM2

5. Oki 8-bit ADPCM2, 8-bit Linear PCM, and 8-bit Oki Non-Linear PCM

6. 16-bit Linear PCM

MSB1

MSB3

3SB1

3SB3

2SB1

2SB3

LSB1

LSB3

MSB2

MSB4

3SB2

3SB4

2SB2

2SB4

LSB2

LSB4

MSB1

MSB2

4SB1

4SB2

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

MSB1

MSB2

5SB1

5SB2

4SB1

4SB2

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

MSB1

MSB2

6SB1

6SB2

5SB1

5SB2

4SB1

4SB2

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

MSB1

MSB2

7SB1

7SB2

6SB1

6SB2

5SB1

5SB2

4SB1

4SB2

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

MSB1

8SB1

15SB1

7SB1

14SB1

6SB1

13SB1

5SB1

12SB1

4SB1

11SB1

3SB1

10SB1

2SB1

9SB1

LSB1

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¡ Semiconductor

MSM9844

· Data Formats When 16-bit Bus Selected
1. Oki 4-bit ADPCM, Oki 4-bit ADPCM2

2. Oki 5-bit ADPCM2

3. Oki 6-bit ADPCM2

4. Oki 7-bit ADPCM2

5. Oki 8-bit ADPCM2, 8-bit Linear PCM, and 8-bit Oki Non-Linear PCM

6. 16-bit Linear PCM

D15

MSB1

MSB3

D14

3SB1

3SB3

D13

2SB1

2SB3

D12

LSB1

LSB3

D11

MSB2

MSB4

D10

3SB2

3SB4

2SB2

2SB4

LSB2

LSB4

D15

D14

D13

D12

MSB1

MSB2

D11

4SB1

4SB2

D10

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

D15

D14

D13

MSB1

MSB2

D12

5SB1

5SB2

D11

4SB1

4SB2

D10

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

D15

D14

MSB1

MSB2

D13

6SB1

6SB2

D12

5SB1

5SB2

D11

4SB1

4SB2

D10

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

D15

MSB1

MSB2

D14

7SB1

7SB2

D13

6SB1

6SB2

D12

5SB1

5SB2

D11

4SB1

4SB2

D10

3SB1

3SB2

2SB1

2SB2

LSB1

LSB2

D15

MSB1

8SB1

D14

15SB1

7SB1

D13

14SB1

6SB1

D12

13SB1

5SB1

D11

12SB1

4SB1

D10

11SB1

3SB1

10SB1

2SB1

9SB1

LSB1

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¡ Semiconductor

MSM9844

· Playback Operation When Micro-controller Interface in Use

(1) Define a synthesis algorithm, sampling frequency, bus width, playback mode, and etc. as required, by

using an appropriate command.

(2) To start playback, input the PLAY command. Or, write one word data to FIFO, letting the LSI ready for

playback, and turn the EMP pin to "L" to initiate playback.

(3) Status shifting indicated by the EMP and FUL pins

(EMP="L", MID="L", FUL="L")

Indicates the state where no one-word data is written to FIFO memory.

(EMP="H", MID="L", FUL="L")

Indicates the state where one-word or more data is written to FIFO memory.

(EMP="L", MID="H", FUL="L")

Indicates the state where data is written to more than half of FIFO memory.

(EMP="L", MID="H", FUL="H")

Indicates the state where FIFO memory is full.

(4) Ending playback

When a write cycle is not completed within pre-fixed time, the LSI deems it as a completed write cycle and

ends playback.

· FIFO Memory's Status Shift

: Empty Block

: Write Done Block

: Block Being Read

EMP=H

MID =L
FUL =L

EMP=L
MID =L
FUL =L

EMP=L

MID =H

FUL =L

EMP=L

MID =H
FUL =H

EMP=L
MID =L
FUL =L

EMP=H

MID =L
FUL =L

Start Playback

Playing Back

End Playback

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MSM9844

MSM9844 issues a DMA Transfer request to the DMA Controller, and starts data transfer in sync with

transfer cycles of the DMA Controller after acknowledging a DMA Transfer permission. Enable/Disable of

DMA Transfer function can be defined by using the command.

The DREQL pin rises to "H" at the Start Playback command, requesting a write cycle to FIFO memory, and

maintains "H" level until FIFO gets full.

At the point of time when one-word data is written to FIFO, playback starts. When FIFO becomes half, the

DREQL returns to "H".

The pin is able to acknowledge a DMA Transfer permission signal from the DMA Controller. The /IOW pin

is enabled with the /DACKL pin at "L".

During the period of /DACKL="L" , controls using the /RD, /WR, CS, D/C pins are disabled. Therefore,

setups of MSM9844 has to be completed before you can enter into a DMA Transfer cycle.

</IOW Pin>

The pin is enabled at /DACKL="L", and thereafter controlled by the DMA Controller. The /IOW is an input pin

to enable data transfer from external memory to the MSM9844.

You can suspend on-going playback by using the Pause command. At this time, you may suspend Write

operation to FIFO memory while in pause. Write is resumed from where having been paused, when

playback restarts.

Or, you may continue Write operation to FIFO memory according to the EMP, MID and FUL pins' status.

You can stop on-going playback by using the STOP command. When this happens, FIFO memory is

cleared to return to the initial status.

·Playback Operation When DMA Interface in Use

·Pausing Playback

·Stopping On-going Playback

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MSM9844

You can select one of the following three types of serial interface by using the command.

1. MSB First (Master/Slave)

2. LSB First (Master/Slave)

3. IIS Format (Master/Slave)

·Serial Port Data Format

(1) MSB 16 bit (J1 = 0, J0 = 0)

1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516

VCK

SIOCK

DASD

MSB

LSB MSB

LSB

LEFT

RIGHT

(2) LSB 16 bit (J1 = 0, J0 = 1)

1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516

VCK

SIOCK

DASD

LSB

MSB LSB

MSB

LEFT

RIGHT

(3) MSB, VCK Inverted, and DASD Shifted 1 bit16 bit (J1 = 1, J0 = 1)

1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516

VCK

SIOCK

DASD

MSB

LSB MSB

LSB

LEFT

RIGHT

Page18

¡ Semiconductor

MSM9844

Command Code Format

Function

NOP

Sampling RATE Conversion

PLAY

STOP

PAUSE

VOLUME

POWER DOWN

SELECT ALGORITHM

ANALOG SETUP 1

ANALOG SETUP 2, BUS WIDTH

DEFINE FIFO SIZE

SIGNAL OUTPUT FORMAT

SELECT DMA TRANSFER

SELECT Serial Port FORMAT

NOP

TEST

X = Don't Care

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¡ Semiconductor

MSM9844

1) NOP Command

Function

NOP

No particular function

2) Sampling RATE Conversion Command

Function

Sampling RATE Conversion

By using this command you can select enable / disable Sampling Rate Conversion and input sampling

frequency when enable this function. Note that this command is enable with monaural playback.

Function

NOT used Sampling Rate Conversion *

Used Sampling Rate Conversion

* Default

Sampling Frequency

4.0 kHz

8.0 kHz

6.4 kHz

12.8 kHz

16.0 kHz

Page20

¡ Semiconductor

MSM9844

3) PLAY Command

Function

PLAY

To start playback, use this command. You can select either the left or right channel playback with C3, as

well as sampling frequency with S2 ~ S0. When stereo-playback is selected, data at C3 is disregarded. You

can select only one sampling frequency.

When the rate converter is used, the frequency defined by S2 ~ S0 is output sampling frequency.

Function

PLAY LEFT *

PLAY RIGHT

* Default

XT = 16.9344MHz

11.025 kHz *

22.05 kHz

Sampling Frequency

XT = 24.576MHz

16.0 kHz *

32.0 kHz

44.1 kHz

4.0 kHz

8.0 kHz

6.4 kHz

12.8kHz

48.0 kHz

2.76 kHz

5.51 kHz

4.41 kHz

8.82 kHz

* Default

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¡ Semiconductor

MSM9844

4) STOP Command

Function

STOP

Use this command to stop playback. After the command input, FIFO data is cleared. C3 allows you to

select the left channel or the right channel playback to be stopped. When you want to stop playback on both

channels, use C2.

Function

STOP LEFT *

STOP RIGHT

* Default

STOP LEFT and RIGHT

5) PAUSE Command

Function

PAUSE

Use this command to temporarily suspend on-going playback. C1 enables you to control PAUSE/reset.

You can select either the left channel or right channel with C3. When you want to suspend playback on both

channels, use C2.

Function

PAUSE LEFT *

PAUSE RIGHT

* Default

PAUSE LEFT and RIGHT

Function

PAUSE

RESUME

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¡ Semiconductor

MSM9844

6) VOLUME Command

Function

VOLUME

You can control sound level of playback by using this command. C3 is to select either the left channel or

right channel, and V2 ~ V0 is to select a proper sound level.

Function

LEFT VOLUME CONTROLL

RIGHT VOLUME CONTROLL

VOL.VALUE

0 dB *

- 3 dB

- 6 dB

- 9 dB

- 12 dB

- 15 dB

- 18 dB

- 21 dB

* Default

7) POWER DOWN Command

Function

POWER DOWN

Inputting this command puts the LSI into power down status, where the LSI stops oscillation and minimize

power consumption. Output from the AOUTL and AOUTR dropped down to the GND level instantaneously.

W3 enables you to control power down/reset and W2 to define whether initialize the LSI or not.

Function

RESUME POWER DOWN

POWER DOWN

Function

NOT initialize the LSI

Initialize the LSI

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MSM9844

10) Analog Setup 2 Command

Function

ANALOG SETUP 2

You can select enable/disable driving amplifier and enable/ disable LPF for the AOUTL and AOUTR pins

with A3 and A2.

You can also select a data bus width with E1 and E0, and when 8-bit bus selected, you can further select

whether to use D15 ~ D8 pins for sound data transfer.

Function

USED Output Amplifire *

NOT USED Output Amplifire

Function

USED internal LPF *

NOT USED intrenal LPF

Function

8bit BUS Width, D15 to D8 unused *

* Default

8bit BUS Width, D15 to D8 used

16bit BUS Width

11) Define FIFO Size Command

Function

DEFINE FIFO SIZE

By using this command you can define the size of FIFO memory.

8bit BUS Width

128 bytes

64 bytes

32 bytes

NOT USED FIFO Memory

16bit BUS Width

64 words

32 words

16 words

Page26

¡ Semiconductor

MSM9844

12) Signal Output Format Command

Function

SIGNAL OUTPUT FORMAT

By using this command you can select output format from the EMP, FUL and DREQL/R pins, and input

format to the DACKL/R pins.

Function

"H" Active for EMP, MID, and FUL Output *

"L" Active for EMP, MID, and FUL Output

Function

"H" Active for DREQL, and DREQR Output *

"L" Active for DREQL, and DREQR Output

Function

No particular function

NOT USED

* Default

Function

"L" Active for DACKL, and DACKR Input *

"H" Active for DACKL, and DACKR Input

13) Select DMA Transfer Command

Function

SELECT DMA TRANSFER

By using this command you can select enable/disable DMA Transfer and DMA Transfer mode.

Function

Not used DMA Transfer *

DMA Transfer by Single Mode

DMA Transfer by Block Mode

* Default

Page31

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MSM9844

Mirror finish

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5µm or more

0.43 TYP.

QFP56-P-910-0.65-2K

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code, and desired mounting conditions
(reflow method, temperature and times).

Package Dimensions

(Unit : mm)

Page32

¡ Semiconductor

MSM9844

NOTICE

1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is up-to-
date.

2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit and assembly designs.

3. When designing your product, please use our product below the specified maximum ratings and within
the specified operating ranges including, but not limited to, operating voltage, power dissipation, and
operating temperature.

4. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party's right which may result
from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for
commercial applications (e.g. office automation, communication equipment, measurement equipment,
consumer electronics ,etc.). These products are not authorized for use in any system or application that
requires special or enhanced quality and reliability characteristics nor in any system or application where
the failure of such system or application may result in the loss or damage of property, or death or injury to
humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including life support and maintenance.

7. Certain products in this document may need government approval before they can be exported to
particular countries. The purchaser assumes the responsibility of determining the legality of export of these
products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

9. MS-DOS is a registered trademark of Microsoft Corporation.

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