s
s
Oki Semiconductor
Contents
Description................................................................................................................................................................ 1
Features .....................................................................................................................................................................1
Signal Descriptions ..................................................................................................................................................4
Functional Description ............................................................................................................................................5
Functional Modules ...........................................................................................................................................5
Data Path Interface ......................................................................................................................................5
Asynchronous Transfer Request Block ....................................................................................................5
Isochronous Transfer Request Block ........................................................................................................5
Read-Write Request Block .........................................................................................................................5
Annex J Request Block ................................................................................................................................5
Transmitter and Receiver Block ................................................................................................................5
Byte-wide Serializer and Deserializer ......................................................................................................6
Quadlet Serializer and Deserializer ..........................................................................................................6
Quadlet Buffer .............................................................................................................................................6
Link Core Controller State Machine .........................................................................................................6
CRC Generator and Checker .....................................................................................................................6
1
Oki Semiconductor
W812 IEEE 1394 Link Layer Controller
0.35
m Technology Mega Macrofunction
DESCRIPTION
The W812, Oki Semiconductor's 1394 Link Layer Controller, is IEEE 1394-1995 compliant and features an
embedded high-performance application bus interface. This device performs data packaging according
to the IEEE 1394-1995 Standard, and bidirectional asynchronous/isochronous data transfers to/from an
IEEE 1394 serial bus physical layer (PHY) device.
The W812 is optimized for use as a peripheral link layer controller. The application bus interface, which
transfers data between a FIFO and the host controller, is designed for highly efficient transport. Oki also
provides an optional FIFO controller, the W812-F to readily interface with the W812.
Oki's W812 accommodates different application needs by using a flexible architecture which to support
both asynchronous and isochronous data transfers or only asynchronous data transfers. This technology
give system designers the maximum flexibility in their design.
FEATURES
Recommended Operating Conditions (V
SS
= 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
V
DD
2.7
3.3
3.6
V
Operating temperature
T
j
-40
+25
+85
C
Mega Macrofunction Characteristics
Mega Macrofunction
Description
Logic Gate Count
Logic Pin Count
W812
IEEE 1394 Link Layer Controller
12K
95
Compliant with IEEE 1394-1995 Standard Link Layer
Controller
Compatible with Texas Instruments' Physical Layer
Controllers
Offers programmable FIFO channel for asynchronous
and isochronous transmission and general reception
Supports transfer rates of 100, 200, and 400 Mbps
Uses flexible architecture to support both
asynchronous and isochronous data transfers or only
asynchronous data transfers
Offers high performance application bus interface
Has 32-bit cyclic redundancy check (CRC) for
transmission and reception of 1394 packets
s
W812 IEEE 1394 Link Layer Controller
s
2
Oki Semiconductor
Figure 1. W812 Logic Symbol
Figure 2. W812 Block Diagram
DPBdata
DPBdrive
DPBValid
DPBValid_en
DPBFifoStatus [0:2]
DPBadr [0:12]
DPBadr_en
DPBWrite
DPRegLink
DPBWait
MasterReset
CycleIn
CycleOut
Lclk
AnxJLReg
Ctlln [0:1]
CtlOut [0:1]
CtlTriEnb
AnxJDout [0:7]
DataTriEnb [0:7]
PHY-Link Interface
Application Bus Interface
W812
DPRegWrLink
DPAckLink
DPStallLink
AnxJDin [0:7]
Direct
LinkPowerOn
Isochronous Control
DPIF
Quadlet
Buffer
Quadlet
Serializer
and
Deserializer
Transmitter and Receiver
AnxJRequest
Async
Transfer
Request
Isochronous
Transfer
Request
Read and
Write
Request
Byte-wide
Serializer
and
Deserializer
PHY-Link
Interface
Link Core
Controller
Application
Bus
Interface
CRC
PDF 
ZIP
