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Электронный компонент: Z684

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1
OKI SEMICONDUCTOR
Z684 PCI Bus Controller
0.5
m Technology Mega Macrocell
DESCRIPTION
The PCI Bus Controller Mega Macrocell is a featured element in OKI's 0.5
m Sea of Gates (SOG) and Cus-
tomer Structured Array (CSA) families. Designers can significantly reduce design and simulation effort
by using OKI's Z684 on PCI bus interface projects. The Z684 is fully compliant with the PCI Bus Revision
2.0 specification.
OKI's Z684 provides a PCI interface, data FIFO and control, and a configuration block in a highly inte-
grated module for system design interfaces that implement the PCI bus protocol. The Z684 connects
between an external PCI bus and a peripheral device's internal 486-like bus. Both buses are 32 bits wide
and operate at clock frequencies of up to 33 MHz. Two 4x36-bit write FIFOs enhance system performance.
The cell also supports address and data parity generation and error reporting. PCI-compliant I/O buffers
are available to connect the Z684 to a PCI bus, and are added when the design is implemented in an SOG
array or CSA. By using the Z684, the users may speed up the design cycle and accelerate market entry for
the end product.
FEATURES
Supported ASIC Families
Family Name
Family Type
MSM10R0000
Sea of Gates
MSM13R0000
Sea of Gates
MSM98R000
Customer Structured Array
Highly integrated interfaces between
customer's application specific design
module and PCI bus
Compliant with PCI Bus Revision 2.0
specification
Internal, i486-like 32-bit address and data bus
interface, with byte-select-enable control
Two 4x36-bit address, data and byte-enable
write FIFOs
32-bit PCI address and data bus interface
with byte-select-enable control
3-V operation
Built-in internal 64-byte PCI configuration
registers, which can be accessed both from
PCI and module buses
Built-in memory and I/O address decoding
Burst write mode operation on both PCI and
module interfaces
Full support for PCI master and slave
functions
Full address parity generation, data parity
generation and error checking and correction
(ECC)
Synchronous operation at up to 33 MHz for
both the PCI and module interfaces
s
Z684 PCI Bus Controller
s
2
OKI SEMICONDUCTOR
Recommended Operating Conditions (V
SS
= 0V)
Parameter
Symbol
Rated Values
Unit
Min.
Typ.
Max.
Power supply voltage
V
DD
2.7
3.3
3.6
V
Operating temperature
T
j
-40
+25
+85
C
Mega Macrocell Characteristics
Mega Macrocell
Description
Logic Gate Count
Number of Mega Macrocell Pins
Z684
PCI Bus Controller
21,600
269
Figure 203. Logic Symbol
PADSB
PBLASTB
PRDYB
PM_IOB
PD_CB
PWR_RDB
PHOLD
PBOFFB
PA[31:0]
PD[31:0]
PBEB[3:0]
PCS[5:0]
REQB
EDEVSELB
EFRAMEB
EIRDYB
ELOCKB
ESTOPB
ETRDYB
EPAR
EPERRB
ESERRB
EAD
ECBEB
ODEVSELB
OFRAMEB
OIRDYB
OLOCKB
OSTOPB
OTRDYB
OPAR
OPERRB
OSERRB
OAD[31:0]
OCBEB[3:0]
MCLK
MRESET
MADSB
MBLASTB
MRDYB
MM_IOB
MD_CB
MWR_RDB
MLOCKB
MHLDA
MCS0
MCS1
MIDSELCS
MA[31:0]
MD[31:0]
MBEB[3:0]
PCLK
RSTB
GNTB
IDSEL
IDEVSELB
IFRAMEB
IIRDYB
ILOCKB
ISTOPB
ITRDYB
IPAR
IPERRB
ISERRB
IAD[31:0]
ICBEB[3:0]
s
Z684 PCI Bus Controller
s
3
OKI SEMICONDUCTOR
Figure 204. PCI Mega Macrocell Block Diagram
FIFO
Write/Read
Control
486-Like Bus
Master Control
Logic
PCI Bus
FIFO
Parity
Slave Control
Logic
Configuration
Register
Figure 205. PCI Mega Macrocell Application
INTERNAL PCI BUS:
Z684-PCI interface bus
Customer Application Module
MODULE BUS:
Module-Z684 Interface Bus
(i486-like bus protocol)
ASIC
Z684 Mega Macrocell
PCI I/O Buffer
PCI Bus
External Module I/O
s
Z684 PCI Bus Controller
s
4
OKI SEMICONDUCTOR
SIGNAL DESCRIPTIONS
The Z684 signals can be classified into two main groups:
Module Interface Signals
PCI Interface Signals
All Z684 signals are unidirectional and unbuffered.
Module Interface Signals
Module Interface Signals interface the Z684 with the customer's application module. Module Interface
Signals are either Z684 inputs or Z684 outputs.
Input signals (driven from the module to the Z684) start with an "M" prefix
Output signals (driven from the Z684 to the module) start with a "P" prefix
Low assertion-signals end with "B" suffix
The Module Interface Signals are derived from 486-like external bus signals and have the same function
as equivalent i486 signals.
Module Interface Signals
Signal
Type Assertion
Description
MCLK Input
Module Clock.
The MCLK signal synchronizes all bus cycles and control signals for module-Z684
transactions. The current version of the Z684 requires that both MCLK and PCLK are connected to the same
clock driver.
MRESET
Input
HIGH
Module Reset.
When asserted HIGH, MRESET resets all components related with Z684-PCI interface
control logic.
MADSB Input
LOW
Module Address Strobe
. When asserted LOW, MADSB indicates that the address on the MA[31:0] address
bus is valid. This signal also indicates the beginning of a bus cycle.
MBLASTB
Input
LOW
Module Burst Last
. When asserted LOW, MBLASTB indicates that the transaction cycle has entered the final
data phase.
MRDYB
Input LOW
Module Data Ready
. This signal indicates that the module has received valid data from the Z684 data bus,
PD[31:0].
MM_IOB
Input
Module Memory or I/O Select
. When asserted HIGH, memory access is selected. When asserted LOW, I/O
access is selected.
MD_CB
Input
Module Data or Code Select
. When asserted HIGH, the bus performs a data access cycle. When asserted
LOW, the bus performs a code access cycle.
MWR_RDB
Input
Module Write or Read.
This signal defines a write or read bus cycle. When asserted HIGH, the bus
performs a write cycle. When asserted LOW, the bus performs a read cycle.
MLOCKB Input
LOW
Module Lock Cycle Request
. When asserted LOW, the module performs a locked transaction.
This signal is not supported in the current version of the Z684 and must be tied inactive (HIGH).
MHLDA
Input
HIGH
Module Bus Hold Acknowledge
. When asserted HIGH, this signal indicates that the customer application
module is available to receive a transaction from the Z684. This signal is equivalent to the i486 bus signal
HLDA.
MCS0
Input
HIGH
Module Chip Select 0
. This signal indicates an access cycle to the internal configuration registers. When
asserted HIGH, the Z684's internal configuration registers are selected.
MCS1
Input
HIGH
Module Chip Select 1
. This signal indicates a PCI bus transaction. When asserted HIGH, this signal selects
external PCI memory or I/O, or PCI configuration register space.
s
Z684 PCI Bus Controller
s
5
OKI SEMICONDUCTOR
MIDSELCS
Input
HIGH
PCI Configuration Cycle Select
. This signal indicates that the module intends to access configuration
registers of a PCI device.
MA[31:0]
Input
Module Address Input Bus
. The MA[31:0] signals are the 32-bit input address bus from the module to the
Z684. The address is valid when MADSB is asserted LOW.
MD[31:0]
Input
Module Data Input Bus
. The MD[31:0] signals are the 32-bit input data bus from the module to the Z684.
MBEB[3:0]
Input
Module Byte Enable
. The MBEB[3:0] signals select the byte or bytes on the MD[31:0] data bus. The byte
is valid when corresponding MBEB[3:0] bit is asserted LOW.
PADSB
Output
LOW
Module Address Strobe Output
. When asserted LOW, the PADSB output signals that the address on the
PA[31:0] address bus is valid. The PADSB output also signals the beginning of a bus transaction.
PBLASTB
Output
LOW
Module Burst Last Output
. When asserted LOW, this signal indicates that the transaction has entered the
last data phase.
PRDYB
Output
LOW
Module Data Ready Output
. This signal indicates that the Z684 has received valid data from the module
data bus, MD[31:0].
PM_IOB
Output
Module Memory or I/O Select Output
. When asserted HIGH, memory access is selected. When asserted
LOW, I/O access is selected.
PD_CB
Output
Module Data or Code Select Output
. When the Z684 asserts PD_CB HIGH, the bus performs a data access
cycle. When the Z684 asserts PD_CB LOW, the bus performs a code access cycle.
PWR_RDB
Output
Module Write or Read Output
. This signal defines whether a write or read bus cycle takes place. When the
Z684 asserts PWR_RDB HIGH, the bus performs a WRITE cycle. When the Z684 asserts PWR_RDB LOW,
the bus performs a read cycle.
PHOLD
Output
HIGH
Module Hold Request Output
. When the Z684 intends to start a transaction targeting the module, the Z684
asserts PHOLD HIGH. The PHOLD signal is equivalent to the HOLD signal on the i486 bus.
PBOFFB
Output
LOW
Module Back-Off Output.
When asserted LOW, this signal indicates that the Z684 is requesting the module
to stop the current transaction.
PA[31:0]
Output
Module Address Output
.
This is the address bus output, driven from the Z684 to the module.
PD[31:0]
Output
Module Data Output
. The PD[31:0] signals are the 32-bit output data bus from the module to the Z684.
PBEB[3:0]
Output
Module Byte Enable Output.
These signals select the valid bytes on the PD[31:0] data bus. The byte is valid
when the corresponding PBEB[3:0] is asserted LOW.
PCS[5:0]
Output
PCI-to-Module
Chip Select. These outputs indicate that one of the address spaces in the base address
registers has been selected.
Module Interface Signals
(Continued)
Signal
Type Assertion
Description