Oxford Semiconductor Ltd.
Oxford Semiconductor 2001
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK OX16C954 rev B Data Sheet R1.0 November 2001
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141 Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
F
EATURES
Four independent full-duplex asynchronous 16C950
high performance UART channels
128-byte deep FIFO per transmitter and receiver
UARTs fully software compatible with industry
standard 16C55x type UARTs
Pin compatible with TL16C554 and ST16C654
Baud rates up to 15 Mbps in normal mode and
60Mbps in external 1x clock (isochronous) mode
Readable FIFO levels
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff characters, in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Readable in-band and out-of-band flow control status
Programmable special character detection
Infra-red (IrDA) receiver and transmitter option
5, 6, 7, 8 and 9-bits data framing
Detection of bad data in the receiver FIFO
Independent channel reset by software
Transmitter and receiver can be disabled
Transmitter idle interrupt
RS-485 buffer enable signals
Four byte device ID
Sleep mode (low operating current)
System clock up to 60 MHz at 5V, 50 MHz at 3.3V
5.0 volt or 3.3v operation*
68pin PLCC and 80pin TQFP package options.
*Only the 80pin TQFP package supports operation at 5v or 3.3v.
R
EV
B E
NHANCEMENTS
The OX16C954B is an enhanced, backward-compatible revision of the OX16C954 rev A. It uses the newer core as in the
OX16C950 rev B. The chief enhancements are as follows
All known errata fixed
Full TCR range from 4-16
Enhanced controls for sleep-mode sensitivity, ability to read FCR and Good Data Status
3.3V operation with 80 pin TQFP
Enhanced isochronous clocking options (optional inversions, DTR/DSR)
Hereafter OX16C954 rev B is simply referred to as OX16C954.
OX16C954 rev B
High Performance Quad UART with 128-byte FIFOs
Intel / Motorola Bus Interface
Oxford Semiconductor Ltd.
Oxford Semiconductor 2001
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK OX16C954 rev B Data Sheet R1.0 November 2001
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141 Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
D
ESCRIPTION
The OX16C954 is a single chip solution for 4 channel serial
add-in cards.
Each UART channel in the OX16C954 offers data rates up
to 15Mbps and 128-byte deep transmitter and receiver
FIFOs. Deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates.
Each UART channel is software compatible with the widely
used industry-standard 16C550 devices and compatibles,
as well as the OX16C95x family of high performance
UARTs. It is pin-compatible with the TL16C554, ST16C654
devices.
In addition to increased performance and FIFO size, the
UARTs also provide the full set of OX16C95x enhanced
features. These include improved flow controls such as
automated software flow control using Xon/Xoff and
automated hardware flow control using CTS#/RTS# and
DSR#/DTR# to prevent FIFO over-run.
Flow control and interrupt thresholds are fully
programmable and readable, enabling programmers to
fine-tune the performance of their system. FIFO levels are
readable to facilitate fast driver applications.
The addition of software reset enables recovery from
unforeseen error conditions allowing drivers to restart
gracefully. The OX16C954 supports 9-bit data frames used
in multi-drop industrial protocols. It also offers multiple
external clock options for isochronous applications, e.g.
ISDN, xDSL.
The OX16C954 is ideally suited to PC applications, such
as high-speed multi-port add-in cards that enable PC users
to take advantage of the maximum performance of
analogue modems or ISDN terminal adapters. It is also
suitable for any equipment requiring high speed
RS232/RS422/RS485 interfaces.
Fabricated in 0.6
m process, OX16C954 also has a low
operating current and sleep mode for battery powered
applications.
Data Sheet Revision 1.0 Page 3
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
FEATURES.................................................................................................................................................................................................1
REV B ENHANCEMENTS.........................................................................................................................................................................1
DESCRIPTION............................................................................................................................................................................................2
CONTENTS.................................................................................................................................................................................................3
1
PERFORMANCE COMPARISON ......................................................................................................................................................5
2
BLOCK DIAGRAM...............................................................................................................................................................................7
3
PIN INFORMATION .............................................................................................................................................................................8
4
PIN DESCRIPTIONS .........................................................................................................................................................................10
4.1
Further Pin Information ...........................................................................................................................................................15
5
MODE SELECTION...........................................................................................................................................................................16
5.1
450 Mode ....................................................................................................................................................................................16
5.2
550 Mode ....................................................................................................................................................................................16
5.3
Extended 550 Mode..................................................................................................................................................................16
5.4
750 Mode ....................................................................................................................................................................................16
5.5
650 Mode ....................................................................................................................................................................................16
5.6
950 Mode ....................................................................................................................................................................................17
6
REGISTER DESCRIPTION TABLES...............................................................................................................................................18
7
RESET CONFIGURATION................................................................................................................................................................22
7.1
Hardware Reset.........................................................................................................................................................................22
7.2
Software Reset ..........................................................................................................................................................................22
8
TRANSMITTER AND RECEIVER FIFOS ........................................................................................................................................23
8.1
FIFO Control Register `FCR'...................................................................................................................................................23
9
LINE CONTROL & STATUS.............................................................................................................................................................24
9.1
False Start Bit Detection..........................................................................................................................................................24
9.2
Line Control Register `LCR' ....................................................................................................................................................24
9.3
Line Status Register `LSR'......................................................................................................................................................25
10
INTERRUPTS & SLEEP MODE .......................................................................................................................................................26
10.1
Interrupt Enable Register `IER'...............................................................................................................................................26
10.2
Interrupt Status Register `ISR'................................................................................................................................................27
10.3
Interrupt Description................................................................................................................................................................27
10.4
Sleep Mode.................................................................................................................................................................................28
11
MODEM INTERFACE........................................................................................................................................................................28
11.1
Modem Control Register `MCR'..............................................................................................................................................28
11.2
Modem Status Register `MSR'................................................................................................................................................29
12
OTHER STANDARD REGISTERS...................................................................................................................................................30
12.1
Divisor Latch Registers `DLL & DLM'....................................................................................................................................30
12.2
Scratch Pad Register `SPR'.....................................................................................................................................................30
13
AUTOMATIC FLOW CONTROL.......................................................................................................................................................31
13.1
Enhanced Features Register `EFR'........................................................................................................................................31
13.2
Special Character Detection...................................................................................................................................................32
13.3
Automatic In-band Flow Control ............................................................................................................................................32
13.4
Automatic Out-of-band Flow Control ....................................................................................................................................32
14
BAUD RATE GENERATION.............................................................................................................................................................33
14.1
General Operation.....................................................................................................................................................................33
14.2
Clock Prescaler Register `CPR'..............................................................................................................................................34
14.3
Times Clock Register `TCR' ....................................................................................................................................................34
14.4
Input Clock Options..................................................................................................................................................................36
Data Sheet Revision 1.0 Page 4
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
14.5
TTL Clock Mode ........................................................................................................................................................................36
14.6
External 1x Clock Mode...........................................................................................................................................................36
14.7
Crystal Oscillator Circuit.........................................................................................................................................................36
15
ADDITIONAL FEATURES ................................................................................................................................................................37
15.1
Additional Status Register `ASR'...........................................................................................................................................37
15.2
FIFO Fill levels `TFL & RFL'.....................................................................................................................................................37
15.3
Additional Control Register `ACR'.........................................................................................................................................37
15.4
Transmitter Trigger Level `TTL'..............................................................................................................................................39
15.5
Receiver Interrupt. Trigger Level `RTL'.................................................................................................................................39
15.6
Flow Control Levels `FCL' & `FCH' ........................................................................................................................................39
15.7
Device Identification Registers ..............................................................................................................................................39
15.8
Clock Select Register `CKS'....................................................................................................................................................40
15.9
Nine-bit Mode Register `NMR'.................................................................................................................................................40
15.10
Modem Disable Mask `MDM' ..............................................................................................................................................41
15.11
Readable FCR `RFC' ............................................................................................................................................................41
15.12
Good-data status register `GDS' .......................................................................................................................................41
15.13
DMA Status Register `DMS'................................................................................................................................................42
15.14
Port Index Register `PIX'.....................................................................................................................................................42
15.15
Clock Alteration Register `CKA' ........................................................................................................................................42
16
OPERATING CONDITIONS..............................................................................................................................................................43
17
DC ELECTRICAL CHARACTERISTICS .........................................................................................................................................44
17.1
5V Operation..............................................................................................................................................................................44
17.2
3.3V Operation...........................................................................................................................................................................45
18
AC ELECTRICAL CHARACTERISTICS .........................................................................................................................................46
18.1
5V Operation..............................................................................................................................................................................46
18.2
3.3V Operation...........................................................................................................................................................................47
19
TIMING WAVEFORMS......................................................................................................................................................................48
20
PACKAGE INFORMATION...............................................................................................................................................................50
21
ORDERING INFORMATION.............................................................................................................................................................52
NOTES ......................................................................................................................................................................................................53
CONTACT DETAILS................................................................................................................................................................................54
Data Sheet Revision 1.0 Page 5
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
1
P
ERFORMANCE
C
OMPARISON
Feature
OX16C954
16C454
16C554
16C654
16C750
Integrated Serial channels
4
4
4
4
1
Good-Data status
Yes
No
No
No
No
External 1x baud rate clock
Yes
No
No
No
No
Max baud rate in normal mode
15 Mbps
115 kbps 115 kbps 1.5 Mbps
1 Mbps
Max baud rate in 1x clock mode
60 Mbps
n/a
n/a
n/a
n/a
FIFO depth
128
1
16
64
64
Sleep mode
Yes
No
No
Yes
Yes
Auto Xon/Xoff flow
Yes
No
No
Yes
No
Auto CTS#/RTS# flow
Yes
No
No
Yes
Yes
Auto DSR#/DTR# flow
Yes
No
No
No
No
No. of Rx interrupt thresholds
128
1
4
4
4
No. of Tx interrupt thresholds
128
1
1
4
1
No. of flow control thresholds
128
n/a
n/a
4
n/a
Transmitter empty interrupt
Yes
No
No
No
No
Readable status of flow control
Yes
n/a
No
No
No
Readable FIFO levels
Yes
n/a
No
No
No
Clock prescaler options
248
n/a
n/a
2
n/a
Rx/Tx disable
Yes
No
No
No
No
Software reset
Yes
No
No
No
No
Device ID
Yes
No
No
No
No
9-bit data frames
Yes
No
No
No
No
RS485 buffer enable
Yes
No
No
No
No
Infra-red (IrDA)
Yes
No
No
Yes
No
Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices
Improvements of the OX16C954 over previous generations of PC UARTs:
Deeper FIFOs:
The OX16C954 offers 128-byte deep FIFOs for the
transmitter and receiver.
Higher data rates:
Transmission and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-"M N/8" circuitry. The
flexible prescaler allows users to select from a wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).
External clock option:
The receiver can accept an external clock on the DSR#
input. The transmitter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR# output.
In 1x mode, asynchronous data may be transmitted and
received at speeds up to 60 Mbps (see section 14.6).
Automatic flow control:
The UART automatically handles either or both in-band
(software) flow control (transmitting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS# or DSR#/DTR# modem control lines.
Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.
Power-down:
The device can be placed in `sleep mode' to conserve
power
Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.
Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmitter FIFO threshold and
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